fundamentals of analog to digital converters: part...
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Texas A&M University 1 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Jose Silva-MartinezTexas A&M University
January 2020
Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part III
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Texas A&M University 2 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
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Texas A&M University 3 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
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Fundamentals on ADCs: Part 3 Jose Silva-Martinez
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Fundamentals on ADCs: Part 3 Jose Silva-Martinez
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Fundamentals on ADCs: Part 3 Jose Silva-Martinez
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Fundamentals on ADCs: Part 3 Jose Silva-Martinez
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Fundamentals on ADCs: Part 3 Jose Silva-Martinez
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Fundamentals on ADCs: Part 3 Jose Silva-Martinez
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Fundamentals on ADCs: Part 3 Jose Silva-Martinez
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Fundamentals on ADCs: Part 3 Jose Silva-Martinez
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Texas A&M University 13 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
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Fundamentals on ADCs: Part 3 Jose Silva-Martinez
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Texas A&M University 15 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
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Texas A&M University 16 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
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Texas A&M University 17 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
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Texas A&M University 18 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
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Texas A&M University 19 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
What the problem is?
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Texas A&M University 20 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Signal Sampling Theorem
Time domain sampling
Frequency Spectrum
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Texas A&M University 21 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Sampling
CT
fclk
xc(t) x(n)C-D
xc(t)
t0
x(n)
n0 1 2 3 4
xc(nT)
T 2T 3T 4T T
( ) ( )nTtxnx c ==
( ) ( ) ( )Ω↔== ∑∞
−∞=
− jXznxezX cn
nj?
ω
DT( ) ( )Ω⇔ jXtx c
FT
c
![Page 22: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/22.jpg)
Texas A&M University 22 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Zero-Order Hold (ZOH)
xc(t)
t0
xSH(t)
t0 T 2T 3T 4T T
xc(nT)T
xc(nT)
t0 T 2T 3T 4T
t0
u(t) - u(t-T)T
T
1/T
T
w
( ) ( ) ( ) ( )[ ]∑∞
−∞=
−−−−⋅=n
cSH TnTtunTtunTxT
tx 1
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Texas A&M University 23 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
If your input signal is periodic, then
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Texas A&M University 24 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
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Texas A&M University 25 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
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Texas A&M University 26 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
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Texas A&M University 27 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Sampling
( ) ( ) ( ) ( ) ( )
( ) ( ) ( )
( ) ( )
( ) ( )∑
∑
Ω−Ω=Ω
=ΩΩ−Ω⇔
Ω⊗Ω=Ω
−⋅=⋅=
kscs
sk
s
FT
cs
ccs
kXT
jX
Tk
Tts
jSjXjX
nTttxtstxtx
1
2,221
πδππ
δ
( ) ( )
( ) ( )T
ksc
Ts
n
nj
kXT
jX
znxeX
ωω
ω
=Ω=Ω
∞
−∞=
−
∑
∑
Ω−Ω=Ω=
=
1
xc(t)
t0
s(t)
t0 T
δ(t-nT)
xs(t)
t0 T 2T 3T 4T T
xc(t)·δ(t-nT)
![Page 28: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/28.jpg)
Texas A&M University 28 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
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Texas A&M University 29 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Sampling
( )( )( ) ( ) ( )[ ]
( ) ( )
( )
( ) ( )∑∑
∑
∑
∑
∞
−∞=
−∞
−∞=
−
∞
−∞=
−−
→
∞
−∞=
+−−
→
∞
−∞=→
→
==
⋅
−=
−⋅=
−−−−⋅=
n
n
n
snTc
n
snTc
sT
0T
n
wnTssnTc0T
nc0T
SH0T
znxenTx
enTxsTe1
es1e
s1nTx
w1
wnTtunTtunTxT1FT
txFT
lim
lim
lim
limxSH(t)
t0 w→0
Area fixed
Impulse train
( ) ( ) ( )Ω↔== ∑∞
−∞=
− jXznxezX sn
njω
xs(t)
t0 T 2T 3T 4T T
xc(t)·δ(t-nT) Z Transform
./T1Fs,,πf,2ωDTπF,2ΩCT
==Ω==→=→
ωjezjs
T→0
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Texas A&M University 30 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
ZOH vs. Track-and-Hold
• Zero acquisition time• Infinite bandwidth• Not realistic
• T/2 acquisition time• Finite bandwidth• Practical
V(t)
t0 T 2TT
V(t)
t0T/2
T 2TH T H T H T H T H T
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Texas A&M University 31 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Notice in the afore equation that the delay due to exp(-jπfT) has being ignored
In practice, this term corresponds to a signal delay of T/2 seconds!
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Texas A&M University 32 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Check the case of the Gaussian PDF
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Texas A&M University 33 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
The sampling and Held operations generate alias frequency components and (sinc) signal distortion, respectively
Quantization generates harmonic distortion components when sinusoidal input signals are used
S/H and Quantization errors
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Texas A&M University 34 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Distortion due to S/H errors
( ) ( ) ( )tVtVtV error0PKd += ωsinThe S/H signal can be expressed as:
The first part of this equation does not generate any distortion since it is a pure sine wave function
The error signal is input dependent and non-linear! Fundamental component is at the signal frequencyIt can be expanded in a Fourier series and then the harmonic components can be found
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Texas A&M University 35 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Distortion due to quantization errors: Ramp
( ) ( )( ) ( ) ∆<≤∆−∆−−−∆
= Nv1Nif1Nv2
v inininε
In general, the quantization error can be expressed as:
For the case of a ramp input signal, then Vin(t)=Kt, then
You may want to find the Fourier series that represent this sawtooth error function to find the harmonic distortion components.
( ) ( ) ( ) ( )
( ) ( ) ( ) ( ) ∆<≤∆−∆−−∆
+−=
∆<≤∆−∆−−∆
+−=
NKt1Nif1N2
Kttor
NV1Nif1N2
tVt inin
ε
ε
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Texas A&M University 36 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
The problem is more complex for a sine function, the quantization error can be expressed as a kind of frequency modulation function See Van dePlassche , pp. 14:
Interestingly, this complex expression can be simplified for n-bit converters, leading to a very simple result for the third order harmonic distortion
Distortion due to quantization errors: Sinusoidal input
( ) ( )
oddispiffunctionBesselcomplexA
evenispif0A
pAv
p
p
1ppin
=
=
Φ= ∑∞
=
sinε
1n2componentlfundamentaofPowercomponentharmonicrd3ofPower3HD n51 ≥== − .
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Texas A&M University 37 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
For 10-Bit ADC, HD3 is in the range of -90.31 dB
HD3 reduces at a rate of -9dB per additional Bit
After 10 bits, this distortion can be easily ignored
Distortion due to quantization errors: Sinusoidal input
n5123HD .−≅
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Texas A&M University 38 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Distortion due to quantization errors: Sinusoidal input
Notice that SNR is over 20dB more relevant than HD3 for n>=7
n223IM −≅
For the case of intermodulation distortion using a couple of test tones, it is found
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Texas A&M University 39 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Clocking issues: Aperture errorLets consider a sinewave signal sampled with a S&H
Aperture error: reasons for this effect?
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Texas A&M University 40 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
( )( ) ( )
A0pk
0A0pkAin
0pk
Ain
tVErrorApertureMaxtcostVtv
dtdErrorAperture
tsinVsignalusoidalsinaofcaseIntv
dtdErrorAperture
ω
ωω
ω
=
=
=
=
Aperture error is proportional to signal slew-rate: Peak value times frequency
==
=
−minsignal
ApkA0pk
Ain
TtV2tVAEMax
tvdtdErrorAperture
πω
Aperture Error (Clock Jitter)
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Texas A&M University 41 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Clocking issues: Aperture errorObvious questions: What is the good, bad or ugly? Nature of tA?
i) Why this AE is relevant?ii) Is this a systematic error or a signal dependent
error?iii) What are the practical implications? More noise?
Distortion?iv) Can this error be eliminated?
Hint: Error is signal dependent in a non-linear fashion
( )
( ) ( )tcostVtvdtdAE
tsinVcasetheFor
0A0pkAin
0pk
ωω
ω
=
=
![Page 42: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/42.jpg)
Texas A&M University 42 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Clocking issues: Aperture errorDesigning for AE under the quantization error
( )
( )( )1Nsignal
A
1NsignalS
pk
signalA
S
signal
ApkA0pk
21
Tt
or2
T2
qV2
Tt
thenlevelonquantizatihalf2
qAEMaxFor
TtV2tVAEMax
+
+−−
−
≤
=
≤
=
==
π
ππ
πω
minmin
min
),(
( )levelsonquantizatiofNumber361
Tt
signal
A
*.≤Rule of Thumb:
![Page 43: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/43.jpg)
Texas A&M University 43 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
( )
( ) ( ) ( ) ( )
( ) ( )tcostfVAE
tcostfVtcostfVAE
tsinVcasetheFor
AFS
AFSApk
pk
0222
0222
0000
0
2
ωπ=
ωπ=ωπ=
ω ( ) ( ) ( )
( ) ( )
( )
( )
∆=∆
∆∆
=∆
=
=
−
∫
2signal
22
s21n22
22
022
FS2
2A
20
22FS
2
2T
00
22A
20
22FS
2
Ttq2A
jittererrortimetheistt2
fVA
becomeserroramplitudesquaremeantheThen
21tfVsquaremeanAE
dtttfVsquaremeanAE0
π
π
π
ωπ
)(
cos/
( )
( ) ( )
∆+=
∆+=
+2
signal
21n22
2s2
22
s2
Tt231
12qtotalq
A12qtotalq
π
Hence, the total (quantization+aperture) noise
( )
∆+= +
2signal
21n22
reduction Tt23110SNR πlog*
The SNR degradation can then be computed as:
Clock Jitter issues: SNR degradation
![Page 44: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/44.jpg)
Texas A&M University 44 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
( )
∆+= +
2signal
21n22
reduction Tt23110SNR πlog*
signal
jitter
signal TT
Tt
=∆
Clock Jitter issues: SNR degradation
![Page 45: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/45.jpg)
Texas A&M University 45 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
S/H, T/H: Formal Math
![Page 46: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/46.jpg)
Texas A&M University 46 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
![Page 47: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/47.jpg)
Texas A&M University 47 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
![Page 48: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/48.jpg)
Texas A&M University 48 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Vo
Ф
CS
RS
Vi
• MOS technology is naturally suitable for implementing T/H.• The lowpass SC network determines the tracking bandwidth of the T/H.• “Top-plate” sampling leads to signal-dependent switch on-resistance.
Ron
0 VDDVi
VTnVTp
PMOSNMOS
CMOS( )ithDDoxon VVV
LWCR −−=− µ1
![Page 49: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/49.jpg)
Texas A&M University 49 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Tracking Bandwidth (TBW)
Ron
CSVi Vo
RS Ron
0 VDDVi( ) SonS CRR +=1TBW
• Tracking bandwidth determines how promptly Vo can follow Vi.• Typically TBW is many times greater than the max signal bandwidth.• Notice that Ron is signal dependent, TBW is signal dependent too
• You should consider the worst case (Ron-maxima); remember Murphy’s Law!
![Page 50: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/50.jpg)
Texas A&M University 50 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Dispersion
( ) ( )
( ) ( )ωωω
ωωω
djHdt
jHt
g
p
∠−=
∠−=
:delay Group
:delay Phase
• Magnitude response• Non-uniform phase delay• Non-uniform group delay
|H(jω)|1
ω0
∠H(jω)
-45°
0
-90°
ω0
ωω0
![Page 51: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/51.jpg)
Texas A&M University 51 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Dispersion
• Waveform distortion mainly due to non-uniform phase- and group-delay.• Shape of waveform not very sensitive to the lowpass magnitude response
as long as the signal bandwidth is on the order of the TBW.
t t
Ron
CSVi Vo
RS
![Page 52: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/52.jpg)
Texas A&M University 52 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Signal-Dependent Ron
Vo
Ф
CS
RS
Vi
• Fixed levels gate signal leads to signal-dependent switch on-resistance→ signal-dependent TBW → extra waveform distortion.
• Signal-dependent Ron and dispersion are both insignificant if TBW issufficiently large (>> fin, depending on the T/H accuracy).
Ron
0 VDDVi
VTnVTp
PMOSNMOS
CMOS( )ithDDoxon VVV
LWCR −−=− µ1
![Page 53: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/53.jpg)
Texas A&M University 53 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
T/H: Practical issues
• Sufficient tracking bandwidth → negligible tracking error• Well-defined sampling instant (asserted by clock rising/falling edge)• Zero track- and hold-mode offset errors
V(t)
tTrack HoldHold
![Page 54: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/54.jpg)
Texas A&M University 54 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
• Finite tracking bandwidth → tracking error, T/H memory• Track-mode offset (can be signal-dependent)
V(t)
t
δ1δ2
Droop
Track HoldHoldΔt
T/H: Practical issues
![Page 55: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/55.jpg)
Texas A&M University 55 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Acquisition Time (tacq)
Ron
CSVi Vo
RS
( ) SonS CRR +==TBW
1τ
Short L, thin tox, large W, large Vov, small Vi all help reduce Ron.
Accuracy tacq
0.5% (7b) ≥ 5τ
0.1% (10b) ≥ 7τ
0.01% (13b) ≥ 9τ
( ) ( ) chithDDoxithDDox
on QL
VVVWLCL
VVVL
WCR
µµµ
221=
−−=
−−=
![Page 56: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/56.jpg)
Texas A&M University 56 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
T/H Errors (T-to-H Transition)
• Pedestal error (often signal-dependent) resulted from switch turn-offnonidealities (clock feedthrough and charge injection).
• Aperture delay – the delay Δt b/t the hold command and the hold action• Aperture jitter – the random variation in Δt (i.e., sampling clock jitter)
V(t)
t
δ1δ2
Droop
Track HoldHoldΔt
![Page 57: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/57.jpg)
Texas A&M University 57 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Sampling Switch CF and CI
Ф
VDD
0
Vin+Vth
Switch on Switch off
Vout
Ф
CS
Zi
Vin
CgdCgs
Qch
Clock feedthrough Charge injection
Fast turn-offSlow
turn-off
DDSgs
gs VCC
CV
+−=∆
( )( )Sgs
inthDDox
CCVVVWLCV
+−−
−=∆2
( )thinSgs
gs VVCC
CV +
+−=∆ 0=∆V
![Page 58: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/58.jpg)
Texas A&M University 58 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
T/H Pedestal Error
( )
( )
−
++
+−⋅
++=
+⋅+=
thDDSgs
oxDD
Sgs
gsi
Sgs
oxo
osio
VVCC
WLCVCC
CV
CCWLCV
VVV
21
211
1 ε
( )
thSgs
gsi
Sgs
gso
osio
VCC
CV
CCC
V
VVV
+−⋅
+−=
+⋅+=
1
1 ε
Slow turn-off:
Fast turn-off:
Vout
Ф
CS
Zi
Vin
CgdCgs
Qch
Check these results!
![Page 59: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/59.jpg)
Texas A&M University 59 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
T/H Speed-Accuracy Tradeoff
S
ch
CQV
21
≈∆Pedestal error:
TBW:S
ch
Son CLQ
CRTBW 2
1 µ=≈
µµ 221 22 L
QCL
CQ
TBWV
ch
S
S
ch =⋅≈∆
Therefore:
Technology scaling improves T/H performance!
![Page 60: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/60.jpg)
Texas A&M University 60 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Aperture Delay (Δt)
• Fixed aperture delay is usually not of problem in a single-channel T/H.• Non-uniform aperture delay among interleaved T/H channels are the
dominant sampling error source (Δt1, Δt2… are also called samplingclock skew)
CH 1
CH 2
Φ1
Φ2
Vin
Φ1
Φ2
![Page 61: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/61.jpg)
Texas A&M University 61 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Aperture Jitter
V(t)
t
δV
Track Hold
δt
dVdt
Ref: M. Shinagawa, Y. Akazawa, and T. Wakimoto, "Jitter analysis of high-speedsampling systems," IEEE Journal of Solid-State Circuits, vol. 25, pp. 220-224,issue 1, 1990.
![Page 62: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/62.jpg)
Texas A&M University 62 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Aperture Jitter
( ) ( ) ( ) ( )
( ) ( )[ ]22
1 2222
22
0
222 tT
i
AtAdttcosA
Ttt
tcosAttsinAtVt
σω=δ⋅
ω=ωω⋅δ=ε
→ω⋅ωδ≈ω−=ε
∫
onary"Cyclostati"
( ) ( )[ ]( ) ( ) ( ) ( )
( ) ( )
( ) ( ) .ttcosAttsinA
tcostsintcosAtsintsinA
tsintcosAtcostsinA
ttsinAtVi
δω⋅ωδ+ω≈
ωδ
ωδ⋅ω+
ωδ−⋅ω=
ωδ⋅ω+ωδ⋅ω=
δ+ω=
small for
222
21 2
22
2222 122 t
tAASNRσω
σω=
=
![Page 63: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/63.jpg)
Texas A&M University 63 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
106 107 108 1090
20
40
60
80
100
120
140
Input Freq [Hz]
SNR
[dB
]σ t = 0.1psσ t = 1psσ t = 10psσ t = 100ps
Aperture Jitter
( )tπfσLOGSNR 220 10⋅−=
![Page 64: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/64.jpg)
Texas A&M University 64 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
T/H Errors (Hold Mode)
• Hold-mode droop caused by off-switch/diode/gate leakage• Hold-mode input feedthrough (i.e., due to capacitive coupling)
V(t)
t
δ1δ2
Droop
Track HoldHoldΔt
![Page 65: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/65.jpg)
Texas A&M University 65 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Evaluating T/H Performance
kT/C noise:
SNDR:
++
=22
222
2
2 εδω VtAV
VSNDRN
i
SSN C
kTdfRCfj
kTRV =⋅+
⋅= ∫∞
0
22
2114π
Noise Distortion
CS √kT/C
1pF 64μV
100pF 6.4μV
10fF 640μV
T = 300K
Jitter
![Page 66: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/66.jpg)
Texas A&M University 66 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Top-Plate Sampling
Vo
Ф
CS
RS
Vi
Pros• Simple, minimum number of devices• Wideband, zero track-mode offsetCons• Signal-dependent tracking bandwidth• Signal-dependent charge injection and clock feedthrough• Signal-dependent aperture delay (sampling point)
![Page 67: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/67.jpg)
Texas A&M University 67 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
CMOS Switch
• Ron of the NMOS and PMOS devices complement each other.• Ron still depends on Vin and is sensitive to N/P matching.• Large parasitic capacitance due to PMOS switch.
Ron
0 VDDVi
VTnVTp
PMOSNMOS
CMOS
Vo
CS
Vi
Ф
Ф
![Page 68: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/68.jpg)
Texas A&M University 68 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Clock Bootstrapping
• Constant gate overdrive voltage VGS = VDD for the switch.• Ron to the first order does not depend on Vin.• NMOS device only, less parasitic capacitance.• Drawbacks:
• Charge pump is needed (Complexity)• (Stress over the SiOx) Gate voltage will be VDD+Vin-max
Ron
0 VDDVi
OutInM1
VDD
Φ Φ
![Page 69: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/69.jpg)
Texas A&M University 69 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Clock Bootstrapping
Ref: A. M. Abo and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline ADC," IEEEJournal of Solid-State Circuits, vol. 34, pp. 599-606, issue 5, 1999.
![Page 70: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/70.jpg)
Texas A&M University 70 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Dummy Switch
• Initial size of dummy chosen with the assumption of a 50/50 splitof Qch; usually (W/L)dummy < ½(W/L)switch in practice.
• The nonlinear dependence of CI on Zi, CS, and clock slew rate makes it difficult to achieve a precise cancellation.
• Ф_ rising edge must trail Ф falling edge.
Vo
Ф
WL CS
W2L
Ф
Vi
![Page 71: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/71.jpg)
Texas A&M University 71 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Balanced Switch + Dummy
Vo
Ф
WL CS
W2L
Ф
Vi
CS
Ref: L. A. Bienstman and H. J. De Man, "An eight-channel 8 bit microprocessorcompatible NMOS D/A converter with programmable scaling," IEEE Journalof Solid-State Circuits, vol. 15, pp. 1051-9, issue 6, 1980.
• TBW• Parasitics
![Page 72: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/72.jpg)
Texas A&M University 72 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Signal-Dependent Aperture Delay
• Non-uniform sampling due to signal-dependent aperture delay causesdistortion.
• Large slew-rate (SR) of clock edge and small Vin mitigate the effect.
Ф
VDD
0
Vi+Vth(Vi)
Switch on Switch off
Vth(Vi)
( )
( ) ( )
−=
=
SRtVtAtV
tAtV
io
i
ω
ω
sin
,sin
![Page 73: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/73.jpg)
Texas A&M University 73 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Signal-to-Distortion Ratio
( ) ( ) ( ) ( )
( ) ( ) ( ) ( )tASR
tASR
tAt
tASRVtVtVt i
oi
ωωωωωε
ωωε
2sin21cossin
cos
2⋅=⋅≈
⋅≈−=
( )
( ) ( )
( ) ( ) .cossin
sincoscossin
sin
SRVtA
SRVtA
SRVtA
SRVtA
SRVtAtV
ii
ii
io
small forωωω
ωωωω
ω
⋅−≈
⋅−
⋅=
−=
22
2
22
2 22
22 ω
ω
ASRSR
AASDR =
=
← 2nd-order
![Page 74: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/74.jpg)
Texas A&M University 74 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Fully-Differential T/H
• All even-order distortions are cancelled, including the signal-dependentaperture delay-induced distortion.
• Actual cancellation is limited by the P/N mismatch (1-5% typically).
fin 0.5GHzVDD 1.8V
tf 0.1nsA 0.5V
SDR (SE) 24.2dBSDR (DIFF) ?
Vo+
CS+
Vi+
Vo-
CS-
Vi-
Ф
M1
M2
![Page 75: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/75.jpg)
Texas A&M University 75 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Bottom-Plate Sampling
• Bottom-plate switch opens slightly earlier than the top-plate switches.• CF and CI of switch Φe are much less signal-dependent!• Bootstrapping the top-plate switch further helps.• For A/D converters of more than 8-bit resolution.• Less tracking bandwidth due to more switches in series.• Signal swing at node X is not completely zero!
Фe Ф
CS
Vi
Ф
Ф Фe
X
![Page 76: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/76.jpg)
Texas A&M University 76 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Flip-Over (Flip-Around) SHA
![Page 77: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/77.jpg)
Texas A&M University 77 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Flip-Over (Flip-Around) SHA
• Non-inverting, 1X closed-loop gain• Nonoverlapping two-phase clock with early sampling phase• CF and CI to the 1st order independent of Vin and cancelled differentially• Large open-loop gain of op-amp ensures the linearity of the SHA.
Vi+ Vo
+
Vo-Vi
-
CS+
Ф2Ф1eCS
-
Ф2Ф1e
Ф1
Ф1
Ф1eФ1
Ф2
T H
CMFB not shown
![Page 78: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/78.jpg)
Texas A&M University 78 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Inverting SHA
Closed-loop gain determined by the ratio CS/CH (mismatch?)
CMOS or bootstrappedswitches are requiredwhen passing signalswith large swing
Vi+ Vo
+
Vo-Vi
-
CS+
Ф2CS
-
Ф2
Ф1e
Ф1
Ф1
Ф2
CH+
CH-
Ф1
Ф1
Ref: R. C. Yen and P. R. Gray, “A MOS switched-capacitor instrumentation amplifier,”IEEE Journal of Solid-State Circuits, vol. 17, pp. 1008-1013, issue 6, 1982.
![Page 79: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/79.jpg)
Texas A&M University 79 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Inverting SHA (Track-Mode)
• CF and CI to the 1st order independent of Vin and cancelled differentially• Φ1e switch is equivalent to two switches of L/2 channel length.
Vi+
Vi-
CS+
CS-
Ф1e
Ф1
Ф1
CH+
CH-
Ф1
Ф1
WLФ1e Ф1e
WL/2
WL/2
![Page 80: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/80.jpg)
Texas A&M University 80 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Inverting SHA (Hold-Mode)
• For 1X gain, the feedback factor (β) is half that of the flip-over SHA.• Floating switch Φ2 in hold-mode → flexible input common mode• Useful for single-ended to differential conversion
Vo+
Vo-
CS+
Ф2CS
-
Ф2
Ф2
CH+
CH-
• CM• DM
![Page 81: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/81.jpg)
Texas A&M University 81 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Equivalent Circuits (Hold-Mode)
• Floating switch Φ2 in hold-mode → flexible input common mode• Useful for single-ended to differential conversion
Vo+
CS
Ф2
Adm
CH
Vi,dmФ2
Vo+
CS
Ф2
Acm
CH
Vi,cm
DM CM
![Page 82: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/82.jpg)
Texas A&M University 82 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
AZ Flip-Around SHA
• Bottom-plate sampling• Op-amp offset compensated by autozeroing• Stability in track-mode and fast settling in hold-mode
Vi+ Vo
+
Vo-Vi
-
CS+
Ф2CS
-
Ф2Ф1
Ф1
Ф1e
Ф1e
Vos
![Page 83: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/83.jpg)
Texas A&M University 83 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Closed-Loop SHA
• Closed loop system• Stability• Speed• Offset and noise due to Gm
• Effects of the clock feed-through? How the switch operates?
Voltage mode Current mode
Why C2 and M2?Advantages? Drawbacks?
![Page 84: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/84.jpg)
Texas A&M University 84 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Closed-Loop SHA
• A two-stage Miller-compensated op-amp → well-known design• CF and CI to the 1st order independent of Vin if A2 is large (VX≈0)• Vo always active and valid• Large slew-rate of A1 needed for fast tracking
Ref: K. R. Stafford et al., "A complete monolithic sample/hold amplifier," IEEE Journalof Solid-State Circuits, vol. 9, pp. 381-387, issue 6, 1974.
ViVo
CS
A2
Ф
A1X
Ф
![Page 85: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/85.jpg)
Texas A&M University 85 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Open-Loop SHA
• Typically 1X buffer gain to widen the TBW• Can utilize either top-plate (faster) or bottom-plate sampling• Suitable for very high-speed, low-resolution S/H applications.
Ф
WL CS
W2L
Ф
Vi Vo
1XVo
1X
CS
Vi
Ф1
Ф1Ф1e
Ф2
Top-plate sampling Bottom-plate sampling
![Page 86: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/86.jpg)
Texas A&M University 86 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Open-Loop SHA
![Page 87: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/87.jpg)
Texas A&M University 87 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Linearized amplifier
![Page 88: Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part IIIjose-silva-martinez/courses/ECEN610/Sample-Hold Part 3.pdfFundamentals on ADCs: Part 3 Jose Silva-Martinez For 10-Bit ADC, HD3](https://reader034.vdocuments.us/reader034/viewer/2022052519/5f0ed21b7e708231d44119bd/html5/thumbnails/88.jpg)
Texas A&M University 88 Spring, 2020
Fundamentals on ADCs: Part 3 Jose Silva-Martinez
Open-Loop SHA