fully buffered dimm

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Very Low Profile Fully Buffered DIMM Bill Gervasi Vice President, DRAM Technology SimpleTech The subject matter of this presentation is a work in progress. It had not been balloted or approved as a final JEDEC standard. Users should not rely on this presentation as indicative of the content of the final standard. JEDEC does not endorse the content of this presentation. The views expressed are solely those of the author(s).

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Page 1: Fully Buffered DIMM

Very Low ProfileFully Buffered DIMM

Bill GervasiVice President, DRAM Technology

SimpleTech

The subject matter of this presentation is a work in progress.  It had not been balloted or approved as a final JEDEC standard.  Users should not rely on this presentation as indicative of the content of the final standard. JEDEC does not

endorse the content of this presentation.  The views expressed are solely those of the author(s).

Page 2: Fully Buffered DIMM

The subject matter is a work in progress, not a final JEDEC standard.

Fully Buffered DIMM

• Designed for needs of mid-range servers– Typically 8 or 16 FB-DIMM slots– 4GB per slot by the time it is ramping

(1Gb DRAMs) 32GB & 64GB servers– Only “standard” height is 30mm (1.2”)

• Need to penetrate broader markets to ensure success and reduce cost

Page 3: Fully Buffered DIMM

The subject matter is a work in progress, not a final JEDEC standard.

Form Factor Wars

• 1.2” (30mm) standard chosen in 1999 based on 1U server market projections

• 1.2” (30mm) standard chosen in 1999 based on 1U server market projections

• But, market fragmenting– Blade needs 18.3mm (VLP)– 1U needs 30mm (LP)– 2U can use 38mm or taller

• OEMs “demand” one size fits all … but …

Page 4: Fully Buffered DIMM

The subject matter is a work in progress, not a final JEDEC standard.

High Profile Module2U Server

Side

View

• Lots of headroom due to huge heat sinks

• Tall module (e.g., 38mm) fits fine

• Better thermal characteristics

• More DRAM supplier options

30mm38mm

CPUHeatSink

Page 5: Fully Buffered DIMM

The subject matter is a work in progress, not a final JEDEC standard.

Standard Profile Module

Angled Socket

17700 mm2

Co

ol

Air

Hea

ted

Air

Top

View

CPU

CPU

30 mm DIMM

Blade Server

Page 6: Fully Buffered DIMM

The subject matter is a work in progress, not a final JEDEC standard.

Very Low Profile Module

Angled Socket

Vertical Socket

2 x 2200 mm2

75% Reduction!

Co

ol

Air

Hea

ted

Air

Blade Server

30 mm DIMM

18.3 mm DIMM

CPU

CPU

Top

View

Page 7: Fully Buffered DIMM

The subject matter is a work in progress, not a final JEDEC standard.

The VLP Form Factor133.35 mm

(5.25”)

4 mm(0.158”)

14.3 mm(0.56”)Usable

Layout Area

18.3 mm(0.72”)

Page 8: Fully Buffered DIMM

The subject matter is a work in progress, not a final JEDEC standard.

FB-DIMM Differentiation• How to build a better FB-DIMM

– Improved thermal solutions– How about a VLP FB-DIMM?

• Challenge #1: AMB is 19.2mm tall!

• Good thing guyslike us like to pack10 pounds into a 5pound sack…

19.2 mm(0.76”)

24 mm(0.95”)

Page 9: Fully Buffered DIMM

The subject matter is a work in progress, not a final JEDEC standard.

FB-DIMM Differentiation• Notice that the AMB has huge windows in the array• This choice was based on some assumptions:

– FB-DIMM must be possible in6 layers

– No blind vias required

• However, what if you’re willing to go to 8 layers and use blind vias?

Page 10: Fully Buffered DIMM

The subject matter is a work in progress, not a final JEDEC standard.

Honey, I Shrunk the AMB

655 ball AMB29x23 ball array (ball pitch 0.8mm)

24.5 x 19.5mm package

510 ball VLP-AMB31x17 ball array (ball pitch 0.8mm)

26 x 14mm package

Page 11: Fully Buffered DIMM

The subject matter is a work in progress, not a final JEDEC standard.

Can the AMB Be THAT Small?

The AMB die size is not the limiter… it’s the number of balls on the package that

defines its footprint.

Page 12: Fully Buffered DIMM

The subject matter is a work in progress, not a final JEDEC standard.

VLP FB-DIMMStacked 2GB

Page 13: Fully Buffered DIMM

The subject matter is a work in progress, not a final JEDEC standard.

DRAM Size

• Max DRAM package supported in VLP= 12.3 x 14.3 mm

• This supports most 512Mb chips now

• 1Gb shrinks with 70 nm process– 4GB VLP FB-DIMM enabled

Page 14: Fully Buffered DIMM

The subject matter is a work in progress, not a final JEDEC standard.

A Simpler Variation

• Primary-only interface – no southbound

• Uses 4-channel memory controller

• Eliminates 100 balls, 1W per AMB

“Lo

w E

nd

” F

B-D

IMM

C

on

tro

ller

“Hig

h E

nd

” F

B-D

IMM

C

on

tro

ller

Page 15: Fully Buffered DIMM

The subject matter is a work in progress, not a final JEDEC standard.

Current Status

• Getting customer input on primary-only AMB• Mechanical feasibility done• Re-ballout analysis under way with AMB

suppliers• Thermal analysis under way

– Improved airflow with lower ambient– Less radiating space– Heat sinking solutions to be developed

• Socket analysis begun

Page 16: Fully Buffered DIMM

The subject matter is a work in progress, not a final JEDEC standard.

Thank You

• Questions?

Bill [email protected]