LAB ASSIGNMENT 3:EE 705- VLSI DESIGN LAB

Describing a Finite State Machine(FSM)

INDRANIL CHAKRABORTY ROLL-143070072

ELECTRICAL ENGINEERING MICROELECTRONICS

DATE 06th February , 2015

IIT BOMBAY

Describing an FSM Characteristics:

Input symbol set: {p,q} Output symbol set: {M, N} The machine outputs M if the input sequence seen thus far (including the

current input) is of the form ppp..pqqq..q, where the number of input ps and number of qs are both even numbers.

Description: The FSM should detect the sequence ppp..pqqq..q, where the number of input ps and number of qs are both even numbers. The minimum detectable sequence is ppqq. So, we need the following states: (starting state), p,pp,ppq,ppqq. We also need a state where the FSM will end up in case of invalid sequences. We call that state dead. Whenever there is a break in the build up to the required sequence, we send the FSM to the dead state. The dead state can only be recovered using a reset signal. The states and transitions: a) State This is the starting state. On receiving input p, it moves to state p but on

receiving input q, it moves to state dead as its an invalid input stream. b) State p- On receiving input p, it moves to state pp but on receiving input q, it

moves to state dead, as pq is an invalid stream. c) State pp- On receiving input pp, it moves to state p but on receiving input q, it

moves to state ppq. d) State ppq - On receiving input ppq, it moves to state p but on receiving input

dead, as it becomes an invalid stream, but on receiving q, it moves to state ppqq, e) State ppqq - On receiving input p, it moves to state dead but on receiving input

q, it moves to state ppq. f) State dead This is the state where the system ends up when an invalid input stream

occurs. On receiving input p or q, it remains in the dead state. Only a reset input can move the system away from this state to state .

The outputs:

a) M When a valid input stream occurs ppppqqqq., output M occurs. Only a transition from ppq to ppqq, will produce this output M. This will signify a successful detection.

b) N In case of any other input stream, unsuccessful detection is signified by output N.

State Diagram:

State Transition Table:

Current State Next State Output X = p X= q X= Reset X = p X= q X= Reset p dead N N N p pp dead N N N

pp p ppq N N N ppq dead ppqq N M N

Ppqq dead ppq N N N dead dead dead N N N

VHDL organization of DUT: i) Package Definition: We define a package in order to introduce new data types - i)

fsm_state ii)input_symbol, iii) output_symbol and the fsm component. ------------------------------------------------------------ package FsmPackage is --Package definition type fsm_state is (s_phi, s_p, s_pp, s_ppq, s_ppqq,s_dead); --States defined type input_symbol is (reset, p,q); --Inputs defined type output_symbol is (M,N); --Outputs defined component exp_fsm is --Component defined specifying input and output ports and clock port (X: in input_symbol; Y: out output_symbol; clk: in bit); end component; end FsmPackage; -------------------------------------------------------------

p pp ppq

ppqq

q/N

q/N

q/N

p/N

p/N

p/N

q/M q/N

p/N

reset/N p/N

dead reset/N

p,q/N

ii) Architecture and Process: We define a signal state, of type fsm_state which would denote the current state. Signals denoting next state(nstate), present state(pstate) and variable denoting the output(vY) is defined. ------------------------------------------------------------- architecture fsm_behave of exp_fsm is signal pstate: fsm_state; --Signal to store Present State signal nstate: fsm_state; --Signal to store Next State begin FSM: process(X,pstate) variable vY: output_symbol; --Variable to store output-------------------------------------------------------------- The start of the FSM process is stated by assigning current state to next state and N to Y. ------------------------------------------------------------- nstate if(X = p) then nstate

------------------------------------------------------------- STATE_TRAN: process begin wait until clk'event and clk = '1'; report ht & input_symbol'image(X) & ht & ht & fsm_state'image(pstate) & ht & ht & fsm_state'image(nstate) & ht & ht & output_symbol'image(Y); --reporting format pstate

6 p p 1 N 7 p p pp 2 N 8 q pp ppq 4 N 9 p ppq dead 5 N 10 reset dead 8 N 11 p p 1 N 12 p p pp 2 N 13 q pp ppq 4 N 14 q ppq ppqq 10 M 15 q ppqq ppq 11 N 16 q ppq ppqq 10 M 17 p ppqq dead 9 N 18 p dead dead 12 N 19 q dead dead 13 N 20 reset dead 8 N 21 q dead 7 N 22 reset dead 8 N 23 p p 1 N 24 reset p Reset p N 25 p p 1 N 26 p p pp 2 N 27 reset pp Reset pp N 28 p p 1 N 29 p p pp 2 N 30 q pp ppq 4 N 31 reset ppq Reset ppq N 32 p p 1 N 33 p p pp 2 N 34 q pp ppq 4 N 35 q ppq ppqq 10 M 36 reset ppqq Reset ppqq N

So, that stream reset, pppq,reset,ppqq,reset,ppqqqqppq,reset,p,reset,pp,reset,ppq,reset,ppqq,reset covers all possible transitions and states.

The expected output stream is NNNNNNNNNNNNNNMNMNNNNNNNNNNNNNNNNNNMN

To be noted that, this is not an exhaustive test and might not be able to show all the problems in the FSM. For an exhaustive test, it is advised to test each combination of input string of length N(N=number of states). However for more than 2 input symbols, this may become a lengthy procedure.

The testbench includes the library we have defined and the architecture behave is defined over the entity Testbench. We use an array of Input_symbol and an array of Output_Symbol to incorporate the input string and match the output.

----------------------------------------------------------------- type InputVector is array (natural range ) of input_symbol; type OutputVector is array (natural range ) of output_symbol;

constant input_trace: InputVector(0 to 36) := (0 => reset, 1 => p, 2 => p, 3 => p, 4 => q, 5 => reset, 6 => p, 7 => p, 8 => q, 9=> p, 10=> reset, 11=> p, 12=> p, 13=> q, 14=> q, 15=> q, 16=> q, 17=> p, 18=>p, 19=> q, 20=> reset, 21=>q , 22=> reset,23=> p, 24=> reset, 25=> p, 26=> p, 27=> reset, 28=> p, 29=> p, 30=>q,31=> reset, 32=> p, 33=> p, 34=> q, 35=>q,36=> reset ); --Input sequence constant output_trace: OutputVector(0 to 36) := (0 => N, 1 => N, 2 => N, 3 => N, 4 => N, 5 => N, 6 => N, 7 => N, 8 => N, 9=> N, 10=> N, 11=> N, 12=> N, 13=> N, 14=> M, 15=> N, 16=> M, 17=> N, 18=> N, 19=> N, 20=> N, 21=> N, 22=> N,23=> N, 24=> N, 25=> N, 26=> N, 27=> N, 28=> N, 29=> N, 30=>N,31=> N, 32=> N, 33=> N, 34=> N, 35=>M,36=> N ); --Corresponding expected output Sequence ----------------------------------------------------------------

We define the clock of period 10 ns, with 50% duty cycle using the following process:

--------------------------------------------------------------- SIM: process --Process to generate clock begin if end_of_sim = false then --Apply Clock clk

wait until clk = '1'; --Wait for rising edge of clock end loop; wait for 5 ns; assert false report "test successful" severity note; end_of_sim := true; wait; end process ESIM; ---------------------------------------------------------------

Points to Note: We have applied the input synchronously with the clock. However, a special characteristic of Mealy machine is that the output changes asynchronously whenever input changes. We have not shown that characteristic in this experiment.

Reporting of output: We report all the transitions that takes place during the processing of the input stream using the following piece of code: ------------------------------------------------------------------------------- report ht & input_symbol'image(X) & ht & ht & fsm_state'image(pstate) & ht & ht & fsm_state'image(nstate) & ht & ht & output_symbol'image(Y); ------------------------------------------------------------------------------- Here, pstate stores the present state, nstate stores the next state, X and Y are the input and output symbols.

Sample output:

WAVE:

ZOOMED TO SHOW DIFFERENT STATES: ZOOM1(0-90ns):

ZOOM2(90ns-180ns)

ZOOM3(180ns-270ns)

ZOOM4(270ns-360ns)