CP-PLL models Design Example

Dottorato di Ricerca in Ingegneria Elettronica Informatica e delleTelecomunicazioni

Frequency Synthesizers for RF TransceiversModelling of PLL in the frequency and time domain with a

design example

E. Franchi, A. Gnudi, M. Guermandi

ARCES - University of Bologna

July, 20th 2010 - Short Course onRF electronics for wireless communication and remote sensing

systems

CP-PLL models Design Example

Outline

1 CP-PLL modelsThe need for accurate PLL modelss-domain modelz-domain modelTime-domain modelComparison between modelsPhase Noise Models

2 Design Example: Frequency Synthesizer for UWB MB-OFDMUWB communicationsSynthesizer ArchitecturePLLsTuning Range ExtensionMeasured results

CP-PLL models Design Example

Outline

1 CP-PLL modelsThe need for accurate PLL modelss-domain modelz-domain modelTime-domain modelComparison between modelsPhase Noise Models

2 Design Example: FrequencySynthesizer for UWB MB-OFDM

UWB communicationsSynthesizer ArchitecturePLLsTuning Range ExtensionMeasured results

CP-PLL models Design Example

Charge Pump Phase Locked Loops (CP-PLLs)

LOOP VCO

DIVIDERFREQ

REF UPF

DN

REF

DIVF

FOUT

DETECTOR FILTERFREQPHASE

PUMPCHARGE

Charge Pump Phase Locked Loop

PFD-CP compares phase misalignment between feedback and reference signal.Loop Filter integrates error signal and controls VCO output frequency.When in-lock FOUT = N · FREF .Loop tracks phase and frequency misalignments with zero errors.

CP-PLL models Design Example

Charge Pump Phase Locked Loops (CP-PLLs)

LOOP VCO

DIVIDERFREQ

REF UPF

DN

REF

DIVF

FOUT

DETECTOR FILTERFREQPHASE

PUMPCHARGE

Charge Pump Phase Locked Loop

CP, LF and VCO are continuous-time systems.PFD and FD are edge-driven systems.Phase comparison is performed once per reference period, not continuously.

CP-PLL models Design Example

The need for accurate PLL models

PLL modelsSimulations need to be performed hierarchically. Circuit leveltime-domain simulation is not feasible.

Traditional models (s-domain and z-domain) rely onlinearizations and approximations to simplify loop analysis.Efficient semi-analytical time-domain models can avoid theseapproximations, with reduced computation time.Derivation and comparison between these models is performed.

CP-PLL models Design Example

The need for accurate PLL models

PLL modelsSimulations need to be performed hierarchically. Circuit leveltime-domain simulation is not feasible.Traditional models (s-domain and z-domain) rely onlinearizations and approximations to simplify loop analysis.

Efficient semi-analytical time-domain models can avoid theseapproximations, with reduced computation time.Derivation and comparison between these models is performed.

CP-PLL models Design Example

The need for accurate PLL models

PLL modelsSimulations need to be performed hierarchically. Circuit leveltime-domain simulation is not feasible.Traditional models (s-domain and z-domain) rely onlinearizations and approximations to simplify loop analysis.Efficient semi-analytical time-domain models can avoid theseapproximations, with reduced computation time.

Derivation and comparison between these models is performed.

CP-PLL models Design Example

The need for accurate PLL models

PLL modelsSimulations need to be performed hierarchically. Circuit leveltime-domain simulation is not feasible.Traditional models (s-domain and z-domain) rely onlinearizations and approximations to simplify loop analysis.Efficient semi-analytical time-domain models can avoid theseapproximations, with reduced computation time.Derivation and comparison between these models is performed.

CP-PLL models Design Example

Outline

1 CP-PLL modelsThe need for accurate PLL modelss-domain modelz-domain modelTime-domain modelComparison between modelsPhase Noise Models

2 Design Example: FrequencySynthesizer for UWB MB-OFDM

UWB communicationsSynthesizer ArchitecturePLLsTuning Range ExtensionMeasured results

CP-PLL models Design Example

Fourth order PLL s-domain model

ApproximationCharge injected by chargepump over one period:Q = θr−θd

2π GT

If the loop dynamic is slowenough one can neglectthe CP current actualshapeand substitute it with anaverage current:iCP = G θr−θd

2π

Averaged linear continuoustime PLL model

θ

θ

θVCOK

VCOLPF

C

1N

FD

s2πr

d

V

G (s)o

G LF

CP

PFD

2

1

π

REF

DIV

Icp

t

t

t

QC

∆θ−2π π

π π π−3π

32

−

CP-PLL models Design Example

Fourth order PLL s-domain model

ApproximationCharge injected by chargepump over one period:Q = θr−θd

2π GTIf the loop dynamic is slowenough one can neglectthe CP current actualshape

and substitute it with anaverage current:iCP = G θr−θd

2π

Averaged linear continuoustime PLL model

θ

θ

θVCOK

VCOLPF

C

1N

FD

s2πr

d

V

G (s)o

G LF

CP

PFD

2

1

π

REF

DIV

Icp

t

t

t

QC

∆θ−2π π

π π π−3π

32

−

CP-PLL models Design Example

Fourth order PLL s-domain model

ApproximationCharge injected by chargepump over one period:Q = θr−θd

2π GTIf the loop dynamic is slowenough one can neglectthe CP current actualshapeand substitute it with anaverage current:iCP = G θr−θd

2π

Averaged linear continuoustime PLL model

θ

θ

θVCOK

VCOLPF

C

1N

FD

s2πr

d

V

G (s)o

G LF

CP

PFD

2

1

π

REF

DIV

Icp

t

t

t

QC

∆θ−2π π

π π π−3π

32

−

CP-PLL models Design Example

Fourth order PLL s-domain model

ApproximationCharge injected by chargepump over one period:Q = θr−θd

2π GTIf the loop dynamic is slowenough one can neglectthe CP current actualshapeand substitute it with anaverage current:iCP = G θr−θd

2π

Averaged linear continuoustime PLL model

θ

θ

θVCOK

VCOLPF

C

1N

FD

s2πr

d

V

G (s)o

G LF

CP

PFD

2

1

π

REF

DIV

Icp

t

t

t

QC

∆θ−2π π

π π π−3π

32

−

CP-PLL models Design Example

s-domain model transfer functionsCP-PFD

iCP = G θr−θd2π → ICP(s)

θr (s)−θd (s)= G

2π

3rd order LF

GLF (s) =VC(s)ICP(s)

=

KLFs+1/τz

s·(s+b/τz)·(s+c/τz)

QVCO

fo = KVCO · VC , θo =∫

2πfo(t)dt→ θo(s)

VC(s)= 2π·KVCO

s

FD

θd (s)θo(s) =

1N

θ

θ

θVCOK

VCOLPF

C

1N

FD

s2πr

d

V

G (s)o

G LF

CP

PFD

2

1

π

REF

DIV

Icp

t

t

t

QC

∆θ−2π π

π π π−3π

32

−

CP-PLL models Design Example

s-domain model transfer functionsCP-PFD

iCP = G θr−θd2π → ICP(s)

θr (s)−θd (s)= G

2π

3rd order LF

GLF (s) =VC(s)ICP(s)

=

KLFs+1/τz

s·(s+b/τz)·(s+c/τz)

QVCO

fo = KVCO · VC , θo =∫

2πfo(t)dt→ θo(s)

VC(s)= 2π·KVCO

s

FD

θd (s)θo(s) =

1N

θ

θ

θVCOK

VCOLPF

C

1N

FD

s2πr

d

V

G (s)o

G LF

CP

PFD

2

1

π

REF

DIV

Icp

t

t

t

QC

∆θ−2π π

π π π−3π

32

−

CP-PLL models Design Example

s-domain model transfer functionsCP-PFD

iCP = G θr−θd2π → ICP(s)

θr (s)−θd (s)= G

2π

3rd order LF

GLF (s) =VC(s)ICP(s)

=

KLFs+1/τz

s·(s+b/τz)·(s+c/τz)

QVCO

fo = KVCO · VC , θo =∫

2πfo(t)dt→ θo(s)

VC(s)= 2π·KVCO

s

FD

θd (s)θo(s) =

1N

θ

θ

θVCOK

VCOLPF

C

1N

FD

s2πr

d

V

G (s)o

G LF

CP

PFD

2

1

π

REF

DIV

Icp

t

t

t

QC

∆θ−2π π

π π π−3π

32

−

CP-PLL models Design Example

s-domain model transfer functionsCP-PFD

iCP = G θr−θd2π → ICP(s)

θr (s)−θd (s)= G

2π

3rd order LF

GLF (s) =VC(s)ICP(s)

=

KLFs+1/τz

s·(s+b/τz)·(s+c/τz)

QVCO

fo = KVCO · VC , θo =∫

2πfo(t)dt→ θo(s)

VC(s)= 2π·KVCO

s

FD

θd (s)θo(s) =

1N

θ

θ

θVCOK

VCOLPF

C

1N

FD

s2πr

d

V

G (s)o

G LF

CP

PFD

2

1

π

REF

DIV

Icp

t

t

t

QC

∆θ−2π π

π π π−3π

32

−

CP-PLL models Design Example

Fourth order PLL s-domain model

θ

θ

θVCOK

VCOLPF

C

1N

FD

s2πr

d

V

G (s)o

G LF

CP

PFD

2

1

π

Open loop transfer function...

Gc(s) =G · KVCO · GLF (s)

s · N

Closed loop transfer function

θo

θr=

G · KVCON · GLF (s)s · N + G · KVCO · GLF (s)

... for third order LF...

Gc(s) = KCs + 1/τz

s2 · (s + b/τz) · (s + c/τz)

Rule of thumb for design

fc =1

tlockζe(φm)ln(

fstep

ferror

)

N

log f

cfzbfz

Gc

1+Gc

Gc

log f

fz fc

π

arg( )

20log(| |)

mφ

CP-PLL models Design Example

Fourth order PLL s-domain model

θ

θ

θVCOK

VCOLPF

C

1N

FD

s2πr

d

V

G (s)o

G LF

CP

PFD

2

1

π

Open loop transfer function...

Gc(s) =G · KVCO · GLF (s)

s · N

Closed loop transfer function

θo

θr=

G · KVCON · GLF (s)s · N + G · KVCO · GLF (s)

... for third order LF...

Gc(s) = KCs + 1/τz

s2 · (s + b/τz) · (s + c/τz)

Rule of thumb for design

fc =1

tlockζe(φm)ln(

fstep

ferror

)

N

log f

cfzbfz

Gc

1+Gc

Gc

log f

fz fc

π

arg( )

20log(| |)

mφ

CP-PLL models Design Example

Fourth order PLL s-domain model

θ

θ

θVCOK

VCOLPF

C

1N

FD

s2πr

d

V

G (s)o

G LF

CP

PFD

2

1

π

Open loop transfer function...

Gc(s) =G · KVCO · GLF (s)

s · N

Closed loop transfer function

θo

θr=

G · KVCON · GLF (s)s · N + G · KVCO · GLF (s)

... for third order LF...

Gc(s) = KCs + 1/τz

s2 · (s + b/τz) · (s + c/τz)

... with

KC =GKVCOKLF

N.

N

log f

cfzbfz

Gc

1+Gc

Gc

log f

fz fc

π

arg( )

20log(| |)

mφ

CP-PLL models Design Example

Fourth order PLL s-domain model

θ

θ

θVCOK

VCOLPF

C

1N

FD

s2πr

d

V

G (s)o

G LF

CP

PFD

2

1

π

Open loop transfer function...

Gc(s) =G · KVCO · GLF (s)

s · N

Closed loop transfer function

θo

θr=

G · KVCON · GLF (s)s · N + G · KVCO · GLF (s)

... for third order LF...

Gc(s) = KCs + 1/τz

s2 · (s + b/τz) · (s + c/τz)

... with

KC =GKVCOKLF

N.

N

log f

cfzbfz

Gc

1+Gc

Gc

log f

fz fc

π

arg( )

20log(| |)

mφ

CP-PLL models Design Example

Fourth order PLL s-domain model

θ

θ

θVCOK

VCOLPF

C

1N

FD

s2πr

d

V

G (s)o

G LF

CP

PFD

2

1

π

Open loop transfer function...

Gc(s) =G · KVCO · GLF (s)

s · N

Closed loop transfer function

θo

θr=

G · KVCON · GLF (s)s · N + G · KVCO · GLF (s)

... for third order LF...

Gc(s) = KCs + 1/τz

s2 · (s + b/τz) · (s + c/τz)

... with

KC =GKVCOKLF

N.

N

log f

cfzbfz

Gc

1+Gc

Gc

log f

fz fc

π

arg( )

20log(| |)

mφ

CP-PLL models Design Example

Fourth order PLL s-domain model

θ

θ

θVCOK

VCOLPF

C

1N

FD

s2πr

d

V

G (s)o

G LF

CP

PFD

2

1

π

Open loop transfer function...

Gc(s) =G · KVCO · GLF (s)

s · N

Closed loop transfer function

θo

θr=

G · KVCON · GLF (s)s · N + G · KVCO · GLF (s)

... for third order LF...

Gc(s) = KCs + 1/τz

s2 · (s + b/τz) · (s + c/τz)

Rule of thumb for design

fc =1

tlockζe(φm)ln(

fstep

ferror

)

N

log f

cfzbfz

Gc

1+Gc

Gc

log f

fz fc

π

arg( )

20log(| |)

mφ

CP-PLL models Design Example

Outline

1 CP-PLL modelsThe need for accurate PLL modelss-domain modelz-domain modelTime-domain modelComparison between modelsPhase Noise Models

2 Design Example: FrequencySynthesizer for UWB MB-OFDM

UWB communicationsSynthesizer ArchitecturePLLsTuning Range ExtensionMeasured results

CP-PLL models Design Example

Fourth order PLL z-domain model

PFD granularity effects when the loop bandwidth is too large.

Compute z-domain model by1 Substitute to the real CP input, weighted impulses of same

area as the real pulse.2 Compute open loop impulse response gc(t)

antitransforming GC(s).3 Sample the obtained equation every T .4 Z-transform to obtain GD(z).5 Compute closed-loop transfer function from GD(z).

CP-PLL models Design Example

Z-domain model

Antitransform open loop transfer function

GC(s) = KC

[As + B

s2+

Cs + b

τz

+D

s + cτz

]

Impulse response

gc(t) = KC [Au(t) + Bt + Ce− btτz + De

− ctτz ]

Sampled impulse response

gd (n) = KC [Au(nT )+BnT +Ce− bnTτz +De

− cnTτz ]

z-Transform

GD(z) =

KCTAzz − 1

+KCBT 2z(z − 1)2

+KCTCz

z − e− bTτz

+KCTDz

z − e− cTτz

CP-PLL models Design Example

Z-domain model

Antitransform open loop transfer function

GC(s) = KC

[As + B

s2+

Cs + b

τz

+D

s + cτz

]

Impulse response

gc(t) = KC [Au(t) + Bt + Ce− btτz + De

− ctτz ]

Sampled impulse response

gd (n) = KC [Au(nT )+BnT +Ce− bnTτz +De

− cnTτz ]

z-Transform

GD(z) =

KCTAzz − 1

+KCBT 2z(z − 1)2

+KCTCz

z − e− bTτz

+KCTDz

z − e− cTτz

CP-PLL models Design Example

Z-domain model

Antitransform open loop transfer function

GC(s) = KC

[As + B

s2+

Cs + b

τz

+D

s + cτz

]

Impulse response

gc(t) = KC [Au(t) + Bt + Ce− btτz + De

− ctτz ]

Sampled impulse response

gd (n) = KC [Au(nT )+BnT +Ce− bnTτz +De

− cnTτz ]

z-Transform

GD(z) =

KCTAzz − 1

+KCBT 2z(z − 1)2

+KCTCz

z − e− bTτz

+KCTDz

z − e− cTτz

CP-PLL models Design Example

Z-domain model

Antitransform open loop transfer function

GC(s) = KC

[As + B

s2+

Cs + b

τz

+D

s + cτz

]

Impulse response

gc(t) = KC [Au(t) + Bt + Ce− btτz + De

− ctτz ]

Sampled impulse response

gd (n) = KC [Au(nT )+BnT +Ce− bnTτz +De

− cnTτz ]

z-Transform

GD(z) =

KCTAzz − 1

+KCBT 2z(z − 1)2

+KCTCz

z − e− bTτz

+KCTDz

z − e− cTτz

CP-PLL models Design Example

Z-domain model - Step fiveClosed loop transfer function

TD(z) =θo(z)θi (z)

=N · GD(z)1 + GD(z)

Antitransforming

θo(n) =4∑

i=1

hu(i) · θo(n − i) +3∑

i=1

hv (i) · θi (n − i)

With

hu(1) = β + γ + 2 + A′(β + γ + 1)− B′T+

+C′(γ + 2) + D′(β + 2)

hu(2) = −1− 2β − 2γ − βγ+−A′(γβ + γ + β) + B′T (β + γ)+

−C′ · (2γ + 1)− D′(2β + 1)

hu(3) = 2βγ + β + γ + A′βγ+−B′Tγβ + C′γ + D′β

hu(4) = βγ

hv (1) = −A′(β + γ + 1) + B′T+

−C′(γ + 2)− D′(β + 2)

hv (2) = A′(γβ + γ + β)− B′T (β + γ)+

+C′ · (2γ + 1) + D′(2β + 1)

hv (3) = −A′γ + B′Tγβ − C′γ − D′β

CP-PLL models Design Example

Z-domain model - Step fiveClosed loop transfer function

TD(z) =θo(z)θi (z)

=N · GD(z)1 + GD(z)

Antitransforming

θo(n) =4∑

i=1

hu(i) · θo(n − i) +3∑

i=1

hv (i) · θi (n − i)

With

hu(1) = β + γ + 2 + A′(β + γ + 1)− B′T+

+C′(γ + 2) + D′(β + 2)

hu(2) = −1− 2β − 2γ − βγ+−A′(γβ + γ + β) + B′T (β + γ)+

−C′ · (2γ + 1)− D′(2β + 1)

hu(3) = 2βγ + β + γ + A′βγ+−B′Tγβ + C′γ + D′β

hu(4) = βγ

hv (1) = −A′(β + γ + 1) + B′T+

−C′(γ + 2)− D′(β + 2)

hv (2) = A′(γβ + γ + β)− B′T (β + γ)+

+C′ · (2γ + 1) + D′(2β + 1)

hv (3) = −A′γ + B′Tγβ − C′γ − D′β

CP-PLL models Design Example

Z-domain model - Step fiveClosed loop transfer function

TD(z) =θo(z)θi (z)

=N · GD(z)1 + GD(z)

Antitransforming

θo(n) =4∑

i=1

hu(i) · θo(n − i) +3∑

i=1

hv (i) · θi (n − i)

With

hu(1) = β + γ + 2 + A′(β + γ + 1)− B′T+

+C′(γ + 2) + D′(β + 2)

hu(2) = −1− 2β − 2γ − βγ+−A′(γβ + γ + β) + B′T (β + γ)+

−C′ · (2γ + 1)− D′(2β + 1)

hu(3) = 2βγ + β + γ + A′βγ+−B′Tγβ + C′γ + D′β

hu(4) = βγ

hv (1) = −A′(β + γ + 1) + B′T+

−C′(γ + 2)− D′(β + 2)

hv (2) = A′(γβ + γ + β)− B′T (β + γ)+

+C′ · (2γ + 1) + D′(2β + 1)

hv (3) = −A′γ + B′Tγβ − C′γ − D′β

CP-PLL models Design Example

Outline

1 CP-PLL modelsThe need for accurate PLL modelss-domain modelz-domain modelTime-domain modelComparison between modelsPhase Noise Models

2 Design Example: FrequencySynthesizer for UWB MB-OFDM

UWB communicationsSynthesizer ArchitecturePLLsTuning Range ExtensionMeasured results

CP-PLL models Design Example

Limits of s- and z-domain models

s-domain modelRelies on the fact that PFD input signal misalignment issampled so fast that it can be considered acontinuous-time operation.Might fail for wideband PLLs.

z-domain modelAssumes PFD input signal misalignment is small (pulses ≈impulses).Might fail for large frequency jumps.

CP-PLL models Design Example

Limits of s- and z-domain models

s-domain modelRelies on the fact that PFD input signal misalignment issampled so fast that it can be considered acontinuous-time operation.Might fail for wideband PLLs.

z-domain modelAssumes PFD input signal misalignment is small (pulses ≈impulses).Might fail for large frequency jumps.

CP-PLL models Design Example

CP-PLL time-domain modelClassical time-domain simulation limits

We need to simulate at least for the settling time (severalTref ) while resolving time-steps of fractions of the VCOperiod.Too many simulation steps to resolve output frequency withdesired precision.Tens-of-hours required.

Better solutionSolve state equation describing loop behavior analytically.Compute system state variables only on few points perperiod.

ref

div

Vc

tpinft

t supq

CP-PLL models Design Example

CP-PLL time-domain modelClassical time-domain simulation limits

We need to simulate at least for the settling time (severalTref ) while resolving time-steps of fractions of the VCOperiod.Too many simulation steps to resolve output frequency withdesired precision.Tens-of-hours required.

Better solutionSolve state equation describing loop behavior analytically.Compute system state variables only on few points perperiod.

ref

div

Vc

tpinft

t supq

CP-PLL models Design Example

CP-PLL time-domain model

Classical time-domain simulation limitsWe need to simulate at least for the settling time (severalTref ) while resolving time-steps of fractions of the VCOperiod.Too many simulation steps to resolve output frequency withdesired precision.Tens-of-hours required.

Better solutionSolve state equation describing loop behavior analytically.Compute system state variables only on few points perperiod.

ref

div

Vc

tpinft

t supq

CP-PLL models Design Example

CP-PLL time-domain model

Next DIV transition found inverting∫ tsup

tinf

fout (t)dt = N

Substituting∫ tsup

tinf

(KVCO · vc(t) + f0

)dt = N

Integrating time-independent terms∫ tsup

tinf

vc(t)dt =N − f0(tsup − tinf )

KVCO.

τq = T − (i−1)

p = − (i−1)

t = 0inf

τ

ref

div

τ τq = T − (i−1) + (i)

t = 0inf

τp = − (i−1)

ref

div

τ

q = T + (i)

p = (i−1)

ττ

supt = T + (i)

ref

div

τ τ

(i)τt = T +

q(i) = T

τ

(i−1) (i)

sup

p(i) =

> 0, > 0ref

div

t = inf τ

τ τ < 0, < 0(i−1) (i)

sup τ τ τ τ

τ τ < 0, > 0

sup

(i−1) (i)

t = T − (i−1) + (i)

(i−1)

(i−1)

t =

(i)

t = T − (i−1) + (i)

inf τ(i−1)

> 0, < 0τ τ

t

inftp

t sup

q t

Vc

tsuptqinft

p

Vc

p

Vc

qt supt inf

p t

Vc

tinf

t supq

Time-domain solver

We analitically integrate the term on the left (depending on the 4 cases) and, every Trefwe numerically invert the obtained equation.

CP-PLL models Design Example

CP-PLL time-domain model

Next DIV transition found inverting∫ tsup

tinf

fout (t)dt = N

Substituting∫ tsup

tinf

(KVCO · vc(t) + f0

)dt = N

Integrating time-independent terms∫ tsup

tinf

vc(t)dt =N − f0(tsup − tinf )

KVCO.

τq = T − (i−1)

p = − (i−1)

t = 0inf

τ

ref

div

τ τq = T − (i−1) + (i)

t = 0inf

τp = − (i−1)

ref

div

τ

q = T + (i)

p = (i−1)

ττ

supt = T + (i)

ref

div

τ τ

(i)τt = T +

q(i) = T

τ

(i−1) (i)

sup

p(i) =

> 0, > 0ref

div

t = inf τ

τ τ < 0, < 0(i−1) (i)

sup τ τ τ τ

τ τ < 0, > 0

sup

(i−1) (i)

t = T − (i−1) + (i)

(i−1)

(i−1)

t =

(i)

t = T − (i−1) + (i)

inf τ(i−1)

> 0, < 0τ τ

t

inftp

t sup

q t

Vc

tsuptqinft

p

Vc

p

Vc

qt supt inf

p t

Vc

tinf

t supq

Time-domain solver

We analitically integrate the term on the left (depending on the 4 cases) and, every Trefwe numerically invert the obtained equation.

CP-PLL models Design Example

CP-PLL time-domain model

Next DIV transition found inverting∫ tsup

tinf

fout (t)dt = N

Substituting∫ tsup

tinf

(KVCO · vc(t) + f0

)dt = N

Integrating time-independent terms∫ tsup

tinf

vc(t)dt =N − f0(tsup − tinf )

KVCO.

τq = T − (i−1)

p = − (i−1)

t = 0inf

τ

ref

div

τ τq = T − (i−1) + (i)

t = 0inf

τp = − (i−1)

ref

div

τ

q = T + (i)

p = (i−1)

ττ

supt = T + (i)

ref

div

τ τ

(i)τt = T +

q(i) = T

τ

(i−1) (i)

sup

p(i) =

> 0, > 0ref

div

t = inf τ

τ τ < 0, < 0(i−1) (i)

sup τ τ τ τ

τ τ < 0, > 0

sup

(i−1) (i)

t = T − (i−1) + (i)

(i−1)

(i−1)

t =

(i)

t = T − (i−1) + (i)

inf τ(i−1)

> 0, < 0τ τ

t

inftp

t sup

q t

Vc

tsuptqinft

p

Vc

p

Vc

qt supt inf

p t

Vc

tinf

t supq

Time-domain solver

We analitically integrate the term on the left (depending on the 4 cases) and, every Trefwe numerically invert the obtained equation.

CP-PLL models Design Example

CP-PLL time-domain model

Next DIV transition found inverting∫ tsup

tinf

fout (t)dt = N

Substituting∫ tsup

tinf

(KVCO · vc(t) + f0

)dt = N

Integrating time-independent terms∫ tsup

tinf

vc(t)dt =N − f0(tsup − tinf )

KVCO.

τq = T − (i−1)

p = − (i−1)

t = 0inf

τ

ref

div

τ τq = T − (i−1) + (i)

t = 0inf

τp = − (i−1)

ref

div

τ

q = T + (i)

p = (i−1)

ττ

supt = T + (i)

ref

div

τ τ

(i)τt = T +

q(i) = T

τ

(i−1) (i)

sup

p(i) =

> 0, > 0ref

div

t = inf τ

τ τ < 0, < 0(i−1) (i)

sup τ τ τ τ

τ τ < 0, > 0

sup

(i−1) (i)

t = T − (i−1) + (i)

(i−1)

(i−1)

t =

(i)

t = T − (i−1) + (i)

inf τ(i−1)

> 0, < 0τ τ

t

inftp

t sup

q t

Vc

tsuptqinft

p

Vc

p

Vc

qt supt inf

p t

Vc

tinf

t supq

Time-domain solver

We analitically integrate the term on the left (depending on the 4 cases) and, every Trefwe numerically invert the obtained equation.

CP-PLL models Design Example

Outline

1 CP-PLL modelsThe need for accurate PLL modelss-domain modelz-domain modelTime-domain modelComparison between modelsPhase Noise Models

2 Design Example: FrequencySynthesizer for UWB MB-OFDM

UWB communicationsSynthesizer ArchitecturePLLsTuning Range ExtensionMeasured results

CP-PLL models Design Example

Estimated settling time for variable fref/fcs-domain vs. time-domain

z-domain vs. time-domain

10 20 30fref

/ fc

0

5

10

Settl

ing

time

erro

r (%

)

4th

order3

rd order

2nd

order

10 20 30fref

/ fc

0

10

20

30

40

Settl

ing

time

erro

r (%

)

4th

order3

rd order

2nd

order

fz = 0.25fc , τ0 = Tref (wide frequency jump)

Unreliable for fref/fc < 10 (it also fails to predictinstability ).

z-domain for varying τ0, fref ≈ 10fc

Error is deeply influenced by first pulse width.For τ0 → 0, error always goes to zero.

10 20 30fref

/ fc

0

5

10

15

20

25

Settl

ing

time

erro

r (%

)

4th

order3

rd order

2nd

order

10 20 30fref

/ fc

0

10

20

30

Settl

ing

time

erro

r (%

)

4th

order3

rd order

2nd

orderfz = 0.25fc , τ0 = Tref (wide frequency jump)

Error can be higher than for s-domain model dueto large τ0 but predicts instability.

fz = 0.75fc , τ0 = Tref (wide frequency jump)

Higher errors for both models when moving zero from fz = 0.25fc to fz = 0.75fc .

CP-PLL models Design Example

Estimated settling time for variable fref/fcs-domain vs. time-domain z-domain vs. time-domain

10 20 30fref

/ fc

0

5

10

Settl

ing

time

erro

r (%

)

4th

order3

rd order

2nd

order

10 20 30fref

/ fc

0

10

20

30

40

Settl

ing

time

erro

r (%

)

4th

order3

rd order

2nd

order

fz = 0.25fc , τ0 = Tref (wide frequency jump)

Unreliable for fref/fc < 10 (it also fails to predictinstability ).

z-domain for varying τ0, fref ≈ 10fc

Error is deeply influenced by first pulse width.For τ0 → 0, error always goes to zero.

10 20 30fref

/ fc

0

5

10

15

20

25

Settl

ing

time

erro

r (%

)

4th

order3

rd order

2nd

order

10 20 30fref

/ fc

0

10

20

30

Settl

ing

time

erro

r (%

)

4th

order3

rd order

2nd

order

fz = 0.25fc , τ0 = Tref (wide frequency jump)

Error can be higher than for s-domain model dueto large τ0 but predicts instability.

fz = 0.75fc , τ0 = Tref (wide frequency jump)

Higher errors for both models when moving zero from fz = 0.25fc to fz = 0.75fc .

CP-PLL models Design Example

Estimated settling time for variable fref/fcs-domain vs. time-domain z-domain vs. time-domain

10 20 30fref

/ fc

0

5

10

Settl

ing

time

erro

r (%

)

4th

order3

rd order

2nd

order

10 20 30fref

/ fc

0

10

20

30

40

Settl

ing

time

erro

r (%

)

4th

order3

rd order

2nd

order

fz = 0.25fc , τ0 = Tref (wide frequency jump)

Unreliable for fref/fc < 10 (it also fails to predictinstability ).

z-domain for varying τ0, fref ≈ 10fc

Error is deeply influenced by first pulse width.For τ0 → 0, error always goes to zero.

10 20 30fref

/ fc

0

5

10

15

20

25

Settl

ing

time

erro

r (%

)

4th

order3

rd order

2nd

order

10 20 30fref

/ fc

0

10

20

30

Settl

ing

time

erro

r (%

)

4th

order3

rd order

2nd

order

fz = 0.25fc , τ0 = Tref (wide frequency jump)

Error can be higher than for s-domain model dueto large τ0 but predicts instability.

fz = 0.75fc , τ0 = Tref (wide frequency jump)

Higher errors for both models when moving zero from fz = 0.25fc to fz = 0.75fc .

CP-PLL models Design Example

Estimated settling time

for variable fref/fc

z-domain vs. time-domain

10 30 50 70 90b ≈ c

0

10

20

30

40

Settl

ing

time

erro

r %

τ(0)Fref

= 1 τ(0)F

ref = 0.6

τ(0)Fref

= 0.33 τ(0)F

ref = 0.25

10 20 30fref

/ fc

0

10

20

30

40

Settl

ing

time

erro

r (%

)

4th

order3

rd order

2nd

order

fz = 0.25fc , τ0 = Tref (wide frequency jump)

Unreliable for fref/fc < 10 (it also fails to predictinstability ).

z-domain for varying τ0, fref ≈ 10fc

Error is deeply influenced by first pulse width.For τ0 → 0, error always goes to zero.

10 20 30fref

/ fc

0

5

10

15

20

25

Settl

ing

time

erro

r (%

)

4th

order3

rd order

2nd

order

10 20 30fref

/ fc

0

10

20

30

Settl

ing

time

erro

r (%

)

4th

order3

rd order

2nd

order

fz = 0.25fc , τ0 = Tref (wide frequency jump)

Error can be higher than for s-domain model dueto large τ0 but predicts instability.

fz = 0.75fc , τ0 = Tref (wide frequency jump)

Higher errors for both models when moving zero from fz = 0.25fc to fz = 0.75fc .

CP-PLL models Design Example

Outline

1 CP-PLL modelsThe need for accurate PLL modelss-domain modelz-domain modelTime-domain modelComparison between modelsPhase Noise Models

2 Design Example: FrequencySynthesizer for UWB MB-OFDM

UWB communicationsSynthesizer ArchitecturePLLsTuning Range ExtensionMeasured results

CP-PLL models Design Example

s-domain modelCP,n

2π1 G 2π

FD

PFDo,nK

CP

s

LPF VCORef

1

C,n

N

R,n PFD,n

(Fref)

I V

vcoG (s)

θ θ

θ

θ

θ

VCO,n

LF

D,n

Output power spectral density

Sθo,n = ‖TR‖2SθR,n +

+‖TPFD‖2SθPFD,n +

+‖TCP‖2SICP,n

+

+‖TLF‖2SVc,n +

+‖TVCO‖2SθVCO,n +

+‖TD‖2SθD,n

REF

TR =NGc(s)

1 + Gc(s)

DIV

TD = −NGc(s)

1 + Gc(s)

PFD

TPFD =2πG · GLF (s)KVCO

s(1 + Gc(s))

CP

TCP =2πGLF (s)KVCO

s(1 + Gc(s))

LF

TLF =2πKVCO

s(1 + Gc(s))

VCO

TVCO =1

1 + Gc(s)

2N

1

~fc

PNTF

log f

Slopes depend on PLL order

REF

VCO

LF

VCO

REF

TOTAL20log(PNoise)

~fc

VCO noise

(and possibly PFD and CP)low freq REF noise

plateau

log f

CP-PLL models Design Example

s-domain modelCP,n

2π1 G 2π

FD

PFDo,nK

CP

s

LPF VCORef

1

C,n

N

R,n PFD,n

(Fref)

I V

vcoG (s)

θ θ

θ

θ

θ

VCO,n

LF

D,n

Output power spectral density

Sθo,n = ‖TR‖2SθR,n +

+‖TPFD‖2SθPFD,n +

+‖TCP‖2SICP,n

+

+‖TLF‖2SVc,n +

+‖TVCO‖2SθVCO,n +

+‖TD‖2SθD,n

REF

TR =NGc(s)

1 + Gc(s)

DIV

TD = −NGc(s)

1 + Gc(s)

PFD

TPFD =2πG · GLF (s)KVCO

s(1 + Gc(s))

CP

TCP =2πGLF (s)KVCO

s(1 + Gc(s))

LF

TLF =2πKVCO

s(1 + Gc(s))

VCO

TVCO =1

1 + Gc(s)

2N

1

~fc

PNTF

log f

Slopes depend on PLL order

REF

VCO

LF

VCO

REF

TOTAL20log(PNoise)

~fc

VCO noise

(and possibly PFD and CP)low freq REF noise

plateau

log f

CP-PLL models Design Example

s-domain modelCP,n

2π1 G 2π

FD

PFDo,nK

CP

s

LPF VCORef

1

C,n

N

R,n PFD,n

(Fref)

I V

vcoG (s)

θ θ

θ

θ

θ

VCO,n

LF

D,n

Output power spectral density

Sθo,n = ‖TR‖2SθR,n +

+‖TPFD‖2SθPFD,n +

+‖TCP‖2SICP,n

+

+‖TLF‖2SVc,n +

+‖TVCO‖2SθVCO,n +

+‖TD‖2SθD,n

REF

TR =NGc(s)

1 + Gc(s)

DIV

TD = −NGc(s)

1 + Gc(s)

PFD

TPFD =2πG · GLF (s)KVCO

s(1 + Gc(s))

CP

TCP =2πGLF (s)KVCO

s(1 + Gc(s))

LF

TLF =2πKVCO

s(1 + Gc(s))

VCO

TVCO =1

1 + Gc(s)

2N

1

~fc

PNTF

log f

Slopes depend on PLL order

REF

VCO

LF

VCO

REF

TOTAL20log(PNoise)

~fc

VCO noise

(and possibly PFD and CP)low freq REF noise

plateau

log f

CP-PLL models Design Example

s-domain modelCP,n

2π1 G 2π

FD

PFDo,nK

CP

s

LPF VCORef

1

C,n

N

R,n PFD,n

(Fref)

I V

vcoG (s)

θ θ

θ

θ

θ

VCO,n

LF

D,n

Output power spectral density

Sθo,n = ‖TR‖2SθR,n +

+‖TPFD‖2SθPFD,n +

+‖TCP‖2SICP,n

+

+‖TLF‖2SVc,n +

+‖TVCO‖2SθVCO,n +

+‖TD‖2SθD,n

REF

TR =NGc(s)

1 + Gc(s)

DIV

TD = −NGc(s)

1 + Gc(s)

PFD

TPFD =2πG · GLF (s)KVCO

s(1 + Gc(s))

CP

TCP =2πGLF (s)KVCO

s(1 + Gc(s))

LF

TLF =2πKVCO

s(1 + Gc(s))

VCO

TVCO =1

1 + Gc(s)

2N

1

~fc

PNTF

log f

Slopes depend on PLL order

REF

VCO

LF

VCO

REF

TOTAL20log(PNoise)

~fc

VCO noise

(and possibly PFD and CP)low freq REF noise

plateau

log f

CP-PLL models Design Example

Time-domain model

LOOP VCO

DIVIDERFREQ

REF UPF

DN

REF

DIVF

FOUT

DETECTOR FILTERFREQPHASE

PUMPCHARGE

Use time-domain simulator for phase noise analysis

Phase noise injected as random jitter which dithers transitions at block outputs.For DIV and REF jitter is added to PFD misalignment.For VCO directly at its output.For the other blocks noise is first converted to jitter at VCO output.

CP-PLL models Design Example

Comparison Examples

2M 10M 100M

0

20

40 4th

orders-domain

4th

ordertime-domain

2nd

orders-domain

2nd

ordertime-domain

2M 10M 100M

-20

0

20

2M 10M 100M

-40

-20

0

20

40

2M 10M 100M

-20

0

|θo/θ

i|2 P

hase

No

ise T

ran

sfer

Fu

ncti

on

(d

B)

|θo/θ

vco|2

Ph

ase

No

ise T

ran

sfer

Fu

ncti

on

(d

B)

fref

= 66 MHz

fref

= 264 MHz

fref

= 66 MHz

fref

= 264 MHz

(a)

(b)

(c)

(d)

fref /fc ≈ 5

High amount ofout-of-band energy foldedback. Error taken bys-domain analysis onintegrated phase noise isin the order of 80%.

fref /fc ≈ 20

Error taken by s-domainanalysis is in the order of40% (2nd order) and 20%(4th order).

CP-PLL models Design Example

Comparison Examples

2M 10M 100M

0

20

40 4th

orders-domain

4th

ordertime-domain

2nd

orders-domain

2nd

ordertime-domain

2M 10M 100M

-20

0

20

2M 10M 100M

-40

-20

0

20

40

2M 10M 100M

-20

0

|θo/θ

i|2 P

hase

No

ise T

ran

sfer

Fu

ncti

on

(d

B)

|θo/θ

vco|2

Ph

ase

No

ise T

ran

sfer

Fu

ncti

on

(d

B)

fref

= 66 MHz

fref

= 264 MHz

fref

= 66 MHz

fref

= 264 MHz

(a)

(b)

(c)

(d)

fref /fc ≈ 5

High amount ofout-of-band energy foldedback. Error taken bys-domain analysis onintegrated phase noise isin the order of 80%.

fref /fc ≈ 20

Error taken by s-domainanalysis is in the order of40% (2nd order) and 20%(4th order).

CP-PLL models Design Example

Comparison Examples

2M 10M 100M

0

20

40 4th

orders-domain

4th

ordertime-domain

2nd

orders-domain

2nd

ordertime-domain

2M 10M 100M

-20

0

20

2M 10M 100M

-40

-20

0

20

40

2M 10M 100M

-20

0

|θo/θ

i|2 P

hase

No

ise T

ran

sfer

Fu

ncti

on

(d

B)

|θo/θ

vco|2

Ph

ase

No

ise T

ran

sfer

Fu

ncti

on

(d

B)

fref

= 66 MHz

fref

= 264 MHz

fref

= 66 MHz

fref

= 264 MHz

(a)

(b)

(c)

(d)

fref /fc ≈ 5

High amount ofout-of-band energy foldedback. Error taken bys-domain analysis onintegrated phase noise isin the order of 80%.

fref /fc ≈ 20

Error taken by s-domainanalysis is in the order of40% (2nd order) and 20%(4th order).

CP-PLL models Design Example

Comparison Examples

2M 10M 100M

0

20

40 4th

orders-domain

4th

ordertime-domain

2nd

orders-domain

2nd

ordertime-domain

2M 10M 100M

-20

0

20

2M 10M 100M

-40

-20

0

20

40

2M 10M 100M

-20

0

|θo/θ

i|2 P

hase

No

ise T

ran

sfer

Fu

ncti

on

(d

B)

|θo/θ

vco|2

Ph

ase

No

ise T

ran

sfer

Fu

ncti

on

(d

B)

fref

= 66 MHz

fref

= 264 MHz

fref

= 66 MHz

fref

= 264 MHz

(a)

(b)

(c)

(d)

fref /fc ≈ 5

High amount ofout-of-band energy foldedback. Error taken bys-domain analysis onintegrated phase noise isin the order of 80%.

fref /fc ≈ 20

Error taken by s-domainanalysis is in the order of40% (2nd order) and 20%(4th order).

CP-PLL models Design Example

Results

Models comparison

s-domain model can become unreliable if fref/fc < 20.Even z-domain model fails for large frequency jumps.

Time-domain model can be used to efficiently simulatewideband PLLs

Fast enough to be extensively used.It can be easily extended to perform averaged analysis ofphase noise.Model has been validated designing a frequencysynthesizer for UWB MB-OFDM.

CP-PLL models Design Example

Results

Models comparison

s-domain model can become unreliable if fref/fc < 20.Even z-domain model fails for large frequency jumps.Time-domain model can be used to efficiently simulatewideband PLLs

Fast enough to be extensively used.It can be easily extended to perform averaged analysis ofphase noise.Model has been validated designing a frequencysynthesizer for UWB MB-OFDM.

CP-PLL models Design Example

Outline

1 CP-PLL modelsThe need for accurate PLL modelss-domain modelz-domain modelTime-domain modelComparison between modelsPhase Noise Models

2 Design Example: FrequencySynthesizer for UWB MB-OFDM

UWB communicationsSynthesizer ArchitecturePLLsTuning Range ExtensionMeasured results

CP-PLL models Design Example

UWB communications

10 Mb/s 1 Gb/s

100m

10m

1m

1km

10km

100km

b/g n

a

Bluetooth

DATA RATE

RA

NG

E

WiMAX802.16

GSMUMTS HSDPA

Wi − Fi802.11 a/b/g/n

802.15

.3

ZigBee802.15.14

100 kb/s 100 Mb/s1 Mb/s10 kb/s

UWB

Federal Communication Commission

FCC authorizes use of 3.1-to-10.6GHz spectrum.Bandwidth larger than 500MHz.Power spectral density of emission below -41.3 dBm/Hz.

Target applications

Low range (<10m).High data rates (>100Mb/sec).

Personal Area Networks.

CP-PLL models Design Example

UWB communications

10 Mb/s 1 Gb/s

100m

10m

1m

1km

10km

100km

b/g n

a

Bluetooth

DATA RATE

RA

NG

E

WiMAX802.16

GSMUMTS HSDPA

Wi − Fi802.11 a/b/g/n

802.15

.3

ZigBee802.15.14

100 kb/s 100 Mb/s1 Mb/s10 kb/s

UWB

Federal Communication Commission

FCC authorizes use of 3.1-to-10.6GHz spectrum.Bandwidth larger than 500MHz.Power spectral density of emission below -41.3 dBm/Hz.

Target applications

Low range (<10m).High data rates (>100Mb/sec).

Personal Area Networks.

CP-PLL models Design Example

UWB communications

10 Mb/s 1 Gb/s

100m

10m

1m

1km

10km

100km

b/g n

a

Bluetooth

DATA RATE

RA

NG

E

WiMAX802.16

GSMUMTS HSDPA

Wi − Fi802.11 a/b/g/n

802.15

.3

ZigBee802.15.14

100 kb/s 100 Mb/s1 Mb/s10 kb/s

UWB

Federal Communication Commission

FCC authorizes use of 3.1-to-10.6GHz spectrum.Bandwidth larger than 500MHz.Power spectral density of emission below -41.3 dBm/Hz.

Target applications

Low range (<10m).High data rates (>100Mb/sec).

Personal Area Networks.

CP-PLL models Design Example

UWB communications

10 Mb/s 1 Gb/s

100m

10m

1m

1km

10km

100km

b/g n

a

Bluetooth

DATA RATE

RA

NG

E

WiMAX802.16

GSMUMTS HSDPA

Wi − Fi802.11 a/b/g/n

802.15

.3

ZigBee802.15.14

100 kb/s 100 Mb/s1 Mb/s10 kb/s

UWB

Federal Communication Commission

FCC authorizes use of 3.1-to-10.6GHz spectrum.Bandwidth larger than 500MHz.Power spectral density of emission below -41.3 dBm/Hz.

Target applications

Low range (<10m).High data rates (>100Mb/sec).Personal Area Networks.

CP-PLL models Design Example

UWB MB-OFDM

554450164488

343292406072

6600

CENTERFREQ

EUROPE

KOREA

JAPAN

USA

IN MHz

GROUP 1 GROUP 2 GROUP 4GROUP 3 GROUP 5

AVOIDDETECT ANDAVAILABLE WITH NOT

AVAILABLEAVAILABLE

10296976887128184

76563960 7128

WiMedia Alliance Proposal

ECMA standards 368 and 369.Data rates up to 480 Mb/sec.QPSK or DCM modulation schemes.

ECMA standard

OFDM symbol last 242.42ns plus 70.08ns for zero-padded suffix.Switching between bands every 312.5ns.9.5ns of guard interval.

CP-PLL models Design Example

UWB MB-OFDM

554450164488

343292406072

6600

CENTERFREQ

EUROPE

KOREA

JAPAN

USA

IN MHz

GROUP 1 GROUP 2 GROUP 4GROUP 3 GROUP 5

AVOIDDETECT ANDAVAILABLE WITH NOT

AVAILABLEAVAILABLE

10296976887128184

76563960 7128

WiMedia Alliance Proposal

ECMA standards 368 and 369.Data rates up to 480 Mb/sec.QPSK or DCM modulation schemes.

ECMA standard

14 bands organized in 6 band groups.MultiBand Orthogonal Frequency Division Multiplexing (MB-OFDM).Different subsets of frequencies allowed outside US.

CP-PLL models Design Example

UWB MB-OFDM

554450164488

343292406072

6600

CENTERFREQ

EUROPE

KOREA

JAPAN

USA

IN MHz

GROUP 1 GROUP 2 GROUP 4GROUP 3 GROUP 5

AVOIDDETECT ANDAVAILABLE WITH NOT

AVAILABLEAVAILABLE

10296976887128184

76563960 7128

WiMedia Alliance Proposal

ECMA standards 368 and 369.Data rates up to 480 Mb/sec.QPSK or DCM modulation schemes.

ECMA standard

14 bands organized in 6 band groups.MultiBand Orthogonal Frequency Division Multiplexing (MB-OFDM).Different subsets of frequencies allowed outside US.

CP-PLL models Design Example

UWB MB-OFDM

554450164488

343292406072

6600

CENTERFREQ

EUROPE

KOREA

JAPAN

USA

IN MHz

GROUP 1 GROUP 2 GROUP 4GROUP 3 GROUP 5

AVOIDDETECT ANDAVAILABLE WITH NOT

AVAILABLEAVAILABLE

10296976887128184

76563960 7128

WiMedia Alliance Proposal

ECMA standards 368 and 369.Data rates up to 480 Mb/sec.QPSK or DCM modulation schemes.

ECMA standard

OFDM symbol last 242.42ns plus 70.08ns for zero-padded suffix.Switching between bands every 312.5ns.9.5ns of guard interval.

CP-PLL models Design Example

UWB MB-OFDM Transceiver

T/R

PA I/Q

I/QLNA VGA

OSCLOCAL

CP-PLL models Design Example

Outline

1 CP-PLL modelsThe need for accurate PLL modelss-domain modelz-domain modelTime-domain modelComparison between modelsPhase Noise Models

2 Design Example: FrequencySynthesizer for UWB MB-OFDM

UWB communicationsSynthesizer ArchitecturePLLsTuning Range ExtensionMeasured results

CP-PLL models Design Example

Target Specifications

System specificationsFrequency range: 3432-to-10296MHz.14 center frequencies to be synthesized.Integrated Phase noise below 3.6o

RMS.Aggregate power of spurs lower than -24dBc.Frequency switching time (for bands in the same group)lower than 9.5ns.

CP-PLL models Design Example

Architecture

66 MHz

PLL

WIDEBAND

WIDEBAND

PLL

TREC

TREC

X

TCXO

U

IC

M

CONTROL

Classic solutions

Multiple fixed-frequency PLLs not suitable for full spectrum coverage.

State-of-the-art solutions generally make use of fixed frequency PLLsand extensive mixing.

Area overhead due to the presence of inductors for band-pass filtering.High power consumption.

Proposed solution

Two PLLs synthesize frequencies in the 6.6-to-10.3GHz range.Two circuits extend the tuning range down to 3.4GHz.MUX switches between the two output every 312.5ns.

CP-PLL models Design Example

Architecture

66 MHz

PLL

WIDEBAND

WIDEBAND

PLL

TREC

TREC

X

TCXO

U

IC

M

CONTROL

Classic solutions

Multiple fixed-frequency PLLs not suitable for full spectrum coverage.

State-of-the-art solutions generally make use of fixed frequency PLLsand extensive mixing.

Area overhead due to the presence of inductors for band-pass filtering.High power consumption.

Proposed solution

Two PLLs synthesize frequencies in the 6.6-to-10.3GHz range.Two circuits extend the tuning range down to 3.4GHz.MUX switches between the two output every 312.5ns.

CP-PLL models Design Example

Architecture

66 MHz

PLL

WIDEBAND

WIDEBAND

PLL

TREC

TREC

X

TCXO

U

IC

M

CONTROL

Classic solutions

Multiple fixed-frequency PLLs not suitable for full spectrum coverage.

State-of-the-art solutions generally make use of fixed frequency PLLsand extensive mixing.

Area overhead due to the presence of inductors for band-pass filtering.High power consumption.

Proposed solution

Two PLLs synthesize frequencies in the 6.6-to-10.3GHz range.Two circuits extend the tuning range down to 3.4GHz.MUX switches between the two output every 312.5ns.

CP-PLL models Design Example

Outline

1 CP-PLL modelsThe need for accurate PLL modelss-domain modelz-domain modelTime-domain modelComparison between modelsPhase Noise Models

2 Design Example: FrequencySynthesizer for UWB MB-OFDM

UWB communicationsSynthesizer ArchitecturePLLsTuning Range ExtensionMeasured results

CP-PLL models Design Example

PLL high level design and simulations

Loop design

Fourth-order loop.Open-loop unit gain frequency8MHz.

Reference frequency of 66MHz.

Requires time-domainsimulations.Can be derived directly from acrystal oscillator.Allows the use Divide-by-2CML prescaler.

CP current digitallyprogrammable.

/104 −> /156

Gm

Fref

vcoFPFD

CP

R

D DN

UP

LF

CMOS

CML2 CML

/2divider/16 −> /132

Dynamicprogrammable

LC−QVCO

FD

ctrlDigital

Fref 66MHzICP 200-400µA

KVCO ≈600 to 2000MHz/VN 100-156fc 8MHzfp 30 and 60MHz

CP-PLL models Design Example

PLL high level design and simulations

Loop design

Fourth-order loop.Open-loop unit gain frequency8MHz.

Reference frequency of 66MHz.Requires time-domainsimulations.Can be derived directly from acrystal oscillator.Allows the use Divide-by-2CML prescaler.

CP current digitallyprogrammable.

/104 −> /156

Gm

Fref

vcoFPFD

CP

R

D DN

UP

LF

CMOS

CML2 CML

/2divider/16 −> /132

Dynamicprogrammable

LC−QVCO

FD

ctrlDigital

Fref 66MHzICP 200-400µA

KVCO ≈600 to 2000MHz/VN 100-156fc 8MHzfp 30 and 60MHz

CP-PLL models Design Example

PLL high level design and simulations

Loop design

Fourth-order loop.Open-loop unit gain frequency8MHz.

Reference frequency of 66MHz.Requires time-domainsimulations.Can be derived directly from acrystal oscillator.Allows the use Divide-by-2CML prescaler.

CP current digitallyprogrammable.

/104 −> /156

Gm

Fref

vcoFPFD

CP

R

D DN

UP

LF

CMOS

CML2 CML

/2divider/16 −> /132

Dynamicprogrammable

LC−QVCO

FD

ctrlDigital

Fref 66MHzICP 200-400µA

KVCO ≈600 to 2000MHz/VN 100-156fc 8MHzfp 30 and 60MHz

CP-PLL models Design Example

PLL high level design and simulations

Loop design

Fourth-order loop.Open-loop unit gain frequency8MHz.

Reference frequency of 66MHz.Requires time-domainsimulations.Can be derived directly from acrystal oscillator.Allows the use Divide-by-2CML prescaler.

CP current digitallyprogrammable.

/104 −> /156

Gm

Fref

vcoFPFD

CP

R

D DN

UP

LF

CMOS

CML2 CML

/2divider/16 −> /132

Dynamicprogrammable

LC−QVCO

FD

ctrlDigital

Fref 66MHzICP 200-400µA

KVCO ≈600 to 2000MHz/VN 100-156fc 8MHzfp 30 and 60MHz

CP-PLL models Design Example

Outline

1 CP-PLL modelsThe need for accurate PLL modelss-domain modelz-domain modelTime-domain modelComparison between modelsPhase Noise Models

2 Design Example: FrequencySynthesizer for UWB MB-OFDM

UWB communicationsSynthesizer ArchitecturePLLsTuning Range ExtensionMeasured results

CP-PLL models Design Example

Tuning Range Extension Circuit

vco

F21F

vcoF

DC

F DIVIDERby 2

SSBMs

SSBM

outF =

XU

XUM

M

1

0

1

0

1S

0S

DC

DIV

vcoF

FOUT (MHz) DIV S0S1 FVCO (MHz) F1(MHz) F2(MHz)3432 2 1 0 6864 6864 34323960 2 1 0 7920 7920 39604488 2 1 0 8976 8976 4488

5016 1.5 0 0 7524 5016 25085544 1.5 0 0 8316 5544 27726072 1.5 0 0 9108 6072 3036

6600-10296 1 X 1 6600-10296 - -

CP-PLL models Design Example

Tuning Range Extension Circuit

vco

F21F

vcoF

DC

F DIVIDERby 2

SSBMs

SSBM

outF =

XU

XUM

M

1

0

1

0

1S

0S

DC

DIV

vcoF

FOUT (MHz) DIV S0S1 FVCO (MHz) F1(MHz) F2(MHz)3432 2 1 0 6864 6864 34323960 2 1 0 7920 7920 39604488 2 1 0 8976 8976 4488

5016 1.5 0 0 7524 5016 25085544 1.5 0 0 8316 5544 27726072 1.5 0 0 9108 6072 3036

6600-10296 1 X 1 6600-10296 - -

CP-PLL models Design Example

Tuning Range Extension Circuit

vco

F21F

vcoF

DC

F DIVIDERby 2

SSBMs

SSBM

outF =

XU

XUM

M

1

0

1

0

1S

0S

DC

DIV

vcoF

FOUT (MHz) DIV S0S1 FVCO (MHz) F1(MHz) F2(MHz)3432 2 1 0 6864 6864 34323960 2 1 0 7920 7920 39604488 2 1 0 8976 8976 44885016 1.5 0 0 7524 5016 25085544 1.5 0 0 8316 5544 27726072 1.5 0 0 9108 6072 3036

6600-10296 1 X 1 6600-10296 - -

CP-PLL models Design Example

Tuning Range Extension Circuit

vco

F21F

vcoF

DC

F DIVIDERby 2

SSBMs

SSBM

outF =

XU

XUM

M

1

0

1

0

1S

0S

DC

DIV

vcoF

FOUT (MHz) DIV S0S1 FVCO (MHz) F1(MHz) F2(MHz)3432 2 1 0 6864 6864 34323960 2 1 0 7920 7920 39604488 2 1 0 8976 8976 44885016 1.5 0 0 7524 5016 25085544 1.5 0 0 8316 5544 27726072 1.5 0 0 9108 6072 3036

6600-10296 1 X 1 6600-10296 - -

CP-PLL models Design Example

Outline

1 CP-PLL modelsThe need for accurate PLL modelss-domain modelz-domain modelTime-domain modelComparison between modelsPhase Noise Models

2 Design Example: FrequencySynthesizer for UWB MB-OFDM

UWB communicationsSynthesizer ArchitecturePLLsTuning Range ExtensionMeasured results

CP-PLL models Design Example

Test chip

DieTSMC 90nm CMOSprocess.Die area 2x2mm2.Core area 0.5mm2.

QVCOs 85%Loop filters 12%

Charge Pumps 1.5%TRECs <1%Dividers <1%PFDs <1%

CP-PLL models Design Example

Test chip

DieTSMC 90nm CMOSprocess.Die area 2x2mm2.Core area 0.5mm2.

QVCOs 85%Loop filters 12%

Charge Pumps 1.5%TRECs <1%Dividers <1%PFDs <1%

CP-PLL models Design Example

Output spectra (3.4-9.2GHz range)

Output Spectra of the synthesizer

Band 1 (TREC divides by 2).

Band 4 (TREC divides by 1.5).Band 7 (TREC acts as buffer).Highest spur is at -32dBc.

CP-PLL models Design Example

Output spectra (3.4-9.2GHz range)

Output Spectra of the synthesizer

Band 1 (TREC divides by 2).Band 4 (TREC divides by 1.5).

Band 7 (TREC acts as buffer).Highest spur is at -32dBc.

CP-PLL models Design Example

Output spectra (3.4-9.2GHz range)

Output Spectra of the synthesizer

Band 1 (TREC divides by 2).Band 4 (TREC divides by 1.5).Band 7 (TREC acts as buffer).

Highest spur is at -32dBc.

CP-PLL models Design Example

Output spectra (3.4-9.2GHz range)

Output Spectra of the synthesizer

Band 1 (TREC divides by 2).Band 4 (TREC divides by 1.5).Band 7 (TREC acts as buffer).Highest spur is at -32dBc.

CP-PLL models Design Example

Output spectra (3.4-9.2GHz range)

Output Spectra of the synthesizer

Highest reference spur at -39dBc.Aggregate spur power -27dBc.Specifications require -24dBc.

Highest spur is at -32dBc.

CP-PLL models Design Example

Phase Noise

Spectrum close-in (1MHz wide).

Phase noise -107dBc/Hz at 50KHz.Phase noise -110dBc/Hz at 100KHz.Some spurs due to digital noise.

Integrated Phase noise.

1.1oRMS at 3432MHz.

2.8oRMS at 9240MHz.

Estimated 3.1oRMS at 10296MHz.

Specification 3.6oRMS .

CP-PLL models Design Example

Phase Noise

Spectrum close-in (1MHz wide).

Phase noise -107dBc/Hz at 50KHz.Phase noise -110dBc/Hz at 100KHz.Some spurs due to digital noise.

Integrated Phase noise.

1.1oRMS at 3432MHz.

2.8oRMS at 9240MHz.

Estimated 3.1oRMS at 10296MHz.

Specification 3.6oRMS .

CP-PLL models Design Example

Frequency switching behavior

VCOs control voltages

First PLL settles in Ta.Second PLL settles in Tb.

Simulated data points are minimumand maximum values for eachreference period.Filtering effect due to capacitive loadon control voltages buffers.Settling time estimated to be below300ns.

CP-PLL models Design Example

Frequency switching behavior

VCOs control voltages

First PLL settles in Ta.Second PLL settles in Tb.Simulated data points are minimumand maximum values for eachreference period.Filtering effect due to capacitive loadon control voltages buffers.Settling time estimated to be below300ns.

CP-PLL models Design Example

Results and comparison with previous solutions

[1] [2] [3] This workTechnology 180nm CMOS 180nm CMOS 180nm CMOS 90nm CMOS

Vsupply 1.8V 1.8V 1.8V 1.2/1.8VFout 3432-10296 MHz 3432-10296 MHz 6336-8976 MHz 3432-9240 MHzFref 264MHz 66MHz 528MHz 66MHz

Phase -98dBc/Hz - -109.6dBc/Hz -99dBc/Hznoise @1MHz, @1MHz @100KHzSpurs -33dBc -35dBc -52dBc -32dBcPower 117mW 162mW 58mW 55mWArea 2.5x2.2mm2 1.2x1.3mm2 0.7x1.1mm2 0.5mm2

(full chip) (core) (single PLL core) (core)

Comparison

Joint power consumption and area occupation are better than state-of-the-artsolutions.1 Che-Fu Liang et al., ISSCC2006. 2 Wei-Zen Chen Tai-You Lu, ISSCC2008.3 Geum-Young Tak et al., JSSCC2005.