frequency and voltage planning for multi-core processors

Frequency and Voltage Planning for Multi-Core ProcessorsUnder Thermal Constraints

Michael Kadin and Sherief RedaDivision of Engineering

Brown UniversityProvidence, RI 02912

Email: {michael kadin, sherief reda}@brown.edu

Abstract— Clock frequency and transistor density increaseshave resulted in elevated chip temperatures. In order to meettemperature constraints while still exploiting the performanceopportunities enabled by continued scaling, chip designers havemigrated towards multi-core architectures. Multi-core architec-tures use multiple cores running at moderate clock frequenciesto run several threads concurrently, which increases overallsystem throughput. In this work, we propose novel methodsto find the optimal operating parameters, i.e., frequency andvoltage, that maximize a multi-core system throughput underthermal constraints. By adjusting core clock frequencies andvoltages, on-chip power dissipation can be spatially and tem-porally distributed to maximize the chip’s physical performanceduring runtime. We propose a simple, yet efficient modelthat accurately characterize the effects that changes in clockfrequency and voltage have on on-chip temperatures. Usingthe model, we find the optimal operating conditions for thefollowing scenarios: (1) standard processor performance, wherevarious cores operate using identical operating parameters,(2) optimal processor performance where each core can haveits own frequency and voltage, and (3) optimal processorperformance with thread priorities, where each core runs athread of varied importance. We run several experiments acrosssix different technology nodes to validate the work, assuringthat our models and methods are accurate. Our methodsdemonstrate the total physical performance of a multi-coresystem can be increased by up to 33.4% without violating themaximum temperature constraints.

I. INTRODUCTION AND MOTIVATION

Technology scaling enables doubling the number of tran-sistors per unit area with every technology scaling. In idealscaling, supply voltages are scaled down appropriately toreduce the power density. However, thermal noise, processvariations, and less-than-ideal scaling of the threshold volt-age have slowed the scaling of supply voltages. Withoutideal voltage scaling, on-chip power density increases withnew technology generations, which leads to higher on-chiptemperatures. Elevated temperatures are traditionally tackledby removing the dissipated heat with improved packagingtechnology and active cooling systems. However, improve-ments in packaging techniques are expensive, complex, andbulky, making them economically and ergonomically ex-pensive. High temperatures increase sub-threshold leakagecurrent, which increases the overall processor power con-sumption. Furthermore, increased temperatures also increasethe circuit delay, decrease the mean time to failure, and can

cause permanent physical damage to the chip. In general,increased on-chip temperatures are detrimental to processorperformance, power, and reliability. Thus, new solutions tothe “thermal wall” are needed.

Despite that smaller transistors have the potential to be runat high frequencies, thermal constraints continue to restricttheir operating frequencies. Chip designers have alleviatedthe thermal complications through the use of multi-corearchitectures, which continue to increase system throughputby utilizing the chip area created by scaling. Rather thanfocusing on improving the single-thread performance, multi-core architectures have several independent cores that con-currently compute different threads. However, since there areseveral independent processing units, running them at mod-erate frequencies does still permit large performance gains.With an ideal amount of thread level parallelism (TLP),performance can approximately double with each technologygeneration. However, a given workload has a fundamentallimit on extractable concurrency. Thus, situations may occurwhere all of the cores in a multi-core processor may not bein use. In fact, coding and compiling for TLP is one of themost difficult challenges of multi-core processors.

In recent years, dynamic thermal management (DTM) hasemerged as a method to deal with thermal constraints instate-of-the-art processors. DTM methods read in the currentthermal state of a processor, either directly using temperaturesensors or indirectly using performance counters, and makechanges to processor parameters to appropriately adjust thetemperature. Most DTM techniques impose some form ofperformance penalty. For example, decreasing the pipelineissue width will decrease the number of switching transistors,and thus, the amount of power dissipated, but will alsoincrease the cycles per instuction. Research into DTM tech-niques attempts to maintain temperature constraints, whileminimizing performance degradation. One of the importanttechniques in DTM is the ability to dynamically controlthe individual physical operating parameters, i.e., frequencyand voltage, of each core. Dynamic Frequency and VoltageScaling (DVFS) can be used to throttle the processor perfor-mance at any time to reduce elevated temperatures [3], [13].Upcoming processor designs offer multiple cores, each withits own clock tree and power network (e.g. AMD quad-corePhenom Processor [2]). This can facilitate the application of

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DVFS techniques at the core level.Our work seeks to find the optimal frequency and voltage

setting of each core in a multi-core system such that animposed thermal constraint is not violated during runtime andthe total physical performance is maximized. For this work,total physical performance is defined as the sum of clockfrequencies of all cores. While not entirely accurate, thesum of frequencies is a reasonable choice, and it is typicallycorrelated with the total system throughput, especially if allworkload threads are independent. In many-core systems,finding the optimal operating parameter settings throughexhaustive enumeration is computationally infeasible dueto the large search space and certainly is not possible toachieve during runtime. Thus, to find the optimal frequenciesand voltages during runtime, it is necessary to abstract aprocessor’s design into a mathematical formulation that canbe quickly solved during runtime under various optimizationobjectives and constraints.

For the given problem in hand, formulating such a math-ematical model is difficult for a number of reasons. First,within the chip, heat is transferred in all three dimensions.Thus, power released by units within the processor can travelout of the chip via the package, or be transmitted laterallyto other units nearby. Thus, the temperature of a sectionof the die is not only dependent on the power dissipatedin that section, but also on nearby areas’ power. A secondmodeling complication arises from coupling between powerand temperature. Leakage current increases with increasingtemperature. However, temperature is a power dependentquantity. With increasing power comes increasing tempera-ture, which in turn increases power more. Therefore, temper-ature and power are coupled through Leakage Dependenceon Temperature (LDT). Third, cores exhibit spatial variationsin temperature. In other words, power is not uniformlydissipated across a core; one area within a core may be sig-nificantly hotter than another. A fourth complication comeswith changes in process parameters at different technologynodes. Examinations of current technology nodes (65nm)may not be applicable to future nodes (45nm, 32nm, andbeyond). Lastly, these models are complicated by the factthat different workloads may use different core modules atdifferent rates. This means that one workload may heat onepart of the chip a great deal, while another workload maybe power intensive in a totally different section of the die.

Our modeling and learning techniques attempt to addressall of the aforementioned challenges. In particular, the majorcontributions of our method are as follows.• Using machine learning techniques, we propose a ther-

mal characterization model for multi-core systems thatproduces accurate temperatures given the individualcore operating frequencies, voltages, and workloads.The model incorporates both vertical and horizontal heattransfer and the leakage dependence on temperature.This characterization is achieved during runtime usingthe temperatures observed from the on-die thermalsensors.

• We use the parameters of the power-thermal model

to formulate a design optimization space using linearprogramming. An exploration of this space quicklygives the potential performance improvements in multi-core systems with thermal constraints.

• We propose using the model and optimization tech-niques during processor operation with multiple threadpriorities. In this scheme, cores will run threads ofvarying importance. The operating system can assignthe optimal frequencies and voltages to the cores sothat critical threads are completed more quickly withoutviolating temperature constraints.

• The models, methods, and optimizations are all testedon several systems and core arrangements, at severaltechnology nodes. In addition, the results are validatedusing previously confirmed full-scale power and thermalmodels. The results show that it is possible to boost thephysical performance of multi-core processors by upto 33.4% without violating thermal constraints. Mostimportantly, our optimizations can be executed withinexisting multi-core system designs.

The organization of rest of this paper is as follows. SectionII provides a brief overview of recent existing research ideasin this field. Section III provides the main methodologybehind our proposed approach. Section IV provides the mainexperimental results ideas of this approach. Finally, the mainconclusions of this work are provided in Section V.

II. PREVIOUS WORK

There has been much DTM research focusing on methodsfor recovering from thermal emergencies [6], [13], [11], [16],[18] These works center mostly on what to do when a chip’stemperature rises above a certain threshold. Our work, onthe other hand, focuses on maximizing performance under agiven steady-state temperature constraint. In other words, weseek to keep temperature at a reasonably constant level byworking with some of the same parameters that are utilizedin the emergency DTM techniques. Even in our steady-statemethods, however, temperatures may fluctuate with codeintensity and external factors such as ambient temperature.Therefore, it is still possible that sections of the chip mayreach emergency temperatures. Thus, our methodology is de-signed to complement existing DTM techniques to maximizeprocessor throughput while still assuring that the chip willnever reach extreme temperatures.

Several recent works have been conducted along similarlines to our work. Rao et al. [15] develop system levelexpressions for number/speed of active of cores with thermalconstraints. The goal in this work shares similarities toour own: a method for determining system-level parametersin thermal management environments. However, their workignores lateral heat transfer, which was shown in [13] to beof critical importance. For example, Skadron [17] commentsthat the horizontal heat transfer path can account for up to30% of heat transfer. In another recent work Murali et al. [14]propose the use of convex optimization methods to solve theproblem of temperature-aware processor frequency assign-ments. However, their work does not offer a clear, generic

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method to calculate the parameters of the convex model,and they do not report the speedups achieved while usingthe proposed method in comparison to traditional frequencyassignment. Furthermore, the reported runtime required tosolve their problem formulations takes “less than few hours”which reduces the method’s utility in the proposed runtimesetting. Solutions to our proposed models can be solved veryquickly (typically in less than a millisecond). Herbert andMarculescu [8] examine the success of three different DVFSschemes at varying levels of voltage-frequency island granu-larity on a multi-core processor. Their experiments comparethe improvements in energy efficiency for different numbersof islands on chip. The results show that for a 16 core chip,the increases in energy efficiency for assigning individualfrequencies and voltages to each core were eclipsed by theincreases in cost and complexity. However, the authors onlyinvestigated the possibility of improving energy efficiency.Donald and Martonosi [6] show, that individual controlof core operating parameters will bring huge performancebenefits in the context of thermal management, and notjust energy efficiency. These performance improvements willshow that there is a great deal of interest in having anindependent voltage/frequency island for each core in amulti-core processor.

III. PROPOSED METHODOLOGY: FREQUENCY ANDVOLTAGE PLANNING

To apply any required optimizations, it is first importantto abstract the processor thermal behavior in terms of itsoperating parameters in a mathematical model that can bequickly solved during runtime. We propose to use machinelearning (ML) models to achieve this objective. Potential MLmodels include linear, nonlinear and geometric models [1].It is important to carry out some analysis of the system inorder to choose an appropriate ML model. If the model istoo simple, it is too constrained and its results might deviatesubstantially from the observed results, and if the model istoo complex, it might require unnecessary amount of timefor training.

A. Frequency Planning

We first develop a model for frequency planning formulti-core processors. In this subsection we assume that allcores operate at the maximum voltage Vmax regardless ofthe differences in their frequencies, and in Subsection III-B, we adjust the model to account for voltage planning aswell. Towards proposing a reasonable ML model, we utilizethe well known duality between RC circuits and thermalsystems. In these thermal RC models, temperature is anal-ogous to voltage, and current is analogous to heat transfer.Resistances represent paths of heat transfer, current sourcesrepresent power dissipation, and voltage sources representconstant temperature sources. Thermal capacitors, representthe ability to store heat, and are included in transient analysis(as opposed to steady-state) to model the time dependantchanges in temperature. Consider a very simple system withtwo “generic” functional units as shown in Figure 1. In the

Unit 0 � � � � � � �

�

Fig. 1. A simple example of heat transfer models.

figure, unit 0 connects to unit 1 via a thermal resistance Ra.Both units are connected to the package through additionalthermal resistances R0 and R1. The package is then connectedto the ambient air through Rp. Each unit also generates itsown power, P0 and P1, which is modeled as a thermal currentsource. In this work, we model the steady-state junctiontemperature. Therefore, thermal capacitors are fully chargedand can be omitted. Solving Kirchhoff’s Current Law for theabove system yields the following results for unit 0:

t0 =RaRp +RaR0 +R1R0 +RpR0 +RpR1

R1 +R0 +Rap0 +

RaRp +RpR0 +R1R0 +RpR1

R1 +R0 +Rap1,

which can be succinctly described by t0 = λ0,0 p0 + λ0,1 p1.The values of λ s depend on the processor design and theruntime conditions. Thus, our objective is to avoid explicitcalculation of the values of λ s and to rather learn themduring runtime using the measurements of the on-die thermalsensors. For a generic N unit system, we write the temper-ature at some unit i as

ti =N

∑j=1

λi, j p j (1)

In addition, we propose that the total power (static anddynamic) of a unit can be approximated as a linear functionof its frequency. Therefore, if we assume a constant supplyvoltage, the power of a given unit j can be approximatedby p j = a j f j +b j, where a j models the direct impact of fre-quency on dynamic power and its indirect impact on leakage,and b j gives the nominal leakage power. Substituting thepower model in Equation 1 yields

ti =N

∑j=1

λi, j(a j f j +b j) (2)

=N

∑j=1

λi, ja j f j +N

∑j=1

λi, jb j (3)

=N

∑j=1

πi, j f j +θi (4)

where πi, j and θi are the model parameters to be learned. Tolearn the values of the model parameters, we apply k differentinput sets of frequencies on the different cores and measurethe temperatures of different units using the on-chip thermal

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Fig. 2. Layout of 16 cores with a total of 276 units.

diodes. Let ti,k denote the kth measured temperature at unit i,and let f j,k denote the kth applied frequency to core j. Thenthe measured temperatures at unit i due to the application ofk sets of frequencies on a N-core processor can be describedby

Ti =

ti,1ti,2..

ti,k

=

1 f1,1 · · · fN,11 f1,2 · · · fN,2· · · · · ·1 f1,k · · · fN,k

θ

πi,1πi,2··

πi,N

= AΠi,

(5)which can be written succinctly in matrix notation asTi = AΠi. For example, Figure 2 shows the layout of a 16core system based on the Alpha EV6 processor core. Inthe system each core has an 17 individual units, and thecache consists of four large blocks. Thus, the total numberof units where the temperature should be ideally measuredis equal to 17× 16 + 4 = 276. Thus the model parameters,defined by the Πi’s, have a total of 276× (16 + 1) = 4692parameters to be learned for all units.

Learning the Model Parameters. Given the ML model, ourobjective is to learn the ML model parameters, i.e., Πi for1≤ i≤N, that give temperature results AΠi that are “closest”to the observed temperature measurements Ti. The closesttemperatures are the ones minimize the average squared errorbetween some k observed and calculated temperatures, i.e.,minΠi ||AΠi−Tobs||2. Using least square error estimation, thebest parameter estimate is given by

Πi = (AT A)−1AT Ti. (6)

Model-based Optimizations. For a given temperature con-straints Tmax, the inequality

AΠi ≤ Tmax (7)

defines the polytope of feasible core frequencies that do notexceed the specified thermal constraints at any unit in theprocessor. Our objective to find the point in this polytopethat maximizes the total processor performance composedof m cores as defined by

maxm

∑i=1

wi fi, (8)

where wi is the weight, or relative importance, of the threadrunning on core i. Such optimization can be carried outusing well-established Linear Programming (LP) techniques.We also add to the linear program two constraints fi ≥ fmin,which bounds the minimum operating frequency of eachcore, and fi ≤ fmax, where fmax is the maximum frequencythat a core can run on without leading to timing violations.

Dynamic Planning. One of the most difficult aspects ofthe change to multi-core architectures will be designing andcompiling code from which a great deal of TLP can beextracted. Therefore, there will be unavoidable situationswhere the number of computable threads and the numberof cores may be different. In the case where the numberof “ready” threads is greater than the number of cores, theoperating system will select which threads are to be runon the available cores. In the case where the number ofcores exceeds the number of threads, the processing power ofthe vacant cores will be wasted. To lower the performancepenalty imposed by the stalled cores, we can increase thespeed of the cores with active threads. Assigning frequenciesto the active cores can easily be accomplished by finding thesolution to our linear program. However, in this approach,the weight constants of this objective function in (8) will notall be unity. Instead, inactive cores should have no priority(weight constant will be 0) and active cores will all haveequal priority (weight constants will be equal).

B. Frequency and Voltage Planning

The derived frequency plans in the previous subsectionassume that all cores run at Vmax. Our objective in thissubsection is to adjust the voltage of each core to furthermaximize the performance without compromising the tem-perature constraints. Because dynamic power scales withthe square of voltage, and static power scales directly withvoltage, directly incorporating voltage into our ML modelwill transform our model from a linear one to a non-linearone, which compromises the optimization runtime as well itspracticality. Thus we develop a heuristic model to calculatethe voltage plan from a given frequency plan.

In deriving the optimal frequency plan in the previoussubsection, we assumed that a core had a specified maximumfrequency fmax, and an operating voltage Vmax. In thissubsection, we follow in suit with [14] and assume that acore running with a frequency f j < fmax can have its voltagescaled down as follows

Vj( f j) = Vmax

√f j

fmax. (9)

A frequency plan finds the optimal frequency for each coref p

j on the assumption that all cores run at the same maximumvoltage Vmax. We note that setting the voltage of unit j tobe equal to Vj( f p

j ) would reduce its power consumption

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1 1.5 2 2.5 30

0.5

1

1.5

Frequency (GHz)

Volta

ge (V

)

operating point obtained by frequency and voltage planning

operating point obtained by frequency planning

constant power

voltage limit

Fig. 3. Illustrating the impact of voltage planning after frequency planning.The solid blue line shows the the minimum voltage that the circuit needs tooperate on using Equation 9. The dashed red line gives the frequency andvoltage of a unit that leads to constant power.

and temperature of unit j, essentially wasting the oppor-tunity to leverage the voltage “knob” to further increasethe unit’s frequency. Thus, given frequency f p

j of unit jwe first calculate the unit’s power consumption assumingVmax. Then we calculate the maximum frequency f j, wheref p

j ≤ f j ≤ fmax, together with the minimum voltage Vj, whereVj( f j)≤Vj ≤Vmax, and such that the power of unit j remainsunchanged. In essence our method increases the frequency ofa unit while at the same time decreases its operating voltage,such that the power profile, and consequently temperature,stays unaltered. Such adjustment can be carried out as longas timing violations do not occur, which can be guaranteedif the voltage is no less than the limit given by Equation(9). Our procedure is illustrated in Figure 3, where we plotthe lower bound on operating voltage given by equation (9)using the solid blue line. The dashed red line represent theconstant power contour of a processor unit, where frequencyand voltage vary along the line to maintain the power. Thestarting point of the dashed line, at 1.6Ghz and 1.3V, is theresult of the frequency plan, and the intersection betweenthe two lines gives the maximum frequency and minimumvoltage that the unit can operate on while maintaining thesame power profile and consequently the temperature.

IV. EXPERIMENTAL RESULTS

To simulate the runtime behavior of a multi-core processor,we setup a simulation infrastructure with widely-used toolsas described in Subsection IV-A. Then we describe how togenerate a number of processor configurations for differenttechnology nodes in Subsection IV-B. And Subsection IV-Cgives the results of our optimal planning techniques.

A. Simulation Infrastructure

First, it is necessary to set up a tool chain or simulationinfrastructure to simulate the impact of changing the frequen-cies, voltages and workloads on the temperatures of variousprocessor units during runtime. Our tool chain (shown inFigure 4) takes as inputs: the individual cores operatingparameters, the specification of the processor circuitry, and

Fig. 4. General tool chain for simulation infrastructure. PTScalar (whichuses Wattch-like calculation) is used to calculate dynamic power traces fromthe given instruction traces of the workloads. CACTI and PTScalar are usedfor leakage power simulations. HotSpot is used for thermal simulations.

the workload tasks that the system will run on the cores.Using these input parameters, the dynamic power of eachunit is calculated and then fed into a thermal simulator. Oncethe temperatures have been calculated, they are fed into theleakage calculator to compute the leakage of each unit. Theleakage power is then added to the original dynamic powervalues, and new temperatures are calculated. The process isiterated until the temperatures converge. The process usuallytakes ten iterations or less to reach stable convergence. Tocompute the power and temperature values, we use thefollowing established tools.• For dynamic power simulation we use PTScalar [12].

PTScalar is a Wattch-like [4] power simulator built asan extension of the of Simple-Scalar toolset. Simple-Scalar [5] is a cycle-accurate performance simulator formodern out-of-order processors. PTScalar is an exten-sion of this tool that models per-cycle power dissipationat the 65nm node. With the details of the processor’scircuitry and the functional unit usage predicted bySimple-Scalar, PTScalar is able to predict how muchenergy each functional unit will dissipate each cycle.

• We also take the expressions for leakage power fromPTScalar, though we construct our own leakage powercalculator in order to maintain tool versatility. To ac-curately model cache leakage power, we use CACTI5.0 [19], which has accurate cache leakage values atcurrent and coming technology nodes. CACTI is anindustry trusted cache access time and power calculator.CACTI uses simulated data from SPICE models for thefuture technology nodes to construct its model. Thus, webelieve its values will be more accurate at later nodes.

• We utilize HotSpot (version 4.0) [17] as our temperaturesimulator. HotSpot uses the duality between RC circuitsand thermal systems to model heat transfer in silicon.Given power values over time, a floorplan, and thedetails of a chip’s package, HotSpot uses a Runge-Kutta (4th order) numerical approximation to solvethe differential equations that govern the thermal RC

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circuit’s operation.• We use the Alpha EV6 processor as our baseline core

[10]. The EV6 is a out-of-order speculative executioncore that is commonly used as a test-bench core inthermal management research [12], [18]. Each Alphacore has its own L1 data cache and L1 instruction cache,and all of the cores on the chip share a single L2 cache.

• As workloads, we use 8 benchmarks from theSPEC2000 suite [7]. We use 4 integer benchmarks: gcc,bzip, mcf, and twolf, and 4 floating point benchmarks:ammp, equake, lucas, and mesa

B. Setup of Processor Configurations

We examine 7 different technology settings using theAlpha EV6 processor as our baseline core. Namely, 130nm(1 core), 90nm, (2 cores), 65nm (4 cores), 45nm (8 cores),32nm (16 cores), and 22nm with ITRS-predicted low cachepower (32 cores). Each technology generation halves thearea of a given circuit, and doubles the number of transistorsin the cache. Thus, transitioning from one technology nodeto the next, doubles the number of cores, and doubles thememory capacity of the cache. Changes in supply voltages,threshold voltages, oxide thickness, and other parameterscause changes in power values with technology. In order tomodel these changes in power, we turn to the InternationalTechnology Roadmap for Semiconductors [9]. This workprovides a framework for the industry to follow as scalingproceeds into the deep sub-micron regime. Assuming theITRS trends are accurate, we use them to formulate TableI. The ITRS report provides us with the expected supplyvoltage, expected leakage current per micrometer of gatewidth, and expected gate capacitance at past, current, andfuture technology nodes. Since our power model is nativeto the 65nm node, we must scale these values, accordingto the ITRS, for the changes at other nodes. Table 1 is asummary of the results from the ITRS scaling trends.

C. Results of Frequency and Voltage Planning

Given the simulation tool chain and a processor configu-ration, we run on each core one of the following workloads(gcc, bzip, mcf, twolf, ammp, equake, lucas, and mesa)to create a mix of workloads that multi-core processorstypically encounter. For each workload configuration, thesystem parameters have to be learned using Equation 6. Thento find the optimal frequency and voltage plans, we solve

Technology Node Bulk silicon FD SOI(nm) 130nm 90nm 65nm 45nm 32nm 22nm

Number of Cores 1 2 4 8 16 32Supply VDD 1.3 1.2 1.1 1.0 0.9 0.8

Leakage / µm width 0.01 0.05 0.20 0.22 0.29 0.37Cap. / µm width 1.2e-15 9.9e-16 6.9e-16 7.4e-16 6.2e-16 5.3e-16

TABLE ISUMMARY OF POWER SCALING RESULTS. ALL OTHER VALUES ARE

COMPUTED BY SCALING ACCORDING TO ITRS PREDICTIONS.

Fig. 5. Optimal frequency plan for 16 cores arranged in a 4× 4 grid.

the linear programming formulation (given by Equations 7and 8) to maximize system performance under the constraintthat the junction temperature is ≤ 85 °C. We present twodifferent solutions to the problem: a standard solution, andan optimal solution. The standard solution has an addedconstraint equating the frequencies of all cores. This is thestandard frequency plan in use in most chips today. Dueto various spatial dependencies, i.e., adjacency of cores tovarious chip features as well as local variations in workload,optimal planning results in a different solution from standardplanning. To quantify such difference, we solve the linearprogramming problem defined by the constraints (7), withthe objective function (8), where all threads running onthe cores have equal weight, i.e., wi = 1. This indicatesthat each core is running a thread of equal importance. Weuse the MATLAB optimization package’s linear programsolver to ascertain the optimal solution. Most optimizationstook approximately 0.01 seconds on a 2.93GHz Intel DualCore Extreme workstation with 2GB RAM. This assures thatour plans are computable at runtime in a dynamic thermalmanagement setting. The results for the various technologynodes are tabulated in Table II, where we report the systemthroughput (as measured by the sum of all frequencies overall cores) for the standard throughput case and the theoptimized case.

The results given in Table II demonstrate that there isa significant throughput improvement for the optimal fre-quency plan (rows 4 and 5) over the standard plan (row 3).In addition, the improvement (row 5) increases with each newtechnology generation. Moreover, the performance improve-ment with coming generations does not just show increasesin absolute performance, but in percentage improvement aswell. In other words, our methods will become more effectiveat future technology nodes. With many cores on the chip,the thermal advantages/disadvantages of spatial core layoutbecome more evident and can be exploited more easily byour methods.

In Figure 5 we plot the frequencies of the optimal fre-quency plan as a function of the core location. In this figure,we can clearly see that some cores have had their frequenciesincreased at the expense of other cores such that the totalsystem performance is maximized. Figure 5 shows one of themost important conclusions of our work. Cores surrounded

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row 1 Technology 130nm 90nm 65nm 45nm 32nm 22nmrow 2 Number of cores 1 2 4 8 16 32row 3 Standard Throughput 2.6 5.5 11.9 19.0 38.1 71.4row 4 Frequency planning Throughput 2.6 5.5 12.1 19.9 41.6 80.8row 5 Improvement (%) 0% 0.5% 1.7% 4.5% 8.5% 11.2%row 6 Frequency + Voltage planning Throughput 2.6 5.7 12.9 21.5 47.4 107.7row 7 Improvement (%) 0% 1.1% 7.6% 11.7% 19.7% 33.4%

TABLE IIMIXED WORKLOAD THROUGHPUT FOR STANDARD, FREQUENCY OPTIMAL, AND VOLTAGE INCORPORATED HEURISTIC PLANS.

Fig. 6. Total and average thread throughput as a function of the numberof active cores in a 16 core system.

by other cores should be run at slower frequencies, whilecores near the comparatively cold cache or adjacent to thechip edge should be run at higher frequencies. The coldercaches and chip edges represent thermal reservoirs whereheat can more quickly and easily be transferred. Thus, outercores can dissipate heat more effectively and should berun faster. Interior cores, surrounded by comparatively hotadditional cores have less efficiency at dissipating their heatlaterally, and can count only on a heat transfer path throughthe package for heat removal. If an interior core is colderthan its surrounding cores, heat will also flow into the interiorcore from its neighboring cores, only worsening its thermaldisadvantage. Thus, Figure 5 confirms that outer cores aremuch better candidates for frequency increases, and interiorcores should be run at slower frequencies. Also, cornercores have two free sides, and thus can be run even faster.Different floorplans may have other thermal advantages anddisadvantages associated with core adjacency and location.However, our method is not specific to our floorplans. Rather,the model could be used with any core arrangement toproduce the optimal frequency plan.

To validate our solutions, we input both the optimal andstandard frequency plans that are computed from the linearprogram into the tool-chain (Figure 4) and examine thetemperature at the outputs. Across all technology settings,the mean absolute error was 1.2°C (if our model is100% accurate then we expect a maximum temperature of85°C resulting in an error of 0°C). Though our model isnot 100% accurate, 1.2°C is more than accurate enoughfor run-time use. Thus, we have confirmed that applyingthe optimal frequency plans to the chip closely meets thesteady-state maximum temperature constraint.

Impact of Voltage Planning. As described in SubsectionIII-B, planning both the frequency and the voltage can bring

Fig. 7. The impact of increasing the weight of high-priority threads ontheir runtime.

further improvements in performance at no impact to themaximum temperature constraints. Our starting point in thisexperiment is the optimal frequency plans that we havecalculated and have led to the results summarized in row4 of Table II. These frequency plans were calculated onthe assumption that all the cores operate at the maximumvoltage, where the maximum varies depending on thetechnology generation as outlined in Table I. It is apparentfrom the distribution of the optimal frequency plan in Figure5 that optimal planning leads to decreases in frequencyfor some cores. Thus, the voltage of these cores can bedecreased, which would decrease power consumption.Since voltage has been scaled on these throttled cores, wecan increase their frequencies to return the cores’ powerconsumption to their levels from the earlier frequency plan.We can see from rows 6 and 7 of II that there are largeperformance gains associated with the incorporations ofvoltage scaling with frequency. The voltage planning resultslead to further increases in performance peaking at 33.4%at the 22nm node. These results are not necessarily optimal,but provide a lower bound for the potential performancegains made possible by frequency and voltage planning asopposed to frequency planning alone.

Results of Dynamic Planning. Consider a 16 core systemwith less than optimal TLP. Figure 6 shows average activecore frequency and total chip-wide throughput with thenumber of active cores. As the number of active coresdecreases from 16, re-solving the linear program gives highercore frequencies for the active cores. Thus, as the numberof active cores decreases to as low as 11, the increases inaverage active core frequency actually permit a negligibleperformance degradation. In other words, the active corescan be boosted such that total chip-wide performance isnear constant. As TLP further decreases, constant chip-wideperformance cannot be maintained, but re-solving the linear

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program does provide large performance gains over simplydisabling cores in the 16 core optimal plan. Therefore, re-solving the linear program in a dynamic setting with lessthan ideal TLP is highly valuable for maximizing chip-widethroughput.

It is also prudent to examine the success of our methods insituations where all cores are in use, but where the threadsbeing run on certain cores are of varying importance. Toillustrate the possible advantages of our system, we proposea simple case study. Suppose a 16 core system is running 16separate threads, 2 of which are of critical importance to theuser. The other 14 cores run tasks of low importance, that donot directly interact with the user. We begin with the optimalfrequency plan of the 16 cores configuration. We assumethe operating system would have already assigned the highpriority threads to the two fastest cores. We subsequentlyexamine the time it would take to complete the two highpriority tasks as we vary their weight constants. The otherlow priority tasks will have weight constants equal to unity.As Figure 7 shows, the speed of the high-priority corescan be increased, at the expense of the speed of the low-priority cores. However, since the high-priority tasks weredirectly visible to the user, quickly completing these taskscan greatly increase the observed performance of a machine.The background tasks are not as time sensitive, and thus canbe sacrificed for the high-priority threads.

V. CONCLUSIONS

In this paper we proposed novel techniques to maximizethe performance of multi-core processors under thermalconstraints. Using machine learning techniques, we haveproposed a simple model that can mathematically describethe thermal characterization of multi-core processors giventheir input operating parameters. Given the measurements ofon-chip thermal sensors, this model allows us to calculatea core’s maximum temperature to a reasonable degree ofaccuracy. Our model lends itself naturally into a linearprogramming optimization formulation. We have examinedseveral different situations where the linear program pro-vides optimal frequency and voltage plans that give superiorphysical performance when compared to standard choices.Moreover, the optimization environment we have developedis versatile. If two cores are running threads that need tobe computed at the same time, those cores’ frequencies canbe equated with an additional constraint in the program.If the chip design does not include individual voltage andfrequency controls for each core, but rather for clusters ofcores, it is a simple matter to equate each cluster’s frequencyas a constraint in the program. Our frequency and voltageplans can be well-integrated in an existing DTM scheme. ADTM scheme can further adjust the frequency and voltageof each core during runtime to account for any unmodeledthermal variations.

There are limits on the amount of thread-level parallelisma workload can have. As a result, situations may arisewhere all of the cores in a multi-core system are not inuse. We have shown that using our methods can help to

increase the performance of a system with stalled cores. Ourmethod increases the active cores’ frequencies just enoughto assure the specified steady-state temperature constraintis not violated. Our method takes into account the spatiallocality of stalled cores as well as the existing thermaladvantage/disadvantages of each core, and recomputes anoptimal frequency plan. This technique has a great dealof value at the current technology node, where multi-corearchitectures are running workloads not necessarily designedfor thread-level parallelism.

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