_freesclaemotorcontrol

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.

Getting Started with Digital Signal Controllers (DSCs) for Motor Control and Energy Conversion

June, 2010

Pavel Grasblum, Ph.D.Application Engineer

FTF-IND-F0580


Agenda

►DSC Introduction• Roadmap Update• DSCs Overview

►DSC Core Introduction►Key peripherals for Motor Control and Energy Conversion Applications

• Detail Description• Differences among DSC Families

►Peripherals Utilization Guidelines• ADC to PWM Synchronization• Low Cost Current Measurement• BLDC Motor Commutation

►MC and SMPS Demos presented at FTF in Orlando

2


What is a Digital Signal Controller?

► Instructions optimized for controller code, DSP, matrix operations ► Compact assembly and “C” compiled code size► Easy to program► Additional MIPS headroom and extended addressing space

3

• Designed for controller code• Compact code size• Easy to program• Inefficient signal processing

• Designed for DSP processing • Designed for matrix operations• Complex programming• Less suitable for control


When is a Digital Signal Controller a Good Fit?

► When the application is dominated by high-speed capture and analysis of analog input and feedback (e.g. PWM adjustment) to a closed loop system

• DSC is similar to an MCU but with the performance to run complex algorithms for more responsive control and often, system cost reduction

• DSC provides flexibility to be used in multiple systems or to adapt within a system to environmental changes (compared to fixed analog-based control)

► Key features• Sufficient MIPs (32-60 MIPS) MCU/DSP performance for advanced algorithms• High speed/performance 600ns/12 bit ADC for fast dynamic response• High speed sophisticated (60 MHz- 96 Mhz) PWMs and timer modules to effectively

increase PWM resolution • Quadrature decoders for direct interface to Hall effect sensors or optical encoders • Safety features (fault inputs, loss of clock…) to prevent catastrophic failures

► Key applications• Motor control• Digital power conversion• Advanced lighting control

4


DSC Roadmap

5

MC56F802x32MHz, HR PWM,

ADC, DAC


ADC, DAC

MC56F801x32MHz,

HR PWM, ADC

MC56F801x32MHz,

HR PWM, ADC

Flash Size

Production - Available NOW

Execution - Specification Frozen, in design

Proposal - Specification Subject to Change

32-bit Core, 100MHz, DMA, FAST ADC &

PWM


PWM

<16k

B<3

2kB

<144

kB

56F800xV. Low Cost,

HR PWM

56F800xV. Low Cost,

HR PWM

<64k

B MC56F803x32MHz, HR PWM, CAN, ADC, DAC

MC56F803x32MHz, HR PWM, CAN, ADC, DAC

MC56F824x/5x60MHz,

Accurate PWMFAST ADC

MC56F824x/5x60MHz,


<280

kB

32-bit Core100 MHz, DMAFAST ADC &

PWM


PWM

40MHzUltra Low Cost

40MHzUltra Low Cost


PWM


PWM


PWM


PWM

<560

kB

MC56F832x60MHz

MC56F832x60MHz

MC56F833x60MHz

MC56F833x60MHz

MC56F835x60MHz

MC56F835x60MHz

MC56F836x60MHz

MC56F836x60MHz

MC56F834x60MHz

MC56F834x60MHz

MC56F812x40MHz

MC56F812x40MHz

MC56F814x40MHz

MC56F814x40MHz

MC56F815x40MHz

MC56F815x40MHz

MC56F816x40MHz

MC56F816x40MHz

Low Power Low Cost

Large CapacityMid Range

High Performance

2009

2010

Pin Compatible

40MHzUltra Low Cost

40MHzUltra Low Cost

60MHz, Accurate PWM

FAST ADC

60MHz, Accurate PWM

FAST ADC

Pin Compatible


Cost-Effective 56F8000 Solutions (56F801x)

► 32 MIPS performance ► 12K -16 K Bytes program FLASH ► 4 K Bytes program/data RAM ► Tunable internal relaxation oscillator► Software programmable phase locked loop► Up to 96 MHz peripherals – timers and PWMs► Up to 6-output PWM module with up to 4

programmable fault inputs► Two 12-bit ADCs with up to 8 inputs, 1.125us

conversion rate► Synchronization between PWM and ADC► Four 16-bit general purpose programmable timers► Computer operating properly timer► Serial ports: SCI, SPI, I2C► Up to 26 GPIOs – Versatile pin usage► Low power consumption – 59 mA max. and

.026 mA min.► JTAG/EOnCE™ debug port► Industrial and automotive temperature range► Cost effective

6

Package: 32LQFPIn Production

56800E Core32MHz

Power-On-Reset

Power Supervisor

COP

12K - 16KB Program Flash

6-ch PWM Output

System Integration Module (SIM) 1 x SCI

1 x SPI1x IIC

JTAG/EOnCE

4kB Program/Data RAM

Voltage Regulator

PLL

Interrupt Controller

Relaxation OSC 3-4ch 12bit ADC3-4ch 12bit ADC

56F8011/56F8013/56F8014Up to 26 GPIOs

4Ch 16bit Timer

Synch


56F8000 Family Expansion (56F802x/56F803x)

► 32 MHz/32 MIPS 56800E core► 3.0-3.6V operation► 32K-64 K Bytes program FLASH► 4K-8 K Bytes program/data RAM ► Flash security► Tunable internal relaxation oscillator► Software programmable phase locked loop► Up to 96 MHz peripherals – timers and PWMs► 6 output PWM module with 4 programmable fault

inputs with selectable PWM frequency for each PWM signal complementary pair

► Two 12-bit ADCs with up to 16 inputs , 1.125us conversion rate

► Up to two 12-bit digital to analog converters► Two analog comparators► Synchronization between PWM and ADC► 4 or 8 16-bit general purpose programmable timers► 1 or 3 programmable interval timers (PIT)► Computer operating properly timer► 2-queued serial communications interface ► 2-queued serial peripheral interface► Optional MSCAN► I2C communications interface► Up to 53 GPIOs – Versatile pin usage► JTAG/EOnCE™ debug port► Industrial and automotive temperature range

7

Package 32 LQFP, 44LQFP, 48LQFP, 64LQFPIn Production

56800E Core32MHz

Power-On-Reset

Power Supervisor

COP

32KB - 64KB Program Flash

6-ch PWM Output

System Integration Module (SIM) 2 x QSCI

2 x QSPI1xIIC

JTAG/EOnCE

4kB-8KB Program/Data RAM

Voltage Regulator

PLL


Relaxation OSC

8ch 12bit ADC8ch 12bit ADC

56F8023/56F8025/56F8036/56F8037Up to 53 GPIOs

8Ch 16bit Timer

Synch

1x MSCAN

Crystal OSC

2 x Comparators2 x 12 bit DAC

3xPIT


Ultra Low Cost: 56F800x

► 32 MHz/32 MIPS 56800E core► 1.8-3.6V operation► 12K - 16K Bytes program FLASH with Flash security► 2K Bytes program/data RAM ► Tunable internal relaxation oscillator and 32 KHz clock► Phase locked loop (PLL)► Up to 96 MHz peripherals – timers, PWM & Hi-SCI► 6 output PWM module with 4 programmable fault inputs

with selectable PWM frequency for each PWM signal complementary pair

► Two programmable gain amplifiers with x2, x4, x8, x16 gains (clocked in order to cancel input offset)

► Two 12-bit ADCs with up to 24 inputs , 2.5us per conversion

► Programmable delay block provides precise control of ADC/PGA sample times relative to PWM reload cycles

► Three high speed analog comparators► 2 multiple function programmable timers► Computer operating properly timer► One periodic interval timer (PIT)► 1 high speed serial communication interface (Hi-SCI)► 1 serial peripheral interface (SPI)► I2C communications interface► Up to 40 GPIOs – versatile pin usage► JTAG/EOnCE™ debug port► Industrial temperature range: -40C – 105C

8

56800E Core

32MHzPower-On-Reset

Power Supervisor

COP

12-16KB Program

Flash

6-ch PWM Output

System Integration Module (SIM) 1 SCI

1 SPI1 IIC

JTAG/EOnCE

2KB Program/Data RAM

Voltage Regulator

PLL


Relaxation OSC

2 x ProgrammableGain Amplifiers

56F8002, 56F8006Up to 40 GPIOs

ProgrammableDelay Block

Synch

2 x 16bit Timers

Crystal OSC3 x Analog

Comparators

1 Period Int Timer

12ch 12bit ADC12ch 12bit ADC

Package: 28SOIC, 32SDIP , 32LQFP, 48 LQFPIn Production


56F8000 Series Feature Summary 56F8002 56F8006 56F8011 56F8013 56F8014 56F8023 56F8025 56F8036 56F8027/37

Performance 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs 32MHz/MIPs

Temperature Range (V) -40C~105C -40C~105C -40C~125C -40C~125C -40C~125C -40C~105C -40C~105C -40C~105C -40C~105C

Voltage Range 1.8V - 3.6V 1.8V - 3.6V 3.0V - 3.6V 3.0V - 3.6V 3.0V - 3.6V 3.0V - 3.6V 3.0V - 3.6V 3.0V - 3.6V 3.0V - 3.6V

Voltage Regulator On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip On-Chip

Program/Data Flash 12KB 16KB 12KB 16KB 16KB 32KB 32KB 64KB 32KB / 64KB

Program/Data RAM 2KB 2KB 2KB 4KB 4KB 4KB 4KB 8KB 4KB /8KB

Program Security Yes Yes Yes Yes Yes Yes Yes Yes Yes

On Chip Relaxation Osc. Yes Yes Yes Yes Yes Yes Yes Yes Yes

PLL Yes Yes Yes Yes Yes Yes Yes Yes Yes

COP (Watchdog) Yes Yes Yes Yes Yes Yes Yes Yes Yes

PWM (96 Mhz Clock) 1 x 6ch 1 x 6ch 1 x 6ch 1 x 6ch 1 x 5ch 1 x 6ch 1 x 6ch 1 x 6ch 1 x 6ch

PWM Fault Inputs 4 4 4 4 3 4 4 4 4

12-bit ADCs 2 x 8ch 2 x 12ch 2 x 3ch 2 x 3ch 2 x 4ch 2 x 3ch 2 x 4ch 2 x 5ch 2 x 8ch

12-bit DACs 0 0 No No No 2 2 2 2 (Pinned out)

Analog Comparator 3 3 No No No 2 2 2 2

Prog Gain Amp 2 2 No No No No No No No

16-bit Timers 3 3 4 4 4 4 4 4 8

Prog. Interval Timers 1 (RTC) 1 (RTC) No No No 1 3 3 3

GPIO (max) (+/-8mA) 23 40 26* 26* 26* 26* 35* 39* 53*

IIC 1 1 1 1 1 1 - QIIC 1 - QIIC 1 - QIIC 1 - QIIC

SCI (UART) / LIN Slave 1 - SCI 1 - SCI 1 - SCI 1 - SCI 1 - SCI 1 - QSCI 1 - QSCI 1 - QSCI 1 - QSCI

SPI (Synchronous) 1 - SPI 1 - SPI 1 - SPI 1 - SPI 1 - SPI 1 - QSPI 1 - QSPI 1 - QSPI 1 - QSPI

CAN No No No No No No No MSCAN MSCAN

JTAG/EOnCE Yes Yes Yes Yes Yes Yes Yes Yes Yes

Power Consumption IDD = 45.6mA;IDDA = 4.5mA IDD = 42mA; IDDA = 13.5mA IDD = 48mA; IDDA = 18.8mA IDD = 48mA; IDDA = 18.8mA

Package 32LQFP (.8p)

28SOIC32LQFP32SDIP48LQFP

32LQFP 32LQFP 32LQFP 32LQFP 44LQFP 48LQFP 64LQFP


DSC Roadmap

10


ADC, DAC


ADC, DAC

MC56F801x32MHz,

HR PWM, ADC

MC56F801x32MHz,

HR PWM, ADC

Flash Size

Production - Available NOW

Execution - Specification Frozen, in design

Proposal - Specification Subject to Change


PWM


PWM

<16k

B<3

2kB

<144

kB

56F800xV. Low Cost,

HR PWM

56F800xV. Low Cost,

HR PWM

<64k

B



MC56F824x/5x60MHz,


MC56F824x/5x60MHz,


<280

kB


PWM


PWM

40MHzUltra Low Cost

40MHzUltra Low Cost


PWM


PWM


PWM


PWM

<560

kB

MC56F832x60MHz

MC56F832x60MHz

MC56F833x60MHz

MC56F833x60MHz

MC56F835x60MHz

MC56F835x60MHz

MC56F836x60MHz

MC56F836x60MHz

MC56F834x60MHz

MC56F834x60MHz

MC56F812x40MHz

MC56F812x40MHz

MC56F814x40MHz

MC56F814x40MHz

MC56F815x40MHz

MC56F815x40MHz

MC56F816x40MHz

MC56F816x40MHz

Low Power Low Cost

Large CapacityMid Range

High Performance

2009

2010

Pin Compatible

40MHzUltra Low Cost

40MHzUltra Low Cost

60MHz, Accurate PWM

FAST ADC

60MHz, Accurate PWM

FAST ADC

Pin Compatible


MC56F824x/MC56F825x Features

► 60 MHz/60 MIPS from 56800E core► 2.7-3.6V operation► 64K Bytes program FLASH► 8K Bytes program/data RAM► Flash security► 8Mhz/100Khz tunable internal relaxation oscillator► Software programmable phase locked loop► Up to 60 MHz peripherals – timers and PWMs

• 8 output PWM module• 520ps PWM and PFM resolution

► 2-12-bit ADCs with total 16 inputs• 600ns conversion rate • built-in PGA with 1x, 2x, 4x, gains

► 1 12-bit digital to analog converter► 3 5-bit digital to analog converters► 3 analog comparators ► 8 16-bit enhanced GP multifunction

programmable timers► Cyclic redundancy check generator (CRC)► Computer operating properly timer► 2 high speed serial communications interface (SCI) ► 1 queued serial peripheral interface (QSPI)► 1 MS-CAN bus► 2 I2C/SMbus communications interface► Up to 54 GPIOs► Inter module cross-bar► JTAG/EOnCE™ debug port► Industrial temperature range: -40°C to 105°C with

60 Mhz

44LQFP, 48LQFP 64 LQFP, Samples Available

11

56800E Core60 Mhz

POR

LVI

COP

8ch 12-bit ADCA

1ch 12-bit DAC

64KB Program Flash

8-ch High Res PWM

2 x High Speed QSCIs

1 x QSPI

2x IIC/SMbus

JTAG/EOnCE

8kB Data RAM

1 x MSCAN

Voltage Regulator

PLL

Crystal Oscillator

System Integration Module (SIM)


3 Analog Comparators

Prog Gain Amp Ax1,2,4

8Ch 16-bit Timer

Relaxation OSC

8ch 12-bit ADCB Prog Gain Amp Bx1,2,4

CRC

3 5-bit DAC

Inter-module Cross Bar

►Breakthrough Features:• New generation high speed PWM module

520 ps duty cycle and frequency resolutionFlexible edge placement

• High speed ADC with programmable gain amplifiers600ns conversion rateSupports multi trigger source in one ADC scan

• Inter-module cross bar Programmable inter module connection


DSP56800E Core Architecture

► Instruction Fetch:PAB - 21 bitsPDB - 16 bits

► 1st Data Access:XAB1 - 24 bitsCDBR - 32 bits CDBW - 32 bits

► 2nd Data Access:XAB2 - 24 bitsXDB2 - 16 bits

► Operations Performed:1st - PAB / PDB2nd - XAB1 /

DBR-CDBW

3rd - XAB2 / XDB2

12

DATAALU

A1B1C1D1

Y0Y1X0

A0B0C0D0

A2B2C2D2

MAC and ALU

Multi-bitShifter

R 0R 1R 2R 3R 4R 5N

S P

R 0R 1R 2R 3R 4R 5N

S P

AGU ALU1 ALU2

ALU1 ALU2

M 01

BITMANIPULATION

UNIT

EOnCE/JTAG TAP

XAB1XAB1

XAB2XAB2PABPAB

PDBPDBCDBWCDBWCDBRCDBRXDB2XDB2

ProgramMemory

DataMemory

IP-BusInterface

ExternalBus

Interface

N 3

PROGRAMCONTROLLER

INSTRUCTIONDECODER

LOOPINGUNIT

INTERRUPTUNIT

PCLA

LA2

HWSFIRAFISR

LCLC2

SROMR


Mapping the Architecture to DSP Algorithms

13

Source 2 Destination 2

PRIMARY READ(Uses XAB1 and CGDB)

SECONDARY READ(Uses XAB2 and XDB2)

OPCODE AND OPERANDS

MACR X0,Y0,A X:(R0)+N,Y0 X:(R3)-,X0

Parallel Move

Source 1 Destination 1

y n( ) = c i( )i= 0

N −1

∑ x n − i( ) ; Typical Digital Filter Formula


Mapping the Architecture to DSP Algorithms

14

DATAALU

Y0Y1X0

MAC and ALU

Multi-bitShifter

R 0R 1R 2R 3R 4R 5N

S P

R 0R 1R 2R 3R 4R 5N

S P

AGU ALU1 ALU2ALU1 ALU2

M 01

BITMANIPULATION

UNIT

EOnCE / JTAG TAP

XAB1XAB1XAB2XAB2PABPAB

PDBPDBCDBWCDBWCDBRCDBRXDB2XDB2

ProgramMemory

DataMemory

IP-BusInterface

ExternalBus

Interface

N 3

Operations Performed:• Multiply-Accumulate• 3 Memory Accesses• 2 Address Additions

PROGRAMCONTROLLER

INSTRUCTIONDECODER

LOOPINGUNIT

INTERRUPTUNIT

PCLA

LA2

HWSFIRAFISR

SR

LCLC2

OMR

2nd Data Access:XAB2 - 24 bitsXDB2 - 16 bits

1st Data Access:XAB1 - 24 bitsCDBR - 32 bits

Instruction Fetch:PAB - 21 bitsPDB - 16 bits

A1B1C1D1

A0B0C0D0

A2B2C2D2


Pulse Width Modulation Modules

15


Pulse Width Modulator (PWM) – MC56F800x, MC56F80xx

► Clock PWM up to 96Mhz► Three complementary signal pairs or six independent

signals or combinations► Complementary channel operation

• Separate deadtime insertions for rising and falling edge• Separate top and bottom polarity control

► Edge-aligned or center-aligned signals► 15-bits of resolution► Half-cycle reload capability► Asymmetric mode of operation (for phase shifting)► Programmable integral reload rates (half to 16)► Individually software-controlled PWM outputs► ADC synchronization► Up to 4 programmable fault inputs► PWM compare output polarity control► 8 or 4 mA current source/sink► Output polarity control► Write protected registers► Double-buffered PWM registers► Wait/debug mode operation► Selectable PWM supply source for each

complementary PWM signal pair (F8000 family only)• PWM generator• External GPIO• Internal timer channel• ADC conversion result, taking into account values setting ADC

high and low limit register

16


Enhanced Flex Pulse Width Modulator (eFlexPWM) – 56F824x/5x

17

► Four independent sub-modules with own time base, two PWM outputs + 1 auxiliary PWM input/output

► 16 bits resolution for center, edge aligned, and asymmetrical PWMs

► Fractional delay for enhanced resolution of the PWM period and edge placement

► Complementary pairs or independent operation► Independent control of both edges for each PWM output► Synchronization to external hardware or other PWM sub-

modules ► Double buffered PWM registers► Integral reload rates from 1 to 16 include half cycle reload► Half cycle reload capability► Multiple output trigger events per PWM cycle► Support for double switching PWM outputs► Fault inputs can be assigned to control multiple PWM outputs► Programmable filters for fault inputs► Independently programmable PWM output polarity► Independent top and bottom deadtime insertion► Individual software control for each PWM output► Software control, and swap features via FORCE_OUT event► Compare/capture functions for unused PWM channels► Enhanced dual edge capture functionality


eFlexPWM - Sub-Module Detail

18


eFlexPWM – PWM Generation

19


eFlexPWM – Edge Aligned PWM Generation

20

VAL1 ($0100)

INIT ($FF00)

VAL2, VAL4 = $FF00

VAL5

($0000)VAL3

► All PWM-on values are set to the init value, and never changed again. Positive PWM-off values generate pulse widths above 50% duty cycle . Negative PWM-off values generate pulse widths below 50% duty cycle . This works well for bipolar waveform generation.

CH0b

CH0a


eFlexPWM – Center Aligned PWM Generation

21

VAL1 ($0100)

INIT ($FF00)VAL2

VAL3

($0000)VAL4

VAL5

Ch0a

Ch0b

► When the Init value is the signed negative of the Modulus value, the PWM module works in signed mode. Center-aligned operation is achieved when the turn-on and turn-off values are the same number, but just different signs.


eFlexPWM – Shifted PWM Generation

22

VAL1 ($0100)

INIT ($FF00)VAL2

VAL3($0000)

VAL4

VAL5

CH0a

CH0b

► In this example, both PWMs have the same duty-cycle. However, the edges are shifted relative to each other by simply biasing the compare values of one waveform relative to the other.

► Alternatively, if the waveforms are generated by different sub-modules, the waveforms can be shifted by simply changing the Init value of one sub-module relative to the other.


eFlexPWM – Force Output Logic

23


eFlexPWM – Complementary and Deadtime Logic

24


eFlexPWM – Fractional Delay and Output Logic

25


eFlexPWM – High Resolution Duty Cycle Generation

►PWM resolution is given by input clock of PWM module ►Example:

• Let’s generate PWM signal with MODULO=4, DUTY_CYCLE=2 (50 %)

26

tclk

0000

0011

tPWM



►PWM resolution is given by input clock of PWM module

►The PWM resolution can be enhanced by analog delay circuit, which can place edge between two edges, derived from input clock

►Example:• Consider 2-bit analog delay block• Let’s generate PWM signal with MODULO=4:0, DUTY_CYCLE=2:3 (68.75 %)

27

tclk

0000:00

0011:00

tPWM



►At high resolution duty cycle generation• The leading edge is usually aligned with digital clock• The falling edge is generated by delay block• The analog delay is constant every PWM period

28

tclk

0000:00

0011:000010:11

ttimer

tPWM

0000:000010:110010:11 0010:11

PWM output using delay blockDUTY_CYCLE = 0010:11

PWM output w/t delay blockDUTY_CYCLE = 0010

Timer clock

0000:00 0000:00


eFlexPWM – High Resolution Frequency Generation

►Example:• Consider 2-bit analog delay block• Let’s generate PWM signal with MODULO=4:2, DUTY_CYCLE=2:1 (50 %)

29

tclk

0000

0011

tPWM



►Example:• Consider 2-bit analog delay block• Let’s generate PWM signal with MODULO=4:2, DUTY_CYCLE=2:1 (50 %)

30

tclk

0000:00

0011:00

tPWM



►At high resolution frequency generation• Both edges are generated by delay block• The analog delay is changing edge by edge every PWM period• The analog delay must be calculated every edge or requires some hardware

support

31

tclk

0000:00

0001:00

0010:00

0000:10

0011:000010:01

ttimer

tPWM

0000:00 0010:110010:01 0000:00 + 1clk 0010:01

PWM output using delay blockperiod = 0100:10

PWM output w/t delay blockperiod = 0100 Timer clock

0000:10


eFlexPWM – HR Frequency Generation HW Support

► Need to calculate the next edge position for rising and falling edges within very short period

► Software not fast enough, so need hardware adder

► Diagram shows 21 bit adder to control both edges automatically setting new comparator values after each edge has been triggered

32

16 bitsat IP Bus

timingresolution

5 bitsNanoEdge

timingresolution

16 bit + 5 bit adder

Ideal timing

16 bitsat IP Bus

timingresolution

5 bitsNanoEdge

timingresolution

16 bitsat IP Bus

timingresolution

5 bitsNanoEdge

timingresolution

Actual timing Timer

5 bits from previous NEP calculation

PWM Period N-1PWM

Period NPWM

Period N

• PWM reload times are restricted to 16-bit IP bus timing (truncation of 21 bit value). Any residual left over from PWM period N-1 needs to be added back to period N.


eFlexPWM – HR Frequency Generation from User Perspective

►The new edge calculation is seem less from user perspective

►The user sets required 21-bit (16+5 bit) values into corresponding value registers only

►The 5-bit delay block corresponds to 1.92 GHz input clock (for 60MHz PWM module input clock)

33

16-bit digital value

16-bit digital value 5-bit nano-edge value

PWM Value Register

PWM Value Register PWM Fractional Value Register

NanoEdgeTM placement not used. 16-bit value only.

NanoEdgeTM placement enabled. 21-bit (32-bit) value.


eFlexPWM – HR Frequency Generation from User Perspective

►Example of high resolution calculation• For high frequency the digital value is usually less than 11 bits. For example,

200 kHz edge-aligned PWM has resolution less than 9 bits• Therefore we can keep calculation in 16 bits• Result of calculation is moved right by 5 bits and written into 32-bit register

34


Internal User Representation

PWM Value Register PWM Fractional Value Register


NanoEdgeTM placement enabled. 21-bit (32-bit) value.


Analog to Digital Converters

35


A/D Converter – MC56F800x

36

► Two ADC modules allowing parallel conversion

► Input voltage range from VSSA to VDDA► Up to 28 analog inputs► Output in 12-, 10- or 8-bit

right-justified format► Single or continuous conversion (automatic

return to idle after single conversion)► 2.5 μs conversion time► Configurable sample time and conversion

speed/power► Conversion complete flag and interrupt► Input clock selectable from up to

four sources► Operation in wait or stop modes for lower

noise operation► Asynchronous clock source for lower noise

operation► Hardware and software triggering► Temperature sensors that are routed

to ANA26 and ANB26► Support up to four samples per conversion


Programmable Gain Amplifier (PGA) – MC56F800x

37

► Sampled PGA architecture► Common mode noise and offset cancelation► Synchronized with PWM operation► 0.14 MSPS maximum► Sampling time can be precisely controlled

(to less than 0.1 μs)► Programmable gains (1×, 2×, 4×, 8×, 16×,

and 32×)► Selectable tradeoff for slower/low power

versus faster/more power► Rail-to-rail input voltage range► Single-ended output routed directly to on-chip

ADCs ANA15 and ANB15► Software and hardware triggers are available► Includes additional calibration features:

• Offset calibration eliminates any errors in the internal reference used to generate the VDDA/2 output center point

• Gain calibration can be used to verify the gain of the overall datapath

• Both features require software correction of the ADC result



38

► 12-bit resolution► Maximum ADC clock frequency is 5.33 MHz► Sampling rate up to 1.6 million samples per second► Sequential: First 1.6μs subsequent 1.125μs► Simultaneous: 8 conversions in 4.97μs ► Internal or external Vref► ADC can be synchronized to a PWM via the

SYNC signal► High and low limits can control PWM outputs► Simultaneous or sequential sampling► Internal multiplexer to select two of eight inputs► Ability to sequentially scan and store up to eight

measurements► Ability to simultaneously sample and hold

two inputs► Optional interrupts at the end of a scan, if an

out-of-range limit is exceeded, (high or low) or at zero crossing

► Optional sample correction by subtracting a pre-programmed offset value

► Signed or unsigned result► Single-ended or differential inputs for all input pins

with support for an arbitrary mix of input types► Auto-standby mode to reduce power consumption► Power savings modes allow automatic

shutdown/startup of all or part of ADC



39


A/D Converter – MC56F802x/3x

►Differences from 56F801x devices:• 16 sample and result registers• First 8 samples support high/low limits, zero-crossing and offset features only

40


A/D Converter – MC56F824x/5x

► Differences from 56F802x/3x devices:• ADC input clock 10 MHz (conversion

time 850/600 ns)• Integrated PGA with gain 1x, 2x, 4x• Support multi-trigger operation

41

>

<

HIGHLIMIT

LOWLIMIT

Zero Crossing Logic

ADC OFFSET

ADCRESULT

IRQ

Log

ic

IRQ

RES

ULT

MU

X12BitADCM

UX

V+

V-

Vrefl

AN0AN1

ANx

Channel SelectSingle Ended or Differential

Below

Above

PGA

Gain SettingX1, x2, x4

…

16x

8x

8x

8x


Analog Comparators

42


Analog Comparator – MC56F802x/3x

43

INV

ProgrammableGlitch Filter

Export to CMP_B

ESEL [0,1] NSEL [0,2]

PSEL [0,2]

+

-CMP_A 0

1

PDN

MUX

MUX

MUX

Import From CMP_B

COUT

Rising EdgeInterrupt Request

To Timer A1

To PWM

To GPIO

To PWM Fault 1

Negative inputSource Select

ExportSource Select

Power Down

CIN_A0

CIN_A1

CIN_A2

DAC_AFalling EdgeInterrupt Request


Analog Comparator – MC56F802x/3x

► Up to two continuous-time differential-input analog comparator modules► Internal switching matrix supports the independent connection of the analog inputs► to the positive or negative input of the analog comparator and to the comparator’s

export output for another comparator module.► 5 selectable input sources:

• Three GPIO pins• One DAC output • One import input from another comparator module

► Programmable comparator output polarity► Comparator output edge indicator► Interrupt can be generated by comparator output rising edge, or falling edge,

or both edges► Comparator output can be fed to timer input, PWM faults input, PWM source,

external pin output► Software controlled power down mode

44


Analog Comparator – MC56F800x, MC56F824x/5x

45

► Two software selectable performance levels:• Shorter propagation delay at the expense

of higher power• Low power, with longer propagation delay

► Comparator output may be:• Sampled• Windowed (ideal for certain PWM

zero-crossing-detection applications)• Digitally filtered• Filter can be bypassed

► Operates over the entire supply range► Less than 40 mV of input offset► Less than 15 mV of hysteresis► Inputs may range from rail to rail► Selectable interrupt on rising edge, falling edge,

or both edges of comparator output► Selectable inversion on comparator output


Timers

46


Quad Timer – All DSCs

47

► Unique architecture with 2x Inputs (primary + secondary) and 1x output► Powerful MUX - primary input, secondary input and output can be connected to external pins► Individual channel capability - input capture trigger, output compare, clock source, prescaler► Counters are pre-loadable, count once or repeatedly► Master operation - any channel can be a master that broadcasts its compare signal to the other channels. This way

they can be configured to reinitialize their counters and/or force their OFLAG output signals to predetermined values.► Compare - The TMRCMP1/2 registers provide the compare values (up/down) for the counter. If a match occurs, the

OFLAG signal can be set, cleared, or toggled (polarity is selectable). If enabled, an interrupt is generated, and the new compare value is loaded into TMRCMP1 or 2 registers from TMRCMPLD1 and 2 (as enabled).

► Capture register stores a copy of the counter’s value when an input edge (positive, negative, or both) is detected. Once a capture event occurs, no further updating of the capture register will occur until the input edge flag is cleared.

Primary Input

Secondary Input

PRESCALER

MUX

CONTROL

COUNTER

TMRLOAD TMRHOLD CAPTURE TMRCMP1 TMRCMP2

CMPLD1 CMPLD2

COMPARATOR COMPARATOR

MUX OFLAG

OUTPUT

INPUTS

OTHER INPUTS

STATUS & CONTROL

DATA BUS

Quad-Timer Channel

Output

4x


Quad Timer Operating Modes

48

►Stop Mode: Counter is inert. No counting will occur ►Count Mode: Counts rising or falling edges(generating periodic interrupts, timing purposes)

►Edge Count Mode: Counts rising and falling edges(counting of simple encoder wheel)

►Gated Count Mode: Counts primary input if secondary input is high (signal width measurement)

►Signed Count Mode: Counts primary input up or down based on polarity of secondary input

►Cascaded Count Mode: Input is connected to the output of another (great for large counts up to 264)



49

►Triggered Count Mode: Start/Stop count of primary input on rising edge of secondary input.

►One-Shot Mode: Provides timing delays(ADC acquisition of new samples until a specified period of time has passed since the PWM sync signal occurred)



50

► Fixed Frequency PWM: Fixed frequency, variable duty cycle (driving PWM amplifiers)

► Variable Frequency PWM: Variable frequency and duty cycle (driving PWM amplifiers)

► Pulse Output Mode: Supports stepper motor systems and provides change of signal frequency and number of pulses

Primary

Count 0 1 2 3 4 0

Output

Count Mode Timer is Off Timer is in Count Mode

TimerStopped dueto Compare(COMP1 = 4)

► Quadrature Count Mode• Counter will decode the primary and secondary

external inputs as quadrature encoded signals• Compare interrupts will signal commutation


Others

51


Crossbar Switch - MC56F824x/5x

►Flexible signal interconnection among peripherals

►Connects any of 22 signals on left side to the output on right side (multiplexer)

►Total 30 multiplexers►All multiplexers share the same

set of 22 signals► Increase flexibility of peripheral

configuration according to user needs

52


Crossbar Inter-module Connection - MC56F824x/5x

53

HSCMP

5-bitVREF

X3

Quad Timer B

8-chGHzPWM

Dual12bit ADC

X6

4

4

Trigger[1:0]

CrossbarFabric

X9

6

14EXTA[3:0]EXT_SYNC[3:0]

EXT_FORCEEXT_CLKFAULT[3:0]

OUT_TRIG0[2,0]OUT_TRIG1[2,0]

12-BitDAC

Pin

Pin

ADC_In

12-bit DAC Output

12-bit DAC output

I/OMuxing

peripheralfunctions

X4

Pin

3

PWMA[3:0]PWMB[3:0]PWMX[3]

To comparators

SYNC_IN

DAC input for test only

3

Window / Sample[2:0]

Pin

PinX6

12-bit DAC output

0123

3021

TB[3:0]

ORFunctions

2 OUT_TRIG0[3]OUT_TRIG1[3]

4I/O Module

I/O Module


ADC to PWM Synchronization

54


Why Is ADC to PWM Synchronization Needed?

►ADC sampling helps to filter the measured current - antialiasing

55

PWM Period

PWM 0

Inductor CurrentAverage Current

A/D

calc.

Data Processing and New PWM Parameters Calculation

ADC trigger Signal

Sampled Current

AsynchronousSampling

SynchronizedSampling


Why Is ADC to PWM Synchronization Needed?

►Phase current can be sensed for certain time only

56

PWM Bt PWM CtPWM At

Phase A Phase B Phase C

DC Bus

Ground

Shuntresistor

n

+U/2

- U/2

PWM Bb PWM CbPWM Ab

3-ph AC Induction Motor3-ph PM Synchronous Motor

Shuntresistor

time to sensing

current

DeadTime

stabilized

sampling

PWM1 QAT

PWM2 Q AB

Isense_A

window


ADC to PWM Synchronization: MC56F80xx

►Smart combination of the PWM + QTimer + ADC allows precise control of the sample event

►The PWM synch output is connected to secondary input of QTimer - Ch3

►The QTimer Ch3 output is connected to ADC SYNC0

►The QTimer Ch2 output is connected to ADC SYNC1

►The ADC sample can be easily synchronized with PWM with no software overhead (constant delay). Note the delay also can be applied to the external trigger signal

►Cycle-by-cycle control of the QTimer addresses advanced ADC trigger delay control

57

MUX

ADCBADCA

ADC SYNC1

PWM SyncIP BusCLK

*0 1 2 3

ADC SYNC0 * can be used to mimicADC SYNC pulse during debugging

PWM


ADC to PWM Synchronization Details: MC56F80xx

58

PWM COUNTER

PWM SYNC

PWM GENERATOROUTPUTS 0, 1

PWM PINS 0, 1

POWER STAGEVOLTAGE

TMR3

t1

t2

COUNTER

TMR3 OUTPUT

ADC CONVERSION

ADC ISR

dead-time/2

dead-time dead-time

dead-time/2

► t1 - time between PWM SYNC signal and TMR3 output. TMR3 output starts ADC conversion immediately.

► t2 – ADC conversion time

► QTimer Ch3 settings:• Primary input: System clock• Secondary Input: 3-th input

(PWM synch)• Operation mode: Triggered

mode• Count length: Count until

compare and reinitialize• Output mode: Clear on

secondary, set on compare


ADC to PWM Synchronization: MC56F800x

59


Programmable Delay Block Operation Modes – MC56F800x

60

► Individual Operation• Each ADC is controlled individually

► ORed Operation• Both ADC converters operate in ping – pong

mode. Up to four samples can be taken per conversion sequence

► Pulsed (PWM) Operation• This mode can be used for window operation

of high speed comparator• The output can be connected to pin and

generated PWM signal


ADC to PWM Synchronization: MC56F800x (Individual mode)

61


ADC to PWM Synchronization: MC56F800x (ORed Mode)

62


ADC to PWM Synchronization: MC56F800x (ORed Mode)

63


ADC to PWM Synchronization: MC56F824x/5x

64

HSCMP

5-bitVREF

X3

Quad Timer B

8-chGHzPWM

Dual12-bit ADC

X6

4

4

Trigger[1:0]

CrossbarFabric

X9

6

14EXTA[3:0]EXT_SYNC[3:0]

EXT_FORCEEXT_CLKFAULT[3:0]

OUT_TRIG0[2,0]OUT_TRIG1[2,0]

12-BitDAC

Pin

Pin

ADC_In

12-bit DAC Output

12-bit DAC output

I/OMuxing

peripheralfunctions

X4

Pin

3

PWMA[3:0]PWMB[3:0]PWMX[3]

To comparators

SYNC_IN

DAC input for test only

3

Window / Sample[2:0]

Pin

PinX6

12-bit DAC output

0123

3021

TB[3:0]

ORFunctions

2 OUT_TRIG0[3]OUT_TRIG1[3]

4I/O Module

I/O Module


eFlexPWM – PWM Generation

65


ADC to PWM Synchronization Details: MC56F824x/5x

66

ORsubmodule 0

OR

OR

submodule 1

submodule 2

submodule 3

OR

8-ch eFlexPWM

OUT_TRIG0[0]

OUT_TRIG1[0]

OUT_TRIG0[1]

OUT_TRIG1[1]

OUT_TRIG0[2]

OUT_TRIG1[2]

OUT_TRIG0[3]

OUT_TRIG1[3]

crossbar input[16]

crossbar input[17]

crossbar input[18]

crossbar input[20]

crossbar input[21]

crossbarinput[19]

CrossbarFabric


Low Cost Current Measurement -Single Shunt Current Reconstruction

67


Single Shunt Current Reconstruction

68

PWM Bt PWM CtPWM At


DC Bus

Ground

Shuntresistor

n

+U/2

- U/2

PWM Bb PWM CbPWM Ab

3-ph AC Induction Motor3-ph PM Synchronous Motor

Shuntresistor


Single Shunt Current Reconstruction - Analysis

69

iDC=0

iDC=+ia

(100)

iDC=-ic

(110) (111)(000)

iDC=0

(110) (100)

iDC=-iciDC=+ia

progdelaydeadtimedelay ttt +=

Voltage Vector DC-Link current idc

V1(100) +iaV2(110) -icV3(010) +ibV4(011) -iaV5(001) +icV6(101) -ibV7(111) 0V0(000) 0

► Measurement Table

ABC


Single Shunt Current Reconstruction - Issues

►Two current samples cannot be taken:1. Voltage vector is crossing a sector border

• Only one sample can be taken2. Low modulation indexes

• Sampling intervals too short• None of current samples can be taken

70

Passing Active Vector Low Modulation Index


Single Shunt Current Reconstruction - Solution

►Asymmetrical PWMs• Case 1 – Passing active vector:

Freeze center edgeMove one critical edgeGoes for higher modulation indexes

• Case 2 – Low modulation indexes:Freeze center edgeMove both side edges in opposite directionGoes for low modulation indexes

71

Critical edge

Critical edges

Move critical edge

Move critical edges


Single Shunt Current Reconstruction – MC56F8013 Implementation

72

Timer ch. 3 Counter

Compare level sample #2



PWM Modulo Counter

ADC Conversion

ADC End-of-Scan ISR

PWM Reload ISRISR duration cca. 13.8us

Conversion time each 2.48us

ISR duration each 0.92us


BLDC Motor Commutation

73



►Six Step BLDC Motor Control• Voltage applied on two phases only

74

PWM Bt PWM CtPWM At


DC Bus

Ground

Shuntresistor

n

+U/2

- U/2

PWM Bb PWM CbPWM Ab

3-ph Brushless DC Motor

Shuntresistor



►Six Step BLDC Motor Control• Voltage applied on two phases only• It creates 6 flux vectors• Phases are powered based on rotor position• The process is called commutation

75

Phase voltages



►Complementary bipolar PWM switching

76

Q1=Q4=PWM; Q2=Q3=Q1


BLDC Motor Commutation – MC56F800x, MC56F80xx

77

PWM Value Register

00 0000 000

1.

2.

3.

4.

5.

6.

A B C

1010 1001 1001 10015999h ≈ 70% of max. value of Duty Cycle

when 7FFFh is the max. value

70%

30%

70%

30%

70%

30%

MASKPWM Channel Control Register

SWAP

One “shot” write to all six PWM channels!

Value written to this registerdefines just the speed of

motor rotation and

One “shot” write to all six PWM channels!

Value written to this registerdefines just the speed of

motor rotation and



78

PWM Channel Control RegisterMASK

PWM Value Register

00 1100 000

6. 5. 4. 3. 2. 1.transistors

MASK 1010 1001 1001 1001

0%

0%

5999h ≈ 70% of max. value of Duty Cycle when 7FFFh is the max. value

SWAP

Mask will disablethe complementary

transistor pair

Mask will disablethe complementary

transistor pair

1.

2.

3.

4.

5.

6.

A B C70%

30%

70%

30%



79

SWAPMASK

PWM Value Register

00 1100 100C B A

phases6. 5. 4. 3. 2. 1.

transistors

SWAP 1010 1001 1001 1001

PWM Channel Control Register

5999h ≈ 70% of max. value of Duty Cycle when 7FFFh is the max. value

Swap reroutes the top and bottom control

signals of complementary pair

Swap reroutes the top and bottom control

signals of complementary pair

Mask and Swap are set simultaneously! Value written to this register defines the

exact commutation stage.

Mask and Swap are set simultaneously! Value written to this register defines the

exact commutation stage.

0%

0%

1.

2.

3.

4.

5.

6.

A B C

70% 30%

30% 70%



►Advantage:• The MASK and SWAP feature is asynchronous to PWM generation• Speed control and commutation control are fully independent

►The same approach can be used on 56F82xx using FORCE_OUT logic►The 56F82xx allows preloading of new state and time for next

commutation. The commutation is performed based on timer event

80


Motor Control and Energy Conversion Demos

81


Sensorless BLDC Motor Control Using MC9S08MP16

►Six step commutation►Sensorless back-EMF zero

crossing detection technique►Back-EMF zero crossing

detection using internal comparators

►Running on MC9S08MP16►Both directions of rotation►Speed closed loop control►Torque closed loop control►Target applications:

• Fans• Compressors• Pumps• Appliances

82


Sensorless PMSM Motor Control Using MC56F80xx

► MC56F80xx digital signal controller► 3-phase AC/BLDC high voltage

power stage board► 1-phase line input 110/230VAC @

50/60Hz► Appliance PM motor► Initial rotor position detection► Full torque at motor start-up► Field weakening► Application based on C-callable

library functions (GFLIB, GDFLIB, MCLIB, ACLIB)

► Current control loop execution time: 55us

► Speed control loop with field weakening execution time : 17us

► Flash: ~ 6KB, RAM ~ 1.5KB► Reference design manual

83


AC/DC Switch Mode Power Supply

84

► 500W digitally controlled LLC resonant converter

► Input voltage• 85-265Vac @ 45-65Hz

► Output voltage• 12V/41 Amps (max.)• 5V/25 Amps (max.)

► Output power• 500W shared by both voltage outputs.

The power limit can be set individually by SW for each voltage output.

► Communication• PM bus communication (HW ready)• CAN communication (HW ready)• Communication with PC using USB

► Full fault protection• Over-voltage, over-current, over-

temperature on both primary and secondary side. Active controlled cooling


Solar Inverter using MC56F8023

85

► 400 VA digitally controlled solar inverter► One or two 200Wp solar panels► On grid/off grid operation► Single phase output 230V/50Hz or 115V/60Hz► Optional battery charger► MPPT algorithm implemented► Over-current, short circuit, input under-voltage protection

_freesclaemotorcontrol

Documents

digital signal

service names

respective

quicc engine

processor

freescale

freescale

2010 freescale