fpga system for flash memory final presentation
DESCRIPTION
FPGA System For Flash Memory Final Presentation. Project B, Winter 2013, HSDSL Lab, Technion Supervisor : Amit Berman Students : Baruh Nurilov Eyal Amir. Flash Overview. Very popular. Non-volatile. Small. Cheap. Uses. Disadvantages. Block erasure. Endurance. Errors. - PowerPoint PPT PresentationTRANSCRIPT
FPGA System For Flash MemoryFinal Presentation
Project B, Winter 2013, HSDSL Lab, Technion
Supervisor: Amit Berman Students: Baruh Nurilov
Eyal Amir
Flash Overview• Very popular.• Non-volatile.• Small.• Cheap.• Uses.
Disadvantages• Block erasure.• Endurance.• Errors.
* Micron NAND Flash memory - MT29F64G08CBAA - Datasheet
WOM Code• Write-Once Memory reuse.•
- Each n-bit codeword represents a k-bit word.- Guarantees at least t writes.
* Ronald L. Rivest and Adi Shamir, “How to Reuse a ‘Write-Once’ Memory”, Information And Controll Vol. 55, Nos. 1-3, November 1982
Project Goal• Designing a controller for flash memory that
implements reading, writing and erasing. • Measuring, using the above controller, the
amount of errors generated by repeated write-erase cycles.
• Assessing the potential advantages of using WOM codes in the writing process.
Overview
Data Generation
Writing
Writin
g
Comparison
Saving
Erasin
g
Reading
Readin
g
Block Diagram
Flash ModuleSDRAM Module
Flash Device SDRAM
PLLMain
Controller
The SDRAM Module
SDRAM Interface
SDRAM Controller
Ack_u
Cmd_u
Data_u_i
Data_u_o
Addr_u
Dram_cke
Dram_clk
Dram_cs_nDram_ldqm
Dram_udqm
Dram_addr
Dram_ras_n
Dram_dq
Dram_bank
We_i
Stb_iCyc_iAck_o
Addr_i
Dat_i
Dat_o
The Flash Commands
* Micron NAND Flash memory - MT29F64G08CBAA - Datasheet
The Flash Module
Flash Interface Flash Controller
Flash_ce_nFlash_re_nFlash_we_n
Flash_ale
Flash_cle
Flash_wp_n
Flash_dq
Flash_r_nb
Cmd_i
Addr_iData_i
Cmd_ena
Addr_enaData_in_en
aData_out_enaCmd_done
Addr_doneData_in_doneData_out_done
Status_checkErase_address
Data_o
Flash_wp_n_u
Flash_ce_n_u Last_word_tb
Next_word_tb
Done_tbWord_done_tb
Cmd_tb
Data_o_tb
Data_i_tb
Addr_tb
The Flash InterfaceFlash_ce_n
Flash_re_n
Flash_we_n
Flash_ale
Flash_cle
Flash_wp_n
Flash_dq
Flash_r_nb
Signal Controller
CommandFSM
Current_state
AddressFSM
Current_state
Data-InFSM
Current_state
Data-OutFSM
Current_state
Cmd_enaCmd_done
Addr_ena
Addr_done
Data_in_enaData_in_done
Data_out_enaData_out_done
A Command Cycle
* Micron NAND Flash memory - MT29F64G08CBAA - Datasheet
Flash Controller
Signal Controller
ReadFSM
Current_state
ProgramFSM
Current_state
ResetFSMCurrent_state
StatusFSM
Current_state
Cmd_enaCmd_done
Addr_ena
Addr_done
Data_in_enaData_in_done
Data_out_enaData_out_done
Last_word_tbNext_word_tbDone_tb
Word_done_tbCmd_tb
Data_o_tbData_i_tb
Addr_tbEraseFSM
Current_state
UserFSM
enabledone
enabledone
enabledone
enabledone
enabledone
The Main Controller
SDRAM Controller
Ack_u
Cmd_u
Data_u_i
Data_u_o
Addr_u
Flash Controller
Last_word_tbNext_word_tbDone_tb
Word_done_tbCmd_tb
Data_o_tbData_i_tb
Addr_tb
Main Controller
Data
Main ControllerAck_u
Cmd_u
Data_u_i
Data_u_o
Addr_u
Last_word_tbNext_word_tbDone_tb
Word_done_tbCmd_tb
Data_o_tbData_i_tb
Addr_tb
Signal Controller
Flash FSM
Current_state
Current_state
Main FSM
SDRAM FSM
tb_cmdenable_n
resetdone
get_data
data_valid
user_data
Results• • On average ~350 errors per block after 3000
cycles.• On average ~2e-5 BER after 3000 cycles.• On average ~46.5 errors per block on first write.
5 401 797 11931589198523812777317335693965436147570
200
400
600
800
1000
1200
f(x) = 2.99012874303865E-05 x² + 0.0115656528742944 x + 46.4751822843133R² = 0.99905257741302
Errors After Multiple Writes
Block 0AABlock 1A6Block 032Block 132Block 874AveragePolynomial (Average)
Write Cycles
Err
ors
5 2 23 10 0.0116 46.475 ( 0.9991)y x x R
Conclusions•
• k – bits to be written, n – bits after encoding,
t – number of writes between erases, R - WOM-rate.
•
1
ndata tobe written nkM erases for sameammount of data
t writes per erase k t
erases for sameammount of dataR
5 2350 3 10 ( ) 0.0116 46.475Mx Mx
* Scott Kayser, Eitan Yaakobi et al, “Multiple-Write WOM-Codes”, IEEE Transactions on Information Theory, 58 (9). pp. 5985-5999. ISSN 0018-9448.
Conclusions
Estimated R value Value of M
% improvement in device life
1.6 0.63 58%1.85 0.54 85%1.95 0.51 96%2.1 0.48 108%
2.15 0.47 112%2.25 0.44 127%2.3 0.43 132%
2.35 0.42 138%
7 532 10571582210726323157368242074732525757826307683273570
100200300400500600700800900
1000WOM Code Expected Improvment
AverageM=0.63M=0.54M=0.51M=0.48M=0.47M=0.44M=0.43M=0.42
Write Cycles
Err
ors
Questions?