fpga - field programmable gate array
DESCRIPTION
FPGA - Field Programmable Gate Array. S/V blo c k I/O Cell. S/V block I/O Cell. S/V block I/O Cell. S/V block I/O Cell. LB Logic Block. LB Logic Block. LB Logic Block. S/V block I/O Cell. S/V block I/O Cell. LB Logic Block. LB Logic Block. LB Logic Block. - PowerPoint PPT PresentationTRANSCRIPT
LBLogic Block
LBLogic Block
LBLogic Block
LBLogic Block
LBLogic Block
LBLogic Block
LBLogic Block
LBLogic Block
LBLogic Block
S/Vblock
I/OCell
S/Vblock
I/OCell
S/Vblock
I/OCell
S/Vblock
I/OCell
S/Vblock
I/OCell
S/Vblock
I/OCell
S/V blockI/O Cell
S/V blockI/O Cell
S/V blockI/O Cell
S/V blockI/O Cell
S/V blockI/O Cell
S/V blockI/O Cell
FPGA - Field Programmable Gate Array
The basic elements of the FPGA structure:
1. Logic blocks Based on memories (LUT – Lookup Table)
Xilinx Based on multiplexers (Multiplexers) Actel Based on PAL/PLA (PAL - Programmable
Array Logic, PLA – Programmable Logic Array) Altera
Transistor Pairs 2. Interconnection Resources
Symmetrical FPGA-s Row-based FPGA-s Sea-of-gates type of FPGA-s Hierarchical FPGA-s (CPLD)
3. Input-output cells (I/O Cell)
Possibilities for programming : a. Input b. Output c. Bidirectional
Buffering by triggers Slew Rate
The structure of FPGA
LB
SymmetricalArray
LB LB
LB
LB
LB
LB LB LB
Row-based
LB
LB LB
LB
LB
LBLB
LB LB
LB
Sea-of-Gates
LB LB LBLB LB
Hierarchical (CPLD)
PLA
PLA
PLA
PLA
PLA
PLA
PLA
PLA
Architecture of FPGA-s
0
1
1
1
1
1
1
1
X 3
X 2
X 1
Y
1 Y
X 3
X 2
X 1
Example: realisation of the OR function based on LUT
LUT
LUT
S
MUX
0
1
S
MUX
0
1
T
T
Logical block based on LUT-s
S
0
1
MUXS
0
1
MUX
S
0
1
MUX
0
0
1
1
X1
X2
X3
X2
X3
Y
Y = X1 X2 + X1 X3
X1 X2 + X1 X3
X3 X2
1 00 1
X1 = 0 X1 = 1
X3 = 0 X3 = 1 X2 = 0 X2 = 1
Example: realisation of function based on MUX-s.
LB
LB
LB
LB
CLK
SBCB CB
CB
CB
Connection arrays
Long lines
Connections between the neighbours
Interconnection resources
Symmetrical FPGAFPGA
Hierarchy of interconnection resources of a symmetrical FPGA
1. long lines throughout the array. 2. Clock signal (clk ) lines throughout the array. 3. General connection resource. 4. Direct connections between the “neighbours”
LB LB
Row of interconnection resources in a FPGA with architecture
LB LB
LBLB
Long lines over logical blocks
For example, Actel-i Act-1, Act-2 FPGA-d
Interconnection resources in Sea-of-Gates type FPGA
Cell CellCell Cell
Cell CellCell Cell
Cell CellCell Cell
Cell CellCell Cell
Neighbouring connections Connections in 4x4 blocks
Cell
Connections in 16x16 blocks4x4 cell
Connections in the array
I/O blocks
I/O blocks
I/Oblocks
I/Oblocks
16x16
For example. XILINX XC6200 and ACTEL-i ES serial arrays
Interconnection resources in CPLD type FPGA
PLA
PLA
PLA
PLA
PLA
PLA
PLA
PLA
Local connection
resource
PLA
PLA
PLA
PLA
PLA
PLA
PLA
PLA
I/O
blo
cks
I/O
blo
cks
I/O blocks
I/O blocks
I/O blocks
I/O blocks
Loc
al c
onne
ctio
n re
sour
ces
Local connection resource
Local connection resource
Glo
bal c
onne
ctio
n re
sour
ce
Logical block
Macrocell
Hierarchy of connections in CPLD:
1. Connections within macrocells 2. Local connection resource within the logical block. 3. lobal connection resource (Switch Matrix)
T
T
S/V contactI/O pad
S
MUX
0
1
S
MUX
0
1
I/O cells
.
Description of the hardware.(Boolean functions
Logical circuit,VHDL …)
Logical optimization /minimisation
Programming /Configuring
TechnologyMapping
Placement
Routing
Designing of hardware based on FGPA