Designed to replace obsolete ASSP IC’s, NDR created a Virtual ASSP Platform using Altera’s MAX®

10 FPGAs to quickly prototype and extend the life cycle of electronic sub-systems. NDR

configures the FPGA to the same function as the obsolete ASSP (license agreement or royalties

are not required). The original equipment manufacturer (OEM) does not need any knowledge

or design experience with FPGAs.

FPGAs provide customers benefits that ASSP’s can’t; some examples include:

• More hardware and embedded software customization options

• Bug fixes to the circuit, found during prototyping, can be made without PCB respin

• Multiple functions in a single FPGA (reducing cost, board space, R&D effort, as well as time to

market)

Evaluate the Virtual ASSP functions with only a 5-volt power supply and connecting pin header

See Figure 1.

NDR is an independent design and

manufacturing company based in

Osaka, Japan specializing in chip,

system, embedded, and software

development. NDR supports

prototype/mass production of

industrial equipment; especially

CPU boards running real-time

operating system (RTOS) and/or

Linux, or analog/digital boards.

P A R T N E R S O L U T I O N : V i r t u a l A S S P P l a t f o r m

FPGA-Based ASSP Replaces Obsolete ASSPs

Figure 1. Evaluating Virtual ASSP Functions with a 5-volt Power Supply and Connecting Pin Header

• SRAM-style bus interface

• Serial peripheral interface (SPI) sensor interface:

- SPI CLK 25 MHz (max.)

- 8-, 16-, 32 bit data

- SPI mode 0 ~ 3

• RX buffer = 1 KB/channel

• Hard/soft sampling

• SRAM-style bus interface

• 6821 Peripheral Interface Adapter (16 bit GPIO)

• 6840 Programmable Timer Module (2-channels)

• 64941 Asynchronous Communication Interface (1-channel UART)

• FPGA board chip p/n: NDR-ADIS801MT01

• Evaluation board p/n: NDR-ADIS801MT01-KIT01

• FPGA board p/n: NDR-DC3A01MT01

• Evaluation board p/n: NDR-DC3A01MT01-KIT02

• Web: http://ndr.co.jp/en/virtual-assap

• Email: info-fpga@ndr.co.jp

The ADIS801MT01 is a Sync SPI Master requiring multichannel sensor sampling at simultaneous and fast speed.

The DC3A01MT01 is a single-package software-compatible combination of 3 discontinued IC’s.

Technical Details

Technical Details

Ordering Details

Ordering Details

Contact Details

Description:

Description:

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Figure 2. Sync SPI Master, 8-channel ADC Block Diagram

Figure 3. GPIO / Timer / UART Block Diagram

P A R T N E R S O L U T I O N

Control Signal

Interrupt

ADDRESS

DATA

BUSI/F

External Trigger

FIFO

FIFO

FIFO

FIFO

SPIMASTER

SPIMASTER

SPIMASTER

SPIMASTER

CTRLREG

Control Signal GPIO_AGPIO_B

ENCLKOUT

TXRTCTRL

Interrupt

ADDRESS

DATA

BUSI/F

GPIOModule

TIMERModule

UARTModule

GlobalInterrupt