fpga algorithm development using a graphical...
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July 2004 1
FPGA Algorithm Development Using a Graphical Environment
GRETINA Electronics Working GroupJuly 25, 2004
RIS Corp.R. Todd
S. Pauly*
ORNL Physics DivisionJ. Pavan
D. C. Radford
July 2004 2
Overview
• Motivation • Process• Design Environment• Graphical Design Methodology• Evaluation Platform• Dual MCA • Real-Time Demonstration
July 2004 3
Motivation
• Reduce extensive VHDL coding requirements• Produce immediate feedback with simulation
• Desktop (high-level) development environment • vs. hardware-level testing
• Create re-usable library components• Applicable to all FPGA programming in system
July 2004 4
Process• Matlab™ and Simulink™ from The Mathworks• System Generator from Xilinx• Block diagram approach for algorithm and system
design • Generates VHDL code optimized for Xilinx FPGAs.• Tested on several platforms
• Evaluation boards• Dual MCA• LBNL GRETA 8-channel digitizer
July 2004 5
Design Environment
• FPGA functions provided by System Generator • counter, relational, memory, shift, multiply, delay, …
• Simulink blocks along with Xilinx In/Out blocks • FPGA pinout, simulation input data
• System Generator outputs VHDL • targets specific Xilinx FPGA, sets global clock
• Fixed point functions • Can use a specified precision (e.g. 14-bit), or • determines precision from driving blocks
• Black box function provided to allow user VHDL functions
July 2004 6
Design Environment
July 2004 7
Graphical Design Methodology• Draw block diagram
• Simulate design
• Modify diagram
• Generate VHDL
• Implement into FPGA
• Create bit file
• Program FPGA
July 2004 8
First Evaluation Platform• ADC Evaluation Board
• Analog Devices AD9432• 12 bits, 105 MSPS
• DAC Evaluation Board• Texas Instruments
DAC2904• 14 bits, 125 MSPS• Dual DAC
• FPGA Evaluation Board• Xilinx Spartan IIE • 100 MHz clock
ADC FPGA DAC12
14
14
July 2004 9
ResultsTrapezoidal Simulation Waveforms
July 2004 10
ResultsEvaluation Platform Waveforms
July 2004 11
ResultsVHDL Comparison
• Same FPGA resource usage for System Generator vs. Hand-coded VHDL
730362444.104730352334.299TrapzFil
441182673.740451182154.648TapDelay
330232104.770340242104.765GauFilt2
290202064.846300212154.652GauFilt1
IOB6RAMB1
sSlice
(MHz)Frequency Period (ns)IOB16
RAMBSlices(MHz)Frequency Period (ns)Name
System Generator VHDLHand Coded VHDLModule
July 2004 12
Graphical Approach Benefits
• Simulation provides immediate feedback• scope view of signals• A variety of Matlab and Simulink functions can be used to analyze
results or provide stimulus to the algorithm• Extensive knowledge of VHDL not required
• System Generator will produce VHDL for the targeted Xilinx FPGA• Makes extensive use of Xilinx cores including Virtex hardware
multipliers• Makes use of synchronous design with one system clock
• Subsystems and custom libraries permit design re-use• Drag and drop of Xilinx library functions• Drag and drop of User library functions• Drag and drop of Simulink functions for creation of stimulus (model
a detector with noise for example)
July 2004 13
Evaluation Platform:LBNL GRETA 8-channel Board
July 2004 14
Evaluation Platform:LBNL GRETA 8-channel Board
• Uses VHDL wrapper• Re-use I/O Pads from LBNL code• Structure instantiating one channel multiple times
• Filter• LE Discriminator• PZ correction• CFD• Programmable Parameters for each channel
• PZ, rise, dwell, noise threshold, CFD
• Packetizer to gather data and send to FIFO• VME Interface
July 2004 15
GRETA ADC Filter
July 2004 16
Simulation Scope Traces
•LE Discriminator
•CFD Output
•CFD1 for time interpolation
•Trapezoidal Output
July 2004 17
Event Detector
July 2004 18
Trapezoidal Shaper
July 2004 19
PZ Corrector
July 2004 20
LocalDecoder
• Sets:• Rise Time• Apex Time• Pole Zero• Threshold• CFD
July 2004 21
Shaping Filters• Cusp
• Cusp_FIR• Polynomial Cusp• Quad Cusp
• Differentiator• Gaussian
• Fast Gaussian• Gaussian_BRAM• Gaussian_FIR• Gaussian_FSR• Gaussian_SR
• Trapezoid• Trapezoid_BRAM• Trapezoid_BRAM_fixed• Trapezoid_FIR• Trapezoid_SR
• Triangle_FIR
July 2004 22
Dual MCA
July 2004 23
Dual MCA Scope Photo of Input Pulse with Shaped Output
July 2004 24
Co-60 Spectra using Dual MCARIS Digitizer 5 minutes Co-60
0
200
400
600
800
1000
1200
0 200 400 600 800 1000
Channel Number
Cou
nts
• All Shaping and Histogram implemented inside FPGA• MATLAB & Simulink Tools used exclusively
July 2004 25
Real-Time Demonstration
July 2004 26
Summary
• Graphical Environment Tools developed under DOE STTR contract for GRETA
• VHDL expertise not required• Immediate feedback from simulation • Useful Library developed: drag & drop • Widely applicable beyond GRETA digitizer
• e.g. trigger system, BaF2 detectors, …• Working Dual MCA