forward error correction: a powerful & indispensable ... · - 1st gen. rs(255,239) - 2nd gen....

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1

Forward Error Correction: A Powerful & Indispensable Technology

for Ultra High Speed Transmission

Kiyoshi Onohara and Takashi MizuochiMitsubishi Electric Corporation


2

Presenter Profile

Kiyoshi Onohara received the B.E., M.E., and Ph.D. degrees in communication engineering from Osaka University, Osaka, Japan, in 2000, 2002, and 2005, respectively.In 2005, he joined Mitsubishi Electric Corporation, Kamakura, Kanagawa, Japan, where he has been engaged in research and development of the applications of forward error correction, optical cross-connect, and supervisory system for optical transport networks.

Kiyoshi OnoharaResearcherEmail: [email protected]: (+81) 467 41 2443


3

Outline

The basics and history on FEC - Key terms related to FEC- 1st Gen. RS(255,239)- 2nd Gen. concatenated codes- 3rd Gen. soft decision decoding

FEC for 100G era - Needs higher SNR- Soft decision FEC in digital coherent systems- Low-density parity-check codes (LDPC)

FEC emulator- FPGA based emulator- Pipelined architecture

Circuit implementation issues for true 100G throughput FEC- Reduction of circuit size to implementation- LSI partitioning- Triple-concatenated FEC- Improvement of correcting algorithm

Impact on next generation submarine cable systems- Accommodating a range of interfaces- Relief from the need for DCFs - Migration scenario

Summary


4

Basics and Historical Perspective on Forward Error Correction


5

Forward Error Correction - Brief Explanation -

+ additive noise+ waveform distortion

bit errors

1 0 1 1 0 0 1 0

1 0 1 0 0 1 1 0 0 0

transmitted data parity

1 0 1 1 0 0 1 0 1 0

received dataError detection

& correction

Adding to the transmitted signal data a parity code that enables the receiver to detect and evaluate the data errors in the transmission channel

1 0 1 0 0 1 1 0

no errors

Optical fiberO/E

E/O

FEC encoder

FEC decoder O/E

E/O

Clientdata

Clientdata

O/E

E/O

FEC decoder

FEC encoder O/E

E/O

caused by chromatic dispersionfiber nonlinearity


6

TerminologiesInformation bit (byte) Original digital signal to be FEC encoded before transmission

FEC parity bit (byte) Redundant bit (byte) generated by FEC encoding

Codeword Information bit (byte) plus FEC parity bit (byte)

Code rate R Ratio of bit rate without FEC to bit rate with FEC

Redundancy ratio

BERin BER of the encoded line signal (= BER of the input signal to the FEC decoder)

BERout BER of the decoded client signal (= BER of the output signal from the FEC decoder)

Q and BER

xxx (n, k) code xxx = code class (BCH or RS). n = number of codeword bits (bytes) k = number of information bits (bytes)

Coding gain (CG)Net coding gain (NCG)

CG: BER reduction by the FEC expressed in dB.NCG: CG corrected by the increased noise due to bandwidth expansion needed for

FEC bits assuming white Gaussian noise.

Source: ITU-T Series G, Supplement 39, Dec. 2008

the number of FEC redundancy bitsthe number of information bits

e.g. RS(255,239)

255-239239 = 6.69%

)dB(log102erfclog202erfclog20 101

10ref1

10 RBERBERNCG in

)dB(2erfclog202erfclog20 110ref

110 inBERBERCG

)2

(21 QerfcBER


7

Net Coding Gain

)dB(log102erfclog202erfclog20 101

10ref1

10 RBERBERNCG in

10-2

10-4

10-6

10-8

10-10

10-12

10-14

Out

put B

ER

(Pos

t-FE

C B

ER

) BER

out

9 10 11 12 13 14 15 16 17 18Q of the input signal to the FEC decoder (dB)

8

NCG = 5.6dB @10-12

uncoded

RS(255,239)10-16

NCG = 6.2dB @10-15

10log10 R

BER ref

CG = 5.9dB @10-12

BER ref

inBER2erfclog20 110

Q limit

NCG takes into account the fact that the bandwidth extension needed for these FEC schemes is associated with increased noise in the receiver.

outref BERBER

e.g) RS(255,239)

)dB(3.093.0log10 10

93.0R


8

History of Forward Error Correction

1950

1960

1970

1980

1990

2000

2010

Shannon’s theory

Convolutional Code

Hamming Code

Cyclic Codes

Reed-Solomon CodesBCH CodesLDPC Codes

Viterbi Decoding

Trellis CodesBCJR Decoding

Soft-Output Viterbi Algorithm

Turbo Codes

Viterbi Block Decoding

RS(255,239)

Concatenated Codes

Block Turbo Code

LDPC Codes

Concatenated Codes

1940

Optical Fiber

Laser

Commercial Systems

• Originated with C.E.Shannon’s • “A mathematical theory of communication” in 1948.

For a long time, no trial appeared in opt. commun.

Widely used in digital radio and satellite communication systems.


9

Which is the Most Effective Way?

In order to improve the system performance - - - -

0

1

2

3

4

5

6

7

8

9

10

NRZ RZ

1.48um 0.98um

EDFA Raman

OOK DPSK

SMF

PreciousFiber

No FECWith FEC

Impr

ovem

ent (

dB)

ITU-TFEC

BTCFEC


10

1st Gen. FEC - ITU-T Standard - ITU-T Recs. G.975 and G.709 RS(255,239)

- Symbol error correcting code- Byte number is used in the designation- Up to 8 bytes in the codeword can be corrected- The frame employs 16-byte interleaving- 1017 continuous error bits can be corrected

Error Correction Performance can be calculated easily

INTERNATIONAL TELECOMMUNICATION UNION

ITU-T G.975SERIES G: TRANSMISSION SYSTEMS AND MEDIA, DIGITAL SYSTEMS AND NETWORKSDigital transmission systems – Digital sections and digital line system – Optical fibre submarine cable systems

Forward error correction for submarine systems

N–iSE

iSE

N

iUE PPN

iNiP )1(

9

81)1(1 /SEPp

81)1(1 /UEc Pp

p = BERinPUE is the probability of uncorrectable errorsPSE is the probability of symbol (byte) errorsN = 255

I. S. Reed, and G. Solomon, “Polynominal codes over certain finite fields,” SIAM J. Appl. Math., vol. 8, pp. 300-304, June 1960.


11

2nd Gen. FEC - Concatenated Codes -

RS(255,223) + RS(255,239) O. Ait Sab (Alcatel), ECOC’99, II-290RS(239,223) + RS(255,239) T. Mizuochi (Mitsubishi), SubOptic2001, P.4.2.3RS(144,128) + RS(248,232) J. Yoshimura (Fujitsu), SubOptic2001, T.4.4.4RS(255,223) + RS(255,239) F. Kerfoot (Tyco), OFC2002, WL1RS(255,239) + CSOC K. Seki (NEC), CICC2002, 9.3

As WDM matured in 2000~, researchers started to seek more powerful FECs.

A class of error correcting codes that are derived by combining an inner code and an outer code.

As a solution for the problem of finding a code that has both exponentially decreasing error probability with increasing block length and polynomial-time decoding complexity.

Sym

bol

Inte

rleav

er

Out

erE

ncod

er

Sym

bol

de-In

terle

aver

Inne

rE

ncod

er

Noise

Sym

bol

de-In

terle

aver

Out

erD

ecod

er

Sym

bol

Inte

rleav

er

Inne

rD

ecod

er

iteration

+

TransmissionLine

payload

parit

y

parit

y

Inner codeOuter code G. D. Forney, Concatenated

Codes, The MIT Press, Cambridge, MA, 1966.

CSOC: Convolutional Self-Orthogonal Code


12

Example of Practical 2nd Gen. FEC Concatenated RS(239,223)+RS(255,239)

with iterative decoding- Released in 2000- 14.2% redundancy (11.4Gb/s for STM-64)- 16-deep interleaving- 8.0 dB of net coding gain (BERref = 1E-11)

2nd Gen. FEC LSI on circuit board

Row #1Row #2

Row #n

overhead

Payload

RS

(239,223)redundancy

223R

S(255,239)

redundancy16

239 16

10-1

BERin

BER o

ut

This FEC

Uncoded

RS(255,239)

10-1

10-3

10-5

10-7

10-9

10-11

10-2 10-3 10-4 10-5T. Mizuochi, et al., P4.2.3, SubOptic2001, Kyoto, Japan


13

Seeking More Powerful FEC - 3rd Gen. FEC -

BERin <10-13 Targeted BERin = 2x10-2

The major interest then shifted to the advent of even more powerful FEC.

The purpose is not only to increase capacity, but also for reducing CAPEX, easy upgrades and utilizing legacy cable and repeaters

We will call this class of FEC, 3rd Gen. FEC.

- based on soft-decision - iterative decoding, - having NCGs of 10 dB or more

3rd Gen. FEC is to try to correctthis very noisy channel.

T. Mizuochi, et al., “Forward error correction based on block turbo code with 3-bit soft decision for 10 Gb/s optical communication systems,” IEEE J. Selected Topics in Quantum Electronics, vol.10, no. 2, pp. 376-386, March/April, 2004.


14

Soft Decision Decoding

Decision thresholdConfidence thresholds

Confidence thresholds

1 1 1 1 00 0 0Hard-decision

Confidence information 10 11 10 00 11 01 00 01

Typical 3-bit Soft-decision

2

2

2 2),(

exp2

1)|(

ydyp jE

j

Soft decision decoder calculates not only MAP of hard-decision but also that of the trial corrections.In theory, we can get more 2dB coding gain compared to hard decision decoding.

Performed by using multiple confidence thresholds as well as a hard-decision threshold

Need to calculate the maximum a posteriori probability (MAP) for the AWGN Channel

It could be !

y: received codej : codeworddE : Euclidian distance

1 1 0 1 00 0 0Trial corrections 1 1 0 1 10 0 0

1 1 1 1 00 0 01 1 1 1 10 0 0


15

Turbo Codes

Turbo CodeBasic idea was invented by C. Berrou, et al., ICC’93, pp. 1064-1071, 1993.Analogy of turbo engine for cars

Turbo Convolutional Code (TCC) and Block Turbo Code (BTC)TCC shows greater correction ability than BTC at low code rates

> Widely used in wireless communicationsBTC shows better performance at high code rates

no error floor because of its large minimum distance (16 or greater is typical)only minor flaring occurred at very small output BER. No puncturing is required > All of these advantages seem to make it suitable for optical communication

systems

First proposal for optical communicationsAit Sab was the first to calculate the performance of a BTC based on product codes for optical communication systems

O. Ait Sab, et al., OFC2000, ThS5


16

BTC Error Correction PerformanceRedundancy 23.6%

Bit rate 12.409 Gb/s @ STM64

Q limit 6.26dB @ BERref = 10-13 1.9x10-2 1.1x10-13

Gross coding gain 11.1dB @ BERref = 10-13

Net coding gain 10.1dB @ BERref = 10-13

Uncoded

RS(255,239)

BTC

10-15

10-13

10-11

10-9

10-7

10-5

10-3

10-1

4 6 8 10 12 14 16 18

Q (dB)

BER o

ut

T. Mizuochi, “Recent progress in forward error correction and its interplay with transmission impairments,” IEEE J. Selected Topics in Quantum Electronics, vol.12, no. 4, pp. 544-554, July/August, 2006.


17

Summary of Three Generations of FECGen. Decision Coding Code rate NCG (dB)

@10-13

1st Hard Cyclic codes / Algebraic codese.g. RS(255,239)

0.93 5.8

2nd Hard Concatenated codese.g. RS+BCH,

RS+RS

0.93-0.79 <10

3rd Soft Soft-decision & Iterative decodinge.g. Block turbo code

> 0.80 >10

1st Gen. FEC

Q=11.2dB, BERin =1.5x10-4

2nd Gen. FEC

Q=8dB, BERin =5x10-3

3rd Gen. FEC

Q=6.3dB, BERin =2x10-2

Correctable Waveforms


18

Forward Error Correction for 100G Era


19

Needs Higher SNR

In the pursuit of high speed transmission, we should consider that multi-level modulation needs a higher SNR than binary formats.

This has increasingly motivated research activity of more powerful, but nevertheless practical FEC for the improvement of OSNR tolerance in 100G digital coherent systems.

64-QAM

16-QAM

8-PSK

QPSK

PSK

2

4

6

8

10

12

14

16

18

10 100

DPSK

OOKDQPSK

OOKDP-16QAMDQPSKDPSKDP-QPSK

DP-16QAM

DP-QPSK

20 40Bit rate (Gb/s)

Req

uire

d O

SNR

(dB

in 0

.1nm

)

5.7dB

1.3dB2.7dB


20

Soft Decision FEC in Digital Coherent

Conveniently, a digital coherent receiver incorporates A/D converters (ADCs) at its front-end for demodulating multi-level coded signals

This suddenly makes it much easier to realize soft-decision decoding

DP-QPSK RX

Module

DP-QPSK RX

Module

6-bit ADC

6-bit ADC

6-bit ADC

6-bit ADC

DSP(CR, FDE

Pol. Demux)

EuclideanDistance

LLR Calc.

Soft Dec.FEC

Decoder

r

6-bit 6-bit 3-bit

(00)(01)

(11) (10)

Corrected Output

100G DP-QPSK

Digital Coherent LSI

EuclideanDistance

DSP: Digital Signal Processor, CR: Carrier Recovery, FDE: Frequency Domain Equalizer, LLR: Log-likelihood Ratio


21

Challenge for 100G Throughput FECChallenge for 100G Throughput FEC

The product of (linear) net coding gain and bit rate (in Gb/s) shows a clear trend where an improvement of 1.4 times has been achieved every year.

This improvement has been achieved not only by FEC algorithm improvements, but also by LSI technology evolution.

Very strong FECs can be a key enabler for DSP-based 100G transmission.

2.5Gb/s

100Gb/s

40Gb/s

10Gb/s

’86 ’88 ’90 ’92 ’94 ’96 ’98 ’00 ’02 ’04 ’06 ’08 ’10 ’12

Net

cod

ing

gain

–Bi

t rat

e pr

oduc

t (G

b/s)

( def

ined

in te

rms

of a

pos

t-FE

C B

ER

of 1

0-15 )

Year’14 ’16 ’18

RS(255,239)40Gb/s

2.5Gb/s

10Gb/s

100Gb/s

Shannon limit(Soft decision, 25% redundancy)

1st gen. RS(255,239）2nd gen. Concatenated codes, Iterative decoding3rd gen. Soft decision, Iterative decoding100

101

102

103

104

100Gb/s (target)

x1.4 every year

T. Mizuochi, et al., IEEE Photonics Society Summer Topicals, WC1.1


22

Low-Density Parity-Check Codes – LDPC –A linear code, defined by a very sparse parity check matrix

Invented by Robert Gallager in his 1960 MIT Ph.D. dissertation. Long ignored.- R. G. Gallager, IRE Trans. Inform. Theory, Jan. 1962.

Re-discovered by D. MacKay in 1996.

First calculation for optical communications- B. Vasic and I. B. Djordjevic., IEEE Photon. Technol. Lett., Aug. 2002.

Merits- Very strong error correction capability- Parallelization to reduce circuit complexity- Very suitable for LSI Implementation


23

Error Floors of LDPC codes

“Error-floor”, frequently observed in the measured post-FEC BER.

Even though an FEC may show superior performance at a post-FEC BER of 10-7,if there is an error floor at 10-8, such an FEC is unusable.

Codeword length

Redundancy ~35% ~10% ~3%or

~20000 ~4000 ~460

3 4 5 6 7 8 9 10 11 12 13Pre-FEC Q (dB)

Pos

t-FE

C B

ER

uncoded

g=6g=8g=10

union bound

Error Floor

Y. Miyata, et al., OFC/NFOEC2008, OTuE4

To avoid the error-floor

- Expansion of the codeword length. Longer codeword requires larger circuit size.

- Increase the redundancy. Larger redundancy needs to higher bit rate.

10-1

10-2

10-3

10-4

10-5

10-6

10-7

10-8

10-9

10-10

10-11

10-12

10-13

10-14

10-15

Union bound

the approximation of post-FEC BER with maximum likelihood decoding at the high Q-limit.

affected by the girth g, which is the length of the short loop in the parity check matrix.


24

Combating Error Floor

Concatenated LDPC + RS

LDPC(9216,7936) + RS(992,956) , 20.5% redundancy

Encoder

Decoder O/EO/E

E/OE/O

LDPC code(inner code)

RS code(outer code)

Client input

Client output

IterationDe-inter-leave

Interleave

Soft-decision

Soft-decision

Encoder

Decoder

Concatenation of another weak code can effectively eliminate the undesired error floor, without increasing circuit complexity.

Y. Miyata, et al., OFC/NFOEC2008, OTuE4

The RS code shows higher tolerance to error bursts than BCH codes.


25

FEC Emulator


26

Developed FEC Emulator

Throughput : 2 Gb/s x 16 ch

CMOS process: 90nmCircuit size per FPGA: 2 million gatesOperating frequency: approx. 100 MHzThroughput : 12.4 Gb/s

MUX/DEMUX BoardsMUX/DEMUX Boards

RS Encoder/DecoderLDPC Encoder

LDPC Decoder

MUX DEMUX

FEC Emulator (Encoder/ Decoder)FEC Emulator (Encoder/ Decoder)


27

Pipelined Architecture

InRAMIn

RAMOut

RAMOut

RAM

DecoderDecoder

Through except for block p

Extra

ctin

g bl

ock

p

Inse

rting

blo

ck p

into

the

next

fram

e

# Extracted block by decode core #

Decoded block by decode core ##

In order to emulate huge circuit operation, e.g. iterative decoding, a pipelined architecture is a key to implement with concatenated FPGAs

FPGA board #1 FPGA board #n

time

12345678123456

FPGA#1

1

FPGA#2

1

12

2

2

FPGA#8

8

8

・・・

dec

dec

dec

dec

dec

InputData

781

1

…

Pipelined processing of iterative decoding using concatenated Pipelined processing of iterative decoding using concatenated FECFEC emulator boardsemulator boards

By concatenating n-boards, we can expand of the emulation circuit size up to 16 x n million gates

…


28

Setup for FPGA Prototyping

10GbETest

31.3Gb/sOOK ASE

Gear Box

RS ENC ILIL

Pre-Skew

LDPC ENC

31.3Gb/s

Gear Box Fsync De-

SkewSoft Dec

LSI

MX

2bitIteration

FIFO

+

Dummy

ILCopy

RS DEC dILdIL LDPC

DEC dIL

10.3Gb/sPRBS31

12.5Gb/s 15.6Gb/s

LN Mod

PDTIA

…

0.13 m SiGe BiCMOS

FIFO


29

FPGA Prototyping

Real-time emulation using high-speed FPGAs

LDPC+RS FEC in FPGAs

2G MUX Board

31.3G MUX

Soft Decision LSIon DEMUX


30

Experimental Results

100

10-310-210-1

Pre-FEC BER

Pos

t-FE

C B

ER

10-1

10-2

10-3

10-4

10-5

10-6

10-7

10-8

10-9

10-10

10-11

10-12

10-13

LDPC(9216,7936) only

ConcatenatedLDPC(9216,7936) + RS(992,956)8.9x10-3 2.5x10-13

Simulation

31.3Gb/s AWGN OOK, 2-bit soft dec., 4-iteration


31

Hard/Soft dec. and Number of Iterations

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

6 7 8 9 10 11

Out

put B

ER

Pre-FEC Q (dB)

Hard dec.measured,4-iteration

2-bit Soft dec.measured, 4-iteration

2-bit Soft dec.

calculated, 4-iteration8-iteration16-iteration

Soft dec.2.2dB better than hard dec

Number of iterations4, 8, 16

Expected NCG @10-15

9.9dB(1.2x10-2 1x10-15)2-bit soft dec.16-iteration


32

Circuit implementation issues for true 100G throughput FEC


33

Circuit Implementation Issues for 100G Systems

Why is the product of NCG and bit rate plotted?This is because the circuit size is proportional to not only NCG but also bit rate.

2.5Gb/s

100Gb/s

40Gb/s

10Gb/s

’86 ’88 ’90 ’92 ’94 ’96 ’98 ’00 ’02 ’04 ’06 ’08 ’10 ’12

Net

cod

ing

gain

–Bi

t rat

e pr

oduc

t (G

b/s)

( def

ined

in te

rms

of a

pos

t-FE

C B

ER

of 1

0-15 )

Year’14 ’16 ’18

RS(255,239 )

40Gb/s

2.5Gb/s

10Gb/s

100Gb/s

Shannon limit(Soft decision, 25% redundancy)

1st gen. RS(255,239）2nd gen. Concatenated codes, Iterative decoding3rd gen. Soft decision, Iterative decoding100

101

102

103

104

100Gb/s (target)

x1.4 every year


34

Circuit Implementation Issues for 100G Systems 10G SD-FEC using FPGA emulator (90nm CMOS)

For 4-iteration, 1 emulation board, 16 Mgates neededFor 16-iteration, 4 emulation boards, 64 Mgates needed

100G SD-FEC by using the same architecture:

40 emulation boards for 16-iteration are needed64 Mgates x (100 / 10) = 640 Mgates

FPGA Emulator

640 Mgates?

40 boards for 100G


35

Reduction of Circuit Size for 100G Throughput FEC (1) LSI partitioning

OIF-FD-100G-DWDM-01.0100G Ultra Long Haul DWDM Framework Document

OIF proposed that the internal FEC encoder/decoder is implemented into transceiver module as an option.

This architecture facilitates the implementation issues underlying not only transceiver module but also 100G framer.


36

Reduction of Circuit Size for 100G Throughput FEC (2) Triple-concatenated FEC to short the length of the LDPC code

The redundancy of the LDPC(9216,7936) as discussed before, is 16%.

The ratio of the LDPC code of the proposed triple-concatenated FEC with Enhanced FEC is 13%, resulting in the circuit size reduction.

By applying the shorter code length of LDPC, we suffer from the error floor performance. Enhanced FEC does not degrade, but assists the coding gain.

Pre-FEC BERPos

t-FE

C B

ER

Pre-FEC BERPos

t-FE

C B

ER

Conventional FEC and frame format

Proposed FEC and frame format

~10-5

~10-3

Inner FEC decoding

Outer FEC decoding

Payload LDPC

row1row2row3row4

OH

13%7%

RSPayload LDPC

row1row2row3row4

OH

16%4%

OTU4 frame

EFE

C


37

Performance Evaluation• Performance evaluation by Monte Carlo simulations

– LDPC+EFEC has no error floor at least down to a post-FEC BER of 1E-11– We expect that proposed concatenated codes can achieve

a Q-limit of 6.4 dB (NCG of 10.8dB) at a post-FEC BER of 1E-15.• 4.6 dB better than the standard RS(255,239) code

1E-15

1E-13

1E-11

1E-09

1E-07

1E-05

1E-03

1E-01

5.5 6.0 6.5 7.0 7.5Q [dB]

Bit

Err

or R

atio

UncodedLDPC onlyLDPC + EFEC

1E-15

1E-13

1E-11

1E-09

1E-07

1E-05

1E-03

1E-01

5.5 6.0 6.5 7.0 7.5Q [dB]

Bit

Err

or R

atio


1E-15

1E-13

1E-11

1E-09

1E-07

1E-05

1E-03

1E-01

5.5 6.0 6.5 7.0 7.5Q [dB]

Bit

Err

or R

atio



38

Reduction of Circuit Size for 100G Throughput FEC (3)

Improving the error correction algorithm

Variable Offset Belief Propagation (BP) based algorithm

Simple Log Likelihood Ratio calculationMathematical function approximated by variable offset factorNearly identical performance to conventional Shuffled BP AlgorithmNearly 90% reduction of the operations against conventional Shuffled BP Algorithm

Applying to state-of-the-art CMOS process

32 ~ 22 nm CMOS processes are available in a few years

100G LSI having NCG of more than 10 dB may emerge in 2011 ~ 2012


39

Impact on next generation submarine cable systems


40

Impact on Next Gen. Submarine Cable Systems

A digital coherent transceiver with this powerful FEC pushes a submarine line terminal equipment (SLTE) with 100 Gb/s interfaces towards fruition.

A range of interfaces: 2 x 40 Gb/s and 10 x 10 Gb/s

Relief from the need for dispersion compensation fibers by implementing a dispersion compensator in the DSP

Pure-silica fiber can be installed when constructing new cable systems, resulting in reduced capital expenditure

The powerful FEC enables us to migrate from existing 40 Gb/s long- haul systems to 100 Gb/s DP-QPSK systems

40G DPSKwith EFEC

100G DP-QPSKwith SD-FEC

Upgrade Scenariofor submarine cable systems


41

Conclusion

Expectations of stronger FECs for 100G transmission discussed

1.3~2.7dB stronger NCG than 40G Enhanced FEC expected

FPGA prototyping developed

LDPC code concatenated with RS codePipelined architecture, 31.3Gb/s throughput

Error correction experiment carried out

7.5dB input Q can be corrected to 10-13 (2-bit soft dec., 4-iterations)9.9dB NCG @10-15 is expected

Soft decision FEC for coherent systems proposed

Triple Concatenated LDPC with EFEC

Circuit implementation issues for 100G systems are discussed

Hard decision FEC in OTU4 framer LSI + soft decision FEC in coherent DSP LSI100G LSI having NCG of >10dB may emerge in 2011 ~ 2012

This work was in part supported by the project of “Digital Coherent Optical Transceiver Technologies” of the Ministry of Internal Affairs and Communications (MIC) of Japan

2010

Pacifico Convention Plaza Yokohama& InterContinental The Grand Yokohama

11 ~ 14 May 2010

www.suboptic.org

enabling the next generation of networks & services

The 7th International Conference & Conventionon Undersea Telecommunications

conference & convention

forward error correction: a powerful & indispensable ... · - 1st gen. rs(255,239) - 2nd gen....

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