Formal Methods and Physical Design:Match Made in Heaven

or Fools’ Paradise?

Formal Methods and Physical Design:Match Made in Heaven

or Fools’ Paradise?

Dr. Carl SegerStrategic CAD Labs, Intel

November 18, 2008

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OutlineOutline

• Brief Introduction to Physical Design

• Using Formal Techniques in Physical Design

• Two Illustrative Examples Electrical Level Example Physics Level Example

• Lessons and Future Work

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Introduction to Physical DesignIntroduction to Physical Design

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Making MicroprocessorsMaking Microprocessors

• The process from silicon (sand) tofinished microprocessor, can bedivided into two distinct phases: The design of the microprocessor The manufacturing of the

microprocessor

• Intuitively, the design comes before the manufacturing.

• However, there are very many aspects of the manufacturing process influencing the design process, so that both must be understood for successful processor design.

+

5

OriginalProductTarget

ArchitectMicro-

ArchitectDesign

EngineerMask

DesignerTest

Engineer

MAS Schematics Layout/Mask

RTL

The Design Process at 10,000 ftThe Design Process at 10,000 ft

Architecture

Analysis

Development

of micro-

architecture

Mapping

of RTL to

transistors

Development

of mask

that yield

transistors

and wires

Making Silicon

+

Stepping(s)Chip

Ideas

Validation

MAS: Micro-Architecture Specification

RTL: Register-Transfer Language

6

OriginalProductTarget

ArchitectMicro-

ArchitectDesign

EngineerMask

DesignerTest

Engineer

MAS Schematics Layout/Mask

RTL

Physical DesignPhysical Design

Architecture

Analysis

Development

of micro-

architecture

Mapping

of RTL to

transistors

Development

of mask

that yield

transistors

and wires

Making Silicon

+

Stepping(s)Chip

Ideas

Validation

MAS: Micro-Architecture Specification

RTL: Register-Transfer Language

7

Characteristics of Physical DesignCharacteristics of Physical Design

• Yesterday: Individual problems often relatively simple Size of data main difficult Most logic designs could be realized

• Today/tomorrow Accuracy requirements rapidly rising

- The problems are by themselves much harder Size of data growing extremely rapidly

- E.g., modern micro-processor:– 109 transistors– 1010 wires– 1012 polygons

- Compare: 1011 is approximately all pages on the WEB Some logic designs not realizable

- There are constraints from physical implementation that affects logic design as first order effects.

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Formal/Symbolic MethodsFormal/Symbolic Methods

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IntroductionIntroduction

• Suppose you have the following circuit and would like to understand what Boolean function the circuit computes.

• Two approaches: Simulate every input combination

- Not feasible for larger/more realistic circuits Build the output expression by symbolically

simulating the circuit

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Symbolic Simulation Using BDDsSymbolic Simulation Using BDDs

A

B

~A

AB

A(~ B)

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Traditional Use of Formal MethodsTraditional Use of Formal Methods

• Formal Verification Formal Equivalence Verification

- Is spec model the same as imp model

- Used extensively and is a “must do” for tape-out Formal Property Verification

- Does this circuit satisfy some desired property

- Used extensively for “small” properties

- Starting to get more wide-spread use for “large” properties

• Synthesis Computation of don’t cares Simplification of logic

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Symbolic Methods in Physical DesignSymbolic Methods in Physical Design

• Four major questions: Which level of abstraction?

- Electrical, component, layout, or mask Which question is to be answered?

- Find a (good) solution

- Find the best solution

- Make sure all cases satisfies something

- Characterize the viable design space Which encoding should be used?

- Bit-level or word level

- Arithmetic encoding: binary, unary, … Which formal method should be applied?

- BDDs, SAT, SMT, …

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Electrical Level ExampleElectrical Level Example

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Leakage MinimizationLeakage Minimization

• Background Transistors are not perfect switches

- Even when “off”, a small leakage current will go through the transistor

Given a combinational circuit:- What is the maximum leakage?

- Compute an input pattern that produces the minimum leakage

For a circuit with a couple of gates, this is not that difficult to compute. However, what if the circuit looks like:

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Interesting ProblemInteresting Problem

a[7:0]b[7:0]

o[7:0]

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BackgroundBackground

• One can approximate a leaky transistor as:

r

Rwhere R>>r

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Background cont.Background cont.

• Examples of CMOS gates:

a

a

a o

o

oab

a

ao

b

b

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Background cont.Background cont.

• From dusty secondary school Physics:

• We can use these to compute the equivalent resistance of a gate if we know which switches are on and off

r1

r2

r1+r2 r1 r2

r1r2r1+r2

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Symbolic AlgorithmSymbolic Algorithm

• Try to re-phrase the algorithm to make it “data independent” or “data oblivious”

• Idea: Design a “circuit” that takes as inputs the

Boolean values of the primary input (in our example a[7:0] and b[7:0]) and that computes a bit-vector representation of the resulting leakage

Questions:- How to encode the circuit- How to encode the resistances, currents, etc.

– Binary vs. unary encoding- How much accuracy is actually needed- …

• Simplistic approach for illustration:

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Modeling the transistors/gatesModeling the transistors/gates

Example done inForte systemusing reFLect

Transistor models

Interconnect models

Gate models

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ExamplesExamples

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ExamplesExamples

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Complete AlgorithmComplete Algorithm

• Use symbolic simulation to compute the Boolean expression over the input variables for every gate.

• For each gate: compute symbolically the resistance R for the

gate given the gate functions Compute (a scaled version) of 1/R

• Add all the 1/R’s together and invert the result

• 35 seconds later a BDD with 3947 nodes is produced representing every possible equivalent resistance (i.e., the leakage) for the whole circuit given it’s input values

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In Forte:In Forte:

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In Forte:In Forte:

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To Answer Interesting QuestionsTo Answer Interesting Questions

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To Answer Interesting QuestionsTo Answer Interesting Questions

• Notice: By picking suitable “sleep state” inputs, we can reduce the leakage power by >15%

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Other Electrical ExamplesOther Electrical Examples

• Compute the pair of input vectors that causes the largest amount of switching in the circuit Note: If gates have delays, one can get more

than n switchings in a circuit of size n!

• Compute input vectors that cause the maximum of noise in some wire (inductive/capacitive coupling between wires)

• …

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Physics Level ExamplePhysics Level Example

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Mask MakingMask Making

• Start with extremely clean and smooth glass plate

• Deposit a layer of chrome

• Using a laser or e-beam to draw (by removing) the desired pattern

• Use a stepper to expose the mask at every location. Extreme position accuracy is

needed!

• This sounds fairly simple. HOWEVER…

Laser/E-beam

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What Happens in Reality?What Happens in Reality?

• Illuminate mask with 193nm wavelength light (UV)

• Consider the result for various sizes of patterns

• The feature sizes are much smaller than the wavelength of the light diffraction destroys the pattern

0.25µ 0.18µ

0.13µ 90-nm 65-nm

Mask

Source: Synopsys Inc.

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What is going on?What is going on?

• Assume we use 193nm coherent (laser) light

• Assume a simplistic photo-resist model Simple threshold model

• If we plot the intensity and resist response for a single small opening in the mask for a typical manufacturing lens configuration, we get:

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What is going on? Part 2What is going on? Part 2

• With two holes we get:

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In More DetailIn More Detail

• Plotting the electrical field as well:

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Potential SolutionsPotential Solutions

• Reduce the wavelength of the light Extreme-UV (13.5nm) is being explored

using reflective optics and reflective masks- Incredibly complex and expensive process

• Increase the refractive index Immersion lithography (optics in water)

- Adds complexity

• Change what you try to pattern Make a mask that after exposure yields

the desired pattern on silicon wafer Some approaches:

- Optical proximity correction

- Phase shifting masks

- Immersion lithography

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Using “Optical Tricks”Using “Optical Tricks”

• With two holes, but using opposite phase, we get:

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Symbolic FormulationSymbolic Formulation

• The intensity is proportional to the square of the electric field

• The individual contributions to the electric field are linear.• Every pixel with the same distance to the target contribute

the same amount• To avoid having to use large precision (many bits) or floating

point representation, a “quantization” approach works well. Each pixel at a specific distance can contribute a fixed (integer)

number of units of electric field. Adding up all the positive/negative contributions to the electric

field, translate into simply counting the number of positive and negative quanta

Rather than squaring the result and then threshold it for the resist, use a magnitude function instead.

• Past a certain distance, the contribution to the electrical field is small enough to be ignored.

Thus dependency between variables is limited (but still large)

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1-Dimensional Example:1-Dimensional Example:

If we want the pattern:

we can use the mask:

which yields:

30nm

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Lessons and Future WorkLessons and Future Work

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ObservationsObservations

• Four major questions: Which level of abstraction?

- All levels seem amenable to formal methods Which question is to be answered?

- Find a (good) solution C+

- Find the best solution B+

- Make sure all cases satisfies something A

- Characterize the viable design space A+ Which encoding should be used?

- Bit-level or word level Not clear…

- Arithmetic encoding: binary, unary, … Which formal method should be applied?

- BDDs, SAT, SMT, … Depends on question and size

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Future WorkFuture Work

• Explore usage of combining formal/symbolic methods with more traditional search algorithms Symbolic methods often only choice when highly

“disjunctive” problems and/or few solutions For subspaces, a traditional search algorithm

often beats symbolic methods

• Symbolic representations for dynamic programming algorithms

• Experiment, experiment, experiment

• Watch out for: “Has hammer. Looking for nail.”

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So What is It?So What is It?

Match Made in Heaven

Fool’s Paradise?

or

Time Will Tell

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Questions?Questions?