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N° d'ordre: 2010-ISAL-0112 Année 2010

THESE

présentée

devant l'Institut National des Sciences Appliquées de Lyon

pour obtenir

LE GRADE DE DOCTEUR

Ecole Doctorale: Electronique Electrotechnique Automatique

Formation Doctorale: Composants et Systemes Electriques

par

Malal Bathily

Ingénieur INSA GE, Lyon

Master GEGP DEI, INSA Lyon

Design of DC/DC converters

for RF Systems-on-Chip

Soutenue le: 14 décembre 2010 devant la Commission d'examenJury:

Corinne Alonso, Professeur des Universités (Université de Toulouse) - Présidente

Yves Lembeye, Professeur des Universités (INP Grenoble) - Rapporteur

José Antonio Cobos, Professeur (Université de Madrid) - Rapporteur

Frédéric Hasbani, Ingénieur (STMicroelectronics, Crolles) - Encadrant

Bruno Allard, Professeur des Universités (INSA Lyon) - Directeur de thèse

Cette thèse a été préparée conjointement à STMicroelectronics Crolles et

au Laboratoire Ampère, CNRS UMR 5005, INSA Lyon

Cette thèse est accessible à l'adresse : http://theses.insa-lyon.fr/publication/2010ISAL0112/these.pdf © [M. Bathily], [2013], INSA de Lyon, tous droits réservés

INSA Direction de la Recherche INSA Direction de la Recherche INSA Direction de la Recherche INSA Direction de la Recherche ---- Ecoles Doctorales Ecoles Doctorales Ecoles Doctorales Ecoles Doctorales –––– Quadriennal Quadriennal Quadriennal Quadriennal 2007200720072007----2010201020102010

SIGLE ECOLE DOCTORALE NOM ET COORDONNEES DU RESPONSABLE

CHIMIE

CHIMIE DE LYON http://sakura.cpe.fr/ED206

M. Jean Marc LANCELIN

Insa : R. GOURDON

M. Jean Marc LANCELIN Université Claude Bernard Lyon 1 Bât CPE 43 bd du 11 novembre 1918 69622 VILLEURBANNE Cedex Tél : 04.72.43 13 95 Fax : [email protected]

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Insa : H. CHARLES

M. Jean-Pierre FLANDROIS CNRS UMR 5558 Université Claude Bernard Lyon 1 Bât G. Mendel 43 bd du 11 novembre 1918 69622 VILLEURBANNE Cédex Tél : 04.26 23 59 50 Fax 04 26 23 59 49 06 07 53 89 13 [email protected]

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INFOMATHS

INFORMATIQUE ET MATHEMATIQUES http://infomaths.univ-lyon1.fr M. Alain MILLE

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MEGA

MECANIQUE, ENERGETIQUE, GENIE CIVIL, ACOUSTIQUE M. Jean Louis GUYADER

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ScSo

ScSo* M. OBADIA Lionel

Insa : J.Y. TOUSSAINT

M. OBADIA Lionel Université Lyon 2 86 rue Pasteur 69365 LYON Cedex 07 Tél : 04.78.69.72.76 Fax : 04.37.28.04.48 [email protected]

*ScSo : Histoire, Geographie, Aménagement, Urbanisme, Archéologie, Science politique, Sociologie, Anthropologie


Abstract

Today's mobile communication devices include many features and deliver data with high

rates. In order to increase the life time of the battery, it is necessary to enhance each block

eciency, i.e. to provide and to design ecient power management system to deliver energy

to the dierent parts of the device. The RF power amplier (PA) that feeds the antenna is

the main power consumer on a mobile platform. The Envelope Elimination and Restoration

(EER) technique constitutes an interesting approach to increase the eciency of the RF

PA when variable-envelope modulations such as WCDMA or WLAN are used. A DC/DC

converter with a large bandwidth is then required to supply the PA with the envelope of the

RF signal.

This PhD work focuses on the design of high switching frequency DC/DC converters for

WCDMA EER. Besides the monolithic integration of the converter and the RF PA on a

single chip requires an increase of the switching frequency beyond the hundred of MHz in

order to shrink the size of passive devices. A formal design methodology is developed to

specify the converter and the main building blocks of the system. This methodology derives

the specications of the converters from those of the RF standard in terms of bandwidth

and output power. New architectures are proposed to overcome the limitation of the con-

ventional architecture and to improve the eciency of the converter. The study focuses the

light output power range. A practical use of this methodology is given through the design of

demonstrators in 0.25-µm BiCMOS and 0.13-µm CMOS SOI technologies and experimental

results are provided to validate the methology and the simulation results.

Keywords: Analog circuits design, buck converter, BiCMOS, CMOS, DC/DC conversion,

EER, PWM, WCDMA, SMPS

- v -Cette thèse est accessible à l'adresse : http://theses.insa-lyon.fr/publication/2010ISAL0112/these.pdf © [M. Bathily], [2013], INSA de Lyon, tous droits réservés

Résumé

Les appareils de communication mobile actuels intègrent de plus en plus de fonctionnal-

ités et transmettent des données à des débits toujours plus élevés. Pour étendre la durée de

vie de la batterie, il est nécessaire de concevoir une bonne stratégie de gestion d'énergie et

d'alimentation des diérents circuits. L'amplicateur de puissance (PA) radio est le princi-

pal consommateur d'énergie. La technique de reconstruction d'enveloppe (Envelope Elim-

ination and Restoration) permet d'augmenter le rendement énergétique de l'amplicateur

de puissance lorsque les modulations à amplitude variable comme le WCDMA ou le WLAN

sont utilisées. Dans cette architecture un convertisseur DC/DC est utilisé pour alimenter

l'amplicateur radio avec l'enveloppe du signal RF.

Ce travail de thèse décrit la conception des convertisseurs à découpage DC/DC à haute

fréquence pour alimenter un PA dans le cadre de la reconstruction d'enveloppe pour le

standard WCDMA. De plus l'intégration monolithique du convertisseur et du PA impose

d'augmenter la fréquence de découpage du convertisseur pour réduire la taille des com-

posants passifs. Une méthodologie formelle est développée pour spécier le convertisseur et

ses principaux circuits. Cette méthodologie déduit les spécications du convertisseur à partir

de celles du standard RF, notamment en termes de bande passante et de puissance. De nou-

velles architectures sont proposées pour dépasser les limitations de l'architecture classique et

améliorer le rendement du convertisseur. L'application pratique de cette méthodologie est

eectuée à l'aide de démonstrateurs réalisés dans les technologies BiCMOS 0.25 µm et CMOS

0.13µm SOI. Les résultats expérimentaux obtenus permettent de valider la méthodologie et

conrment les résultats de simulation.

Mots-clés: Circuits intégrés analogiques, BiCMOS, CMOS, convertisseur DC/DC, EER,

PWM, WCDMA

- vii -Cette thèse est accessible à l'adresse : http://theses.insa-lyon.fr/publication/2010ISAL0112/these.pdf © [M. Bathily], [2013], INSA de Lyon, tous droits réservés

Acknowledgements

Carrying out this PhD work has been a very rich and interesting experience due in large

part to the help of many people I wish to thank here.

My thesis advisor Prof Bruno Allard has been very helpful during the project. His support

was decisive for my research activities as well as for the preparation of this manuscript and

other scientical papers. His careful reading of the manuscript allowed to nd many errors

and provided me with valuable remarks. I am also grateful for his precious advices during

the years I have been working under his supervision.

I wish to thank my supervisor at STMicroelectronics, Frédéric Hasbani for his help. This

PhD project succeeded thanks to his support and his great technical contributions.

I am grateful to Corinne Alonso for accepting to be the chairmain of the thesis evaluation

comitee and to Yves Lembeye and José Antonio Cobos for their review of the manuscript.

Thier suggestions allowed a more comprehensive presentation of the work.

Many colleagues within STMicroelectronics including Denis Pache, Alexandre Giry, Vin-

cent Pinon, Nicole Bertholet, Christian Badard and many others gave me their help and

advices during my works. I thank all.

I am grateful to my family for their unconditional help and support during my studies.

- ix -Cette thèse est accessible à l'adresse : http://theses.insa-lyon.fr/publication/2010ISAL0112/these.pdf © [M. Bathily], [2013], INSA de Lyon, tous droits réservés

Remerciements

La préparation de cette thèse, pendant trois années, a été une expérience riche et intéres-

sante qui fut rendue possible grâce à l'aide précieuse de plusieurs personnes que je tiens à

remercier ici.

Je remercie mon directeur de thèse Bruno Allard pour toute l'aide apportée pendant

cette thèse. Son soutien a été constant et déterminant durant des travaux de recherche et

lors de la rédaction d'articles scientiques et du manuscrit de thèse. Ses conseils avisés ont

toujours été utiles au cours des années durant lesquelles il m'a encadré.

Mes sincères remerciements vont à mon encadrant industriel Frédéric Hasbani qui m'a

accueilli au sein de son équipe à STMicroelectronics. Ses contributions ont été décisives et

protables pour la réussite des diérents projets mis en oeuvre au cours de la thèse. Ses

grandes qualités humaines ont beaucoup contribué au succès de notre collaboration.

Je remercie Corinne Alonso d'avoir accepté de présider le jury de thèse ainsi que Yves

Lembeye et José Antonio Cobos d'avoir accepté de rapporter mes travaux. Leurs com-

mentaires sur le manuscrit de thèse ont beaucoup aidé pour une meilleure présentation

pédagogique de l'ensemble des travaux.

A STMicroelectronics, plusieurs personnes dont Denis Pache, Alexandre Giry, Vincent

Pinon, Nicole Bertholet, Christian Badard m'ont apporté aide et conseils pour la réussite de

mes projets. Je les en remercie sincèrement. La liste est longue et mes remerciements vont

à tous.

Je remercie toute ma famille dont le soutien inconditionnel a toujours été constant et

utile pendant mes études.

- xi -Cette thèse est accessible à l'adresse : http://theses.insa-lyon.fr/publication/2010ISAL0112/these.pdf © [M. Bathily], [2013], INSA de Lyon, tous droits réservés

Résumé étendu

Cette partie propose un résumé étendu du contenu du manuscrit.

This section oers an extended summary of the manuscript content in french.

Introduction

La reconstruction d'enveloppe (Fig. 1) est une technique proposée pour réduire la con-

sommation d'énergie d'un système radiofréquence. Le signal à émettre est séparé en com-

posantes de phase et d'amplitude. La composante de phase permet la commutation d'un

amplicateur de puissance RF (PA RF) polarisé en classe saturée. La reconstruction du

signal au pied de l'antenne est obtenue par l'alimentation du PA RF à l'identique de la com-

posante d'amplitude du signal à émettre. L'amplication en puissance de cette composante

d'amplitude est assurée par un régulateur de tension à découpage directement connecté à

la batterie. Les caractéristiques du signal à émettre, par exemple le standard WCDMA

donnent des contraintes fortes de bande passante de régulation au convertisseur de tension à

découpage. Celui-ci doit fonctionner à très haute fréquence de découpage: l'impact négatif

sur le rendement en énergie doit être compensé. L'objet de la thèse est de démontrer, au

sens d'un système-sur-puce, l'application EER en explorant plusieurs techniques de gain en

rendement du convertisseur DC/DC.

Le manuscrit comprend six chapitres. L'état-de-l'art est revu vis-à-vis des liens radio pour

les standards avancés et pour les convertisseurs DC/DC à très haute fréquence de découpage.

Le deuxième chapitre décrit une méthodologie formelle de conception des convertisseurs

DC/DC et de leurs blocs constitutifs. Le troisième chapitre décrit un premier démonstrateur

de convertisseur (200 MHz, 2 W) en technologie BiCMOS 0.25 µm. Le chapitre 4 décrit une

première amélioration sous la forme d'une commande rapprochée de grille, à résonance. Le

chapitre 5 revoit rapidement la problématique de l'intégration des composants passifs. Le

chapitre 6 décrit un démonstrateur de système-sur-puce ainsi que deux autres techniques

d'amélioration du rendement du convertisseur DC/DC.

- xiii -Cette thèse est accessible à l'adresse : http://theses.insa-lyon.fr/publication/2010ISAL0112/these.pdf © [M. Bathily], [2013], INSA de Lyon, tous droits réservés

Résumé étendu

Chapitre 1

La littérature décrit plusieurs techniques permettant d'augmenter l'écacité énergétique

de l'étage d'émission RF. On retient en particulier la technique dite d'élimination et de

restauration d'enveloppe (EER). Les principales caractéristiques à retenir pour les princi-

paux standards sont reportées dans le tableau 1.1; ces caractéristiques sont les principales

contraintes du convertisseur DC/DC, objet de l'étude. Les meilleurs résultats en terme de

transmetteurs radiofréquence sont mis en perspective dans le tableau 1.2. L'état-de-l'art est

ensuite utilisé pour justier l'architecture du convertisseur DC/DC haute fréquence retenue

pour la suite. Le tableau 1.3 résume les principaux résultats établis pour de tels convertis-

seurs.

Chapitre 2

Une méthodologie de conception de convertisseurs DC/DC à haute fréquence de dé-

coupage est proposée dans ce chapitre. Elle consiste à dériver les spécications du conver-

tisseur DC/DC et de ses blocs principaux de celles du standard radio. Ainsi la puissance

fournie par le convertisseur DC/DC et l'impédance de charge sont obtenues à partir de la

puissance radio émisse par l'antenne et le rendement du convertisseur (éq. 2.1 et 2.4). Les

spécications pour les standards CDMA200, WCDMA et IEEE 802.11g WLAN sont réportés

dans le tableau 2.1.

Le choix de la fréquence de commutation et de la caractéristique fréquentielle du conver-

tisseur en boucle fermée se fait en prenant en compte leur impact sur le spectre du signal

radio émis. Les valeurs proposées pour les trois standards précédents sont indiquées dans le

tableau 2.2 et sont plus optimales que celles fournies par une méthode empirique.

Le comportement fréquentiel du controleur est dérivé de la bande passante de régulation

exigée tandis que la taille des transistors de l'étage de puissance est dérivée du courant

maximal fourni. L'optimisation de la taille ainsi que la commande de l'étage sont des points

importants pour optimiser le rendement du convertisseur DC/DC. Pour cela, outre l'éq. 2.21

qui donne la largeur optimale des transistors de puissance, un contrôle adaptatif du temps-

mort est proposé an de réduire les pertes d'énergie dûe à la conduction de la body-diode du

transistor synchrone.

L'analyse du rendement théorique du convertisseur est éectuée à partir d'une modélisa-

tion de l'ensemble des pertes d'énergie intrinsèques au convertisseur (éqs. 2.33, 2.34 et 2.36).

Cette analyse permet d'estimer en particulier le rendement maximal atteignable compte-tenu

de la puissance mise en jeu et de la technoologie utilisée (éq. 2.37). Elle conrme également

l'avantage des noeuds technologiques CMOS submicroniques sur les technologies CMOS de

plus grande géométrie.

- xiv -Cette thèse est accessible à l'adresse : http://theses.insa-lyon.fr/publication/2010ISAL0112/these.pdf © [M. Bathily], [2013], INSA de Lyon, tous droits réservés

Résumé étendu

Chapitre 3

La méthodologie formelle développée au chapitre 2 est appliquée pour concevoir et réaliser

un convertisseur DC/DC en technology BiCMOS 0.25 µm dans le cadre de la reconstruction

d'envelope avec le standard WCDMA.

Les diérentes parties du contrôleur et de l'étage de puissance sont conçues pour répon-

dre aux spécications indiquées dans le tableau 3.1. Une fréquence de découpage élévée

(200 MHz) a été choisie an de réduire la taille des composants passifs. Les transistors de

puissance sont réalisés avec des transistors à Extension de drain (NLDEMOS) capables de

supporter une tension batterie (5 V max.).

Le layout et l'assemblage sont éectués en minimisant les éléments parasites, notamment

les résistances des lignes d'interconnection qui peuvent abaisser le rendement.

Le circuit ainsi réalisé (Fig. 3.24) est testé en substituant une résistance de 5.6 Ω sur le

PCB à l'amplicateur de puissance. L'analyse du rendement mesuré indique un bon accord

avec les résultats de simulation.

Le rendement à faible charge est fortement inuencé par les pertes d'énergie par com-

mutation qui sont proportionnelles à la fréquence de découpage. Il est donc important de

mettre en oeuvre des techniques pour compenser cette réduction du rendement à faible charge

lorsqu'on veut travailler avec des fréquences de découpage élevées.

Chapitre 4

Une structure de driver appélé driver résonnant (Fig. 4.3) est proposée an de réduire

les pertes d'énergie par commutation dans l'étage de puissance et de compenser la baisse

de rendement à faible charge. L'approche utilisée consiste à eectuer la commutation de

la grille des transistors par l'intermédiaire d'un circuit LC, puis de restituer à la source

d'alimentation l'énergie stockée dans l'inductance et dans la capacité de grille. Comparé à

un driver conventionnel, le driver résonnant permet d'économiser en partie l'énergie utilisée

pour la commutation de l'étage de puissance. Toutefois sa conception exige une prise en

compte de ses propres pertes d'énergie qui sont répertoriées dans le tableau 4.1. Un modèle

décrit par l'éq. 4.7 est établi an d'estimer la réduction des pertes par commutation obtenue

avec le driver résonnant comparé à un driver conventionnel.

Un démonstrateur (Fig. 4.16) est réalisé en technologie BiCMOS 0.25 µm avec, un

convertisseur DC/DC standard et un convertisseur DC/DC utilisant le driver résonnant,

pour valider le modèle et prouver l'intérêt du driver résonnant. Les résultats de mesure

concordent bien avec ceux de la simulation et les predictions du modèle théorique.

- xv -Cette thèse est accessible à l'adresse : http://theses.insa-lyon.fr/publication/2010ISAL0112/these.pdf © [M. Bathily], [2013], INSA de Lyon, tous droits réservés

Résumé étendu

Chapitre 5

Les composants passifs occupent une place importante dans la performance des conver-

tisseurs DC/DC à découpage. Leur intégration dans le même boitier que la partie active

du convertisseur constitue un des objectifs majeurs pour la réalisation de systèmes ecaces

de gestion d'énergie. Ce chapitre explore quelques techniques utilisées dans la littérature

pour réaliser des inductances et des capacités de forte densité, bien que la fabrication de

composants passifs ne fasse pas partie des objectifs de la thèse.

Les contraintes sur les composants passifs utilisés dans le ltre de sortie du convertis-

seur DC/DC sont d'abord présentés ainsi que l'impact de leurs éléments parasites. Pour

l'inductance cela concerne notamment sa resistance série qui peut contribuer à abaisser sig-

nicativement le rendement du convertisseur. Ensuite quelques techniques permettant de

réaliser une inductance avec un noyau magnétique sont présentées avec des prototypes réal-

isés.

La conception de capacités 3D est présentée dans la deuxième partie du chapitre. Des

densités élevées sont réportées dans les travaux citées et permettent la fabrication de capac-

ités de fortes valeurs. Les éléments sont cependant assez importants comparés à ceux d'une

capacité discrète et limitent la plage d'utilisation en fréquence.

Chapitre 6

Deux techniques sont proposées dans ce chapitre pour améliorer le rendement du conver-

tisseur DC/DC à haute fréquence de découpage: l'abaissement de la tension d'alimentation

des drivers et l'ajustement dynamique de la taille des transistors de puissance suivant la

puissance de sortie. La combinaison de ces deux techniques permet de réduire davantage les

pertes d'énergie par commutation lorsque la puissance de sortie devient faible.

Le chapitre décrit les circuits mis en oeuvre pour réaliser cet ajustement dynamique

ainsi qu'une nouvelle implémentation du contrôle adaptatif de temps-mort. Des régulateurs

linéarires sont également réalisés an d'alimenter le contrôleur et les drivers à partir de la

tension de batterie.

L'ensemble est réalisé en technologie 0.13-µm CMOS SOI avec un amplicateur de puis-

sance RF WLAN. Les résultats des mesures, en cours, ne sont pas disponibles à la date de

soumission de ce manuscrit.

Conclusion

Ce travail présente une méthodologie pour la spécication et la réalisation d'un convertis-

seur DC/DC HF pour la reconstruction d'enveloppe. De nouvelles techniques sont proposées

- xvi -Cette thèse est accessible à l'adresse : http://theses.insa-lyon.fr/publication/2010ISAL0112/these.pdf © [M. Bathily], [2013], INSA de Lyon, tous droits réservés

Résumé étendu

an d'améliorer les performances du convertisseur. Ces techniques sont ensuite validées à

l'aide de démonstrateur réalisés et testés.

L'approche suivie, notamment pour l'amélioration du rendement peut servir dans d'autres

types d'application de gestion d'énergie comme le Dynamic Voltage Scaling (DVS) pour

réduire la consommation d'énergie des circuits numériques.

Une étude des problèmes de compatibilité électromagnétique peut justement compléter

ce travail.

- xvii -Cette thèse est accessible à l'adresse : http://theses.insa-lyon.fr/publication/2010ISAL0112/these.pdf © [M. Bathily], [2013], INSA de Lyon, tous droits réservés

Résumé étendu

- xviii -Cette thèse est accessible à l'adresse : http://theses.insa-lyon.fr/publication/2010ISAL0112/these.pdf © [M. Bathily], [2013], INSA de Lyon, tous droits réservés

Contents

Abstract v

Résumé vii

Acknowledgements ix

Remerciements xi

Résumé étendu xiii

List of gures xxix

List of tables xxxi

Glossary xxxiii

Introduction 1

1 State-of-the-art of wideband radio transmitters and DC/DC converters 5

1.1 Wideband radio transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1.1 Digital modulation of RF signals . . . . . . . . . . . . . . . . . . . . 5

1.1.2 Architectures of radio transmitters . . . . . . . . . . . . . . . . . . . 6

1.1.2.1 Typical radio transmitters . . . . . . . . . . . . . . . . . . . 6

1.1.2.2 Doherty power amplier . . . . . . . . . . . . . . . . . . . . 7

1.1.2.3 Envelope tracking (ET) . . . . . . . . . . . . . . . . . . . . 7

1.1.2.4 Envelope Elimination and Restoration (EER) . . . . . . . . 8

1.1.2.5 Supply modulator . . . . . . . . . . . . . . . . . . . . . . . 9

1.1.2.6 Multiple standard capability . . . . . . . . . . . . . . . . . . 11

1.1.2.7 Conclusion of the state-of-the-art of wideband transmitters . 11

1.2 Trends in HF DC/DC converters design . . . . . . . . . . . . . . . . . . . . 12

1.2.1 Types of DC/DC converters . . . . . . . . . . . . . . . . . . . . . . . 12

1.2.1.1 Linear regulator . . . . . . . . . . . . . . . . . . . . . . . . 12

1.2.1.2 Switched-capacitor converter . . . . . . . . . . . . . . . . . 13

- xix -Cette thèse est accessible à l'adresse : http://theses.insa-lyon.fr/publication/2010ISAL0112/these.pdf © [M. Bathily], [2013], INSA de Lyon, tous droits réservés

CONTENTS

1.2.1.3 Inductive SMPS . . . . . . . . . . . . . . . . . . . . . . . . 13

1.2.2 Principle of operation of a buck converter . . . . . . . . . . . . . . . 13

1.2.2.1 Spurious emission . . . . . . . . . . . . . . . . . . . . . . . . 14

1.2.2.2 Power loss mechanisms . . . . . . . . . . . . . . . . . . . . . 15

1.2.3 Architectures of high frequency buck converter . . . . . . . . . . . . . 16

1.2.3.1 Multiphase interleaved buck converter . . . . . . . . . . . . 16

1.2.3.2 Cascode power stage . . . . . . . . . . . . . . . . . . . . . . 17

1.2.4 Control method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.2.4.1 Feedback loop . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.2.4.2 Power stage switching . . . . . . . . . . . . . . . . . . . . . 19

1.2.5 Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.2.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2 Design methodology 23

2.1 Specications of the SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.1.1 Power specications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.1.1.1 Output voltage and load current ranges . . . . . . . . . . . 25

2.1.2 Control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.1.2.1 Frequency response . . . . . . . . . . . . . . . . . . . . . . . 26

2.1.2.2 Switching frequency selection method . . . . . . . . . . . . . 28

2.1.2.3 High frequency PWM noise . . . . . . . . . . . . . . . . . . 30

2.2 Circuit optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.2.1 Controller and output lter . . . . . . . . . . . . . . . . . . . . . . . 31

2.2.1.1 Linear model of the buck converter . . . . . . . . . . . . . . 31

2.2.1.2 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.2.2 Power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.2.2.1 Power switches size . . . . . . . . . . . . . . . . . . . . . . . 35

2.2.2.2 Power switches drivers . . . . . . . . . . . . . . . . . . . . . 36

2.2.3 Impact of the increase of switching frequency . . . . . . . . . . . . . 37

2.2.3.1 Impact of the increase of switching frequency on the control

circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.2.3.2 Impact of the increase of switching frequency on the power

stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.2.4 Adaptive dead-time control . . . . . . . . . . . . . . . . . . . . . . . 38

2.2.4.1 Optimization of dead-time td2 . . . . . . . . . . . . . . . . . 39

2.2.4.2 Optimization of dead-time td1 . . . . . . . . . . . . . . . . . 41

2.2.4.3 Power transistors control signals . . . . . . . . . . . . . . . 41

2.2.5 Eciency analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.3 Methodology summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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CONTENTS

3 Design of the SMPS in CMOS 45

3.1 Preliminary optimization for WCDMA standard . . . . . . . . . . . . . . . . 45

3.2 Control circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.2.1 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.2.1.1 Operational amplier . . . . . . . . . . . . . . . . . . . . . . 47

3.2.1.2 Stability analysis . . . . . . . . . . . . . . . . . . . . . . . . 48

3.2.2 Pulse width modulator (PWM) . . . . . . . . . . . . . . . . . . . . . 50

3.2.2.1 Ramp signal generator . . . . . . . . . . . . . . . . . . . . . 50

3.2.2.2 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.3 Dead-time controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.4 Power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.4.1 Power transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.4.2 Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.4.3 Boostrap supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.4.4 Voltage level-shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.5 Assembling and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.5.1 Blocks placement and layout . . . . . . . . . . . . . . . . . . . . . . . 57

3.5.2 Ground planes connection . . . . . . . . . . . . . . . . . . . . . . . . 57

3.5.3 Decoupling method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.5.4 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.6 Top-level simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.6.1 Eciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.6.2 Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.6.3 Duty cycle and output voltage range . . . . . . . . . . . . . . . . . . 63

3.7 Measurements results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.7.1 Measurements setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.7.2 Steady-state measurements . . . . . . . . . . . . . . . . . . . . . . . . 67

3.7.3 Dynamic measurements . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.7.4 Reference tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.7.5 Measured eciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.7.5.1 Eciency variation with battery voltage . . . . . . . . . . . 71

3.7.5.2 Power dissipation breakdown . . . . . . . . . . . . . . . . . 72

3.7.6 Parasitics extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.7.6.1 Resistance extraction . . . . . . . . . . . . . . . . . . . . . . 73

3.7.6.2 Capacitance extraction . . . . . . . . . . . . . . . . . . . . . 74

3.8 Discussion and conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.8.1 Eciency improvement . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.8.2 Comparison with previous works . . . . . . . . . . . . . . . . . . . . 76

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CONTENTS

4 Resonant gate drivers 79

4.1 Fundamentals of the resonant gate driver . . . . . . . . . . . . . . . . . . . . 79

4.1.1 State-of-the-art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.1.2 Principle of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.2 Design of the resonant gate driver . . . . . . . . . . . . . . . . . . . . . . . . 83

4.2.1 Modeling of the power losses . . . . . . . . . . . . . . . . . . . . . . . 83

4.2.2 Comparison with a conventional driver . . . . . . . . . . . . . . . . . 84

4.2.3 Duty range and switching frequency limitation . . . . . . . . . . . . . 86

4.3 Test-chip design and optimization . . . . . . . . . . . . . . . . . . . . . . . . 87

4.3.1 Optimization of the resonant inductor . . . . . . . . . . . . . . . . . 87

4.3.2 Control of the switches of the driver . . . . . . . . . . . . . . . . . . . 88

4.3.3 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.3.3.1 Layout of the resonant inductor . . . . . . . . . . . . . . . . 90

4.3.3.2 Assembly of the buck converter . . . . . . . . . . . . . . . . 91

4.3.4 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.3.4.1 Relative eciency of the resonant gate driver . . . . . . . . 92

4.3.4.2 Output voltage range and regulation bandwidth . . . . . . . 92

4.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94



4.4.3 Eciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

4.5 Discussion and conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

5 Integrated passive devices for power management systems 99

5.1 State-of-the-art of integrated inductors . . . . . . . . . . . . . . . . . . . . . 100

5.1.1 Requirements on the output inductor in a HF DC/DC converter . . . 100

5.1.2 Integrated inductors with a magnetic core . . . . . . . . . . . . . . . 102

5.1.2.1 Fabrication of magnetic cores . . . . . . . . . . . . . . . . . 102

5.1.2.2 Parasitic eects in integrated inductors with a magnetic core 104

5.1.3 Comparison of dierent techniques . . . . . . . . . . . . . . . . . . . 105

5.2 State-of-the-art of integrated capacitors . . . . . . . . . . . . . . . . . . . . . 105

5.2.1 Trench capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

5.2.2 Electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . 107

5.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

6 Improvement of the eciency at low output power 109

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

6.2 Design of the control of the SMPS . . . . . . . . . . . . . . . . . . . . . . . . 110

6.2.1 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

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CONTENTS

6.2.2 PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

6.3 Design of the power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

6.3.1 Low voltage swing operation of the drivers . . . . . . . . . . . . . . . 112

6.3.2 Dynamic sizing of the power transistors . . . . . . . . . . . . . . . . . 112

6.3.2.1 Combination with the resonant gate driver . . . . . . . . . . 114

6.3.2.2 Design of the dynamic sizing controller . . . . . . . . . . . . 114

6.3.3 Drivers and power transistors . . . . . . . . . . . . . . . . . . . . . . 115

6.3.4 Digital dead-time controller . . . . . . . . . . . . . . . . . . . . . . . 116

6.3.4.1 Discretization of the delay . . . . . . . . . . . . . . . . . . . 117

6.3.4.2 Circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . 117

6.4 Internal power management . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

6.4.1 LDO for low power circuits . . . . . . . . . . . . . . . . . . . . . . . . 120

6.4.2 LDOs for drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

6.5 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

6.5.1 Transient performance . . . . . . . . . . . . . . . . . . . . . . . . . . 122

6.5.1.1 Dynamic width sizing of the power transistors . . . . . . . . 122

6.5.1.2 Adaptive dead-time control . . . . . . . . . . . . . . . . . . 122

6.5.2 Eciency analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

6.6 Assembling and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

6.7 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126



6.7.3 Reference tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

6.7.4 Experimental eciency . . . . . . . . . . . . . . . . . . . . . . . . . . 132

6.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Conclusion 135

Bibliography 139

List of publications 145

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CONTENTS

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List of Figures

1 Envelope Elimination and Restoration (EER) diagram . . . . . . . . . . . . 2

1.1 A typical radio transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2 Doherty power amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3 Envelope tracking PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.4 EER transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.5 Digital PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.6 Linear drop-out regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.7 Switched-capacitor DC/DC converter . . . . . . . . . . . . . . . . . . . . . . 13

1.8 Buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1.9 Typical waveforms of a buck converter . . . . . . . . . . . . . . . . . . . . . 14

1.10 Buck converter with parasitic components . . . . . . . . . . . . . . . . . . . 15

1.11 Multiphase interleaved buck converter . . . . . . . . . . . . . . . . . . . . . . 17

1.12 Buck converter with cascode power stage . . . . . . . . . . . . . . . . . . . . 18

1.13 Digital PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.14 3D-stack of active and passive dies . . . . . . . . . . . . . . . . . . . . . . . 20

2.1 CDMA probability density function (PDF) in urban and suburban areas, and

class-E PA eciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.2 WCDMA envelope in time domain . . . . . . . . . . . . . . . . . . . . . . . 25

2.3 Closed-loop buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.4 WCDMA envelope and RF spectra . . . . . . . . . . . . . . . . . . . . . . . 27

2.5 WLAN RF spectrum for modulator bandwidth f 0 equal to one, two and four

times the channel bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.6 PWM spectrum for single tone modulation at 200 MHz switching frequency 29

2.7 Linear model of the buck converter . . . . . . . . . . . . . . . . . . . . . . . 31

2.8 Pulse width modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.9 Poles and zeros placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.10 Bode diagram of the controller, the open-loop and the closed-loop transfer

function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.11 Nyquist diagram of the open-loop transfer function . . . . . . . . . . . . . . 35

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LIST OF FIGURES

2.12 Ohmic, switching and total power losses variation with the width . . . . . . 36

2.13 Gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.14 Power dissipation due to the dead-time . . . . . . . . . . . . . . . . . . . . . 38

2.15 Variation of the discharge time of CLX with load current . . . . . . . . . . . 39

2.16 Contribution of the body diode conduction losses as a function of switching

frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.17 Dead-time control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

2.18 CMOS technologies eciency comparison for Vout=1 V and Iout=500 mA . 43

2.19 Eciency drop due to switching frequency increase . . . . . . . . . . . . . . 43

3.1 Block-diagram of the SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.2 PID controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.3 Bode diagram of the operational amplier and the actual controller . . . . . 48

3.4 Folded-cascode amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.5 Linear model used for the stability analysis . . . . . . . . . . . . . . . . . . . 49

3.6 Open-loop transfer function of the main loop . . . . . . . . . . . . . . . . . . 50

3.7 Nyquist diagram of the open-loop transfer function . . . . . . . . . . . . . . 50

3.8 Ramp generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.9 PWM comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.10 Delay cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.11 Transconductance amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.12 Cross section view of a NLDEMOS designed in ST 's 0.25-µm BiCMOS . . . 54

3.13 Boostrap supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.14 Schematic of the voltage level-shifter . . . . . . . . . . . . . . . . . . . . . . 56

3.15 Layout of the SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.16 Ground planes connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.17 Simulation of the internal supply voltage spikes without an on-chip decoupling 59

3.18 Decoupling network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.19 Simulation with layout and PCB parasitic eects . . . . . . . . . . . . . . . 62

3.20 Simulated eciency of the buck converter for a 6 Ω load resistance and

Vbat=3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.21 Simulated frequency response of the SMPS . . . . . . . . . . . . . . . . . . . 64

3.22 WCDMA envelope tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.23 Simulated output voltage range without pulse-skipping (Vout is top and Vref

is bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.24 Measurements board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.25 Input clock (200 MHz) and resulting LX voltage in open-loop condition . . . 68

3.26 Measured output voltage range using a 1 kHz sawtooth reference voltage . . 68

3.27 Reduction of the dead-time with the implemented control . . . . . . . . . . . 69

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LIST OF FIGURES

3.28 Output voltage for a 2 MHz sine reference signal . . . . . . . . . . . . . . . . 70

3.29 Spectrum of the output voltage for a 2 MHz and 411 mVpp sine voltage . . . 70

3.30 Comparison of measured and simulated eciencies (Vbat=3.6 V) . . . . . . 72

3.31 Corrected eciency for dierent battery voltages . . . . . . . . . . . . . . . . 72

3.32 Breakdown of the total power loss (Ploss) of the SMPS with Vbat=3.6 V . . 73

3.33 Test bench designed for parasitic resistance extraction . . . . . . . . . . . . . 74

3.34 Variation of gate drive losses vs. the switching frequency . . . . . . . . . . . 75

4.1 Charge and discharge of a gate equivalent capacitance . . . . . . . . . . . . . 80

4.2 Resonant gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.3 Proposed resonant gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.4 Waveforms of the proposed resonant gate driver . . . . . . . . . . . . . . . . 82

4.5 Conduction diagram of driver's components . . . . . . . . . . . . . . . . . . 84

4.6 Relative eciency of the resonant gate driver vs. the conventional driver . . 86

4.7 Relative eciency of the resonant gate driver vs. the switching frequency . . 87

4.8 Rise/fall time of the gate voltage of the power transistor . . . . . . . . . . . 88

4.9 Eciency and gate voltage rise/fall time for 17 pF of gate capacitance . . . . 89

4.10 Control signals of M1-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.11 Resonant inductor with shielding . . . . . . . . . . . . . . . . . . . . . . . . 91

4.12 Layout of the buck converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.13 Switching losses and the reduction due to resonant gate drivers . . . . . . . . 92

4.14 Simulated eciencies comparison . . . . . . . . . . . . . . . . . . . . . . . . 93

4.15 A 4-MHz sine-wave reference tracking . . . . . . . . . . . . . . . . . . . . . . 93

4.16 Microphotograph of the test-chip . . . . . . . . . . . . . . . . . . . . . . . . 94

4.17 Overshoot on the output voltage of the power stage . . . . . . . . . . . . . . 95

4.18 Dead-time obtained at both transitions of LX voltage . . . . . . . . . . . . . 95

4.19 Dead-time in low output current condition . . . . . . . . . . . . . . . . . . . 96

4.20 Switching losses comparison at low to medium output power for Vbat=3.6 V 97

4.21 Eciency comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.1 Surface-mounted devices (SMD) used in power management . . . . . . . . . 100

5.2 A simple model of inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

5.3 Breakdown of the power losses for a 200 MHz SMPS . . . . . . . . . . . . . 101

5.4 SiP approach to assembly active and passive chips . . . . . . . . . . . . . . . 102

5.5 Micro-inductor with a magnetic core from Tyndall Lab. . . . . . . . . . . . . 103

5.6 Sandwiched magnetic core inductor (Credit: B. Orlando [1]) . . . . . . . . . 103

5.7 Process steps for the fabrication of the inductor with a YIG core (Credit:

Martin[2]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

5.8 A generic design-ow for trench capacitors . . . . . . . . . . . . . . . . . . . 107

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LIST OF FIGURES

5.9 Trench capacitor in PICS technology (Credit: NXP[3]) . . . . . . . . . . . . 107

5.10 PICS capacitor with 3 MIM layers: dielectric and electrode stack (a), the

multilayer capacitor (b) (Credit: Klootwijk[4]) . . . . . . . . . . . . . . . . . 108

6.1 Controller circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

6.2 PWM comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

6.3 Channel resistance of a NLDEMOS as a function of gate-source voltage with

W=7 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

6.4 Multiple transistors forming a single power device . . . . . . . . . . . . . . . 113

6.5 Simulated eciency of a conventional SMPS and a dynamic width sizing

SMPS (Vbat=3.6 V and Rload=6 Ω) . . . . . . . . . . . . . . . . . . . . . . . 114

6.6 Schematic of the dynamic width sizing controller . . . . . . . . . . . . . . . . 115

6.7 Hysteresis and voltage shift of the dynamic width sizing controller . . . . . . 116

6.8 Relative eciency and rise/fall time of the resonant gate driver for a gate

capacitance of 8.5 pF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

6.9 Discharge time of the capacitance at the LX node as a function of the output

current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

6.10 Block diagram of the dead-time controller . . . . . . . . . . . . . . . . . . . 118

6.11 Dead-time selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

6.12 Delay cell of the dead-time controller . . . . . . . . . . . . . . . . . . . . . . 119

6.13 Single LDO for on-chip power management . . . . . . . . . . . . . . . . . . . 120

6.14 Multiple LDOs for a separate supply of analog and digital circuits . . . . . . 120

6.15 LDO used for the power supply of analog and low power digital circuits . . . 121

6.16 The two LDOs designed for the supply of the drivers . . . . . . . . . . . . . 122

6.17 Block-diagram of the SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

6.18 Width selection signal variation with the output voltage of the converter . . 123

6.19 Variation of the dead-time with the output voltage and the control signals of

the power transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

6.20 Simulated eciency of the converter without the dynamic width sizing and

with the dynamic width sizing . . . . . . . . . . . . . . . . . . . . . . . . . . 125

6.21 Simulated eciency of the SMPS and an LDO for Vbat=3.6 V and RPA=6 Ω 125

6.22 Layout and oor plan of the test-chip (the SMPS with a RF PA) . . . . . . . 127

6.23 Test board and chip microphotograph . . . . . . . . . . . . . . . . . . . . . . 128

6.24 LX node voltage for Vbat=3.6 V (200 MHz) . . . . . . . . . . . . . . . . . . 128

6.25 Dynamic sizing of the size of the power stage: control signal vs. the output

voltage at 100 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

6.26 Adaptive dead-time: dead-time selection signals vs. output voltage . . . . . 129

6.27 Measured dead-times at dierent output voltage . . . . . . . . . . . . . . . . 130

6.28 Reference tracking at dierent input signal frequencies . . . . . . . . . . . . 131

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LIST OF FIGURES

6.29 Comparison of measured eciency and input current from the battery vs.

simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

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LIST OF FIGURES

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List of Tables

1.1 Power and bandwidth requirements of modern standards . . . . . . . . . . . 10

1.2 Wideband radio transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3 Recent works on HF DC/DC converters . . . . . . . . . . . . . . . . . . . . 21

2.1 PA equivalent resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.2 Optimum switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.1 Buck converter specications for WCDMA standard . . . . . . . . . . . . . . 46

3.2 Performance summary of the SMPS . . . . . . . . . . . . . . . . . . . . . . . 76

3.3 Comparison with previous works . . . . . . . . . . . . . . . . . . . . . . . . . 77

4.1 Resonant gate driver's power dissipation . . . . . . . . . . . . . . . . . . . . 84

4.2 Logic equations and size of switches M1-4 . . . . . . . . . . . . . . . . . . . 90

4.3 Performance summary of the buck converter using resonant gate drivers . . . 98

5.1 Comparison of integrated power inductors with a discrete inductor . . . . . . 106

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LIST OF TABLES

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Glossary

ASK Amplitude Shift Keying

EDGE Enhanced Data Rate for GSM Evolution

EER Envelope Elimination and Restoration

EMI Electromagnetic Interference

ET Envelope Tracking

EVM Error Vector Magnitude

FSK Frequency Shift Keying

GBW Gain Bandwidth product

GSM Global System for Mobile communication

LDO Linear Drop-Out regulator

MIM Metal Insulator Metal capacitor

OFDM Orthogonal Frequency Division Multiplex

PAPR Peak to Average Power Ratio

PCB Printed Circuit Board

PFM Pulse Frequency Modulation

PID Proportional Integral Derivative

PSK Phase Shift Keying

PWM Pulse Width Modulation

QAM Quadrature Amplitude Modulation

SiP System-in-Package

SMPS Switched-Mode Power Supply

SoC System-on-Chip

WCDMA Wideband Code Division Multiple Access

WiMAX Worldwide Interoperability for Microwave Access

WLAN Wireless Local Area Network

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Glossary

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Introduction

Portable devices take a more and more important position in our daily life. From mobile

phones to smart phones or MP3 players they constitute a great market for the semiconductor

industry. The interest of the public is motivated by the great number of functions available

on these devices and also by their smaller and smaller sizes. The integration of multiple

chips in small device size is possible thanks to the shrink of the CMOS technology nodes.

The radiofrequency communication as one main function of the mobile handsets, is con-

tinuously improving from the basic voice communication to the high data rate services like

the TV reception. The communication standards have evolved from earlier generations

(GSM) to the 3rd (UMTS) and 4th (WiMAX) generations and oer now more data rates.

On the motherboard of a mobile handset a large number of transmission and reception chains

corresponding to the various standards exist together like the GSM-EDGE, the WCDMA,

the Bluetooth, the WiFi, etc. The appropriate operation of these multiple communication

standards is handled by high performance Digital Signal Processors (DSP) and microproces-

sors.

The challenge of energy management

The increasing number of chipsets and functions of a mobile phone yields an increasing

power consumption. Yet the only energy source is still the battery. More energy consumption

requires a larger battery volume what does not cope with the policy of phone makers because

the battery represents already a great part of the size and weight of the mobile phone.

Indeed a thin prole is one of the attractiveness of mobile phones among the consumers. A

larger battery duration, i.e. the autonomy, constitutes another key commercial point. The

additional eects of smaller energy reserve and higher consumption require a very ecient

energy management in order to achieve a long battery lifetime.

The RF power amplier (PA) that supplies the antenna is one of the most energy con-

suming circuit of the mobile phone. Although the power radiated by the antenna is usually

tiny, the energy delivery process wastes a great amount of energy that is dissipated within

the mobile phone. The linearity required for a low signal distortion increases the power

consumption of the PA. This issue becomes harder to handle with new communication stan-

dards that apply amplitude and phase modulations for the information transmission. This

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Introduction

Fig. 1. Envelope Elimination and Restoration (EER) diagram

double modulation leads to a complex RF signal with a variable amplitude. In a conven-

tional PA architecture a great linearity is needed with such signals and results in a poor

power eciency.

The Envelope Elimination and Restoration (EER) is a transmitter architecture proposed

by Kahn1 to improve the eciency of the RF PA. The basic idea is the decomposition

of a complex signal into its polar components, i.e. amplitude and phase (Fig. 1). The

constant amplitude only phase-modulated signal, is amplied by a highly ecient saturated

PA (classes C, D, E, ...). The narrow bandwidth envelope is restored through the supply

voltage of the PA by a DC/DC converter.

The DC/DC converter used in this architecture is the step-down or buck converter. It is

a Switched-Mode Power Supply (SMPS) that can achieve a very large power eciency. One

of its constraints in EER application is the bandwidth required by the envelope signal, which

can range from hundreds of kHz for a small bandwidth modulation like the EDGE to more

than 10 MHz for wideband modulations like the WCDMA. A large bandwidth signal requires

a high switching frequency for the DC/DC converter that impacts its power eciency.

The aim of this work is to design a DC/DC converter as the power supply of the RF

power amplier in EER application for the WCDMA standard. The LC lter at the output

of the DC/DC converter usually takes an important place and so far is usually designed

with discrete components on the printed circuit board (PCB). One of the objectives of this

thesis is to decrease the required size of these passive devices to allow their integration with

the active components of the DC/DC converter in a System-on-Chip (SoC) or a System-in-

Package (SiP) conguration. The approach adopted is to increase the switching frequency

of the DC/DC converter in order to decrease the required values for the lter inductance

and capacitance. A high switching frequency is necessary to achieve the required regulation

bandwidth of the DC/DC converter with respect to WCDMA standard. For a given CMOS

technology, the eciency of the converter drops when the switching frequency increases.

New techniques are introduced to improve the eciency while taking prot of the advantage

of a high switching frequency.

1L. R. Kahn, Single-Sideband Transmission by Envelope Elimination and Restoration, Proc. IRE, pp.803-806, July 1952.


Introduction

The manuscript is structured as follow:

The rst chapter reviews the stat-of-the-art of wideband transmitters and high fre-

quency DC/DC converters.

The second chapter presents the formal design methodology developed during this

thesis for the specications of the DC/DC converter and its building blocks.

A practical use of the methodology is provided in the third chapter with the design of a

high frequency DC/DC converter for the WCDMA standard in the 0.25-µm BiCMOS

technology. The experimental results are also included in this chapter. The 0.25-µm

BiCMOS technology is suitable for RF PA but shows a limitation in eciency for HF

DC/DC converters. A challenge in this work is to prove that the theoretical peak

eciency is obtained.

In the fourth chapter a resonant gate driver is proposed to improve the eciency of

the converter at medium output power by reducing the switching losses.

The fth chapter is a short introduction to the state-of-the-art of integrated passive

components.

Further eciency improvement techniques like the power MOSFET dynamic sizing are

presented in the sixth chapter with the design of another DC/DC converter in 0.13-µm

CMOS SOI technology.

Finally in the last chapter a conclusion summarizes the contribution of this work and

provides perspectives with respect to further improvements of the integration of high

frequency DC/DC converters.


Introduction


Chapter 1

State-of-the-art of wideband radio

transmitters and DC/DC converters

Overview

1.1 Wideband radio transmitters . . . . . . . . . . . . . . . . . . . . 5

1.2 Trends in HF DC/DC converters design . . . . . . . . . . . . . . 12

This chapter explores the state-of-the of wideband radio transmitters and the key part of

the EER architecture that constitutes the matter of this thesis, the DC/DC converters. The

rst section deals with wideband transmitters and the second deals section with the high

frequency DC/DC converters. Each section starts with an introduction describing the main

features, followed by an analysis of the solutions proposed in the litterature. By the end of

the chapter the reader is introduced to our architecture choice for the DC/DC converters

designed during this thesis.

1.1 Wideband radio transmitters

The radio transmitter on a mobile platform is part of a chain going from the digital

signal processor to the antenna. Its aim is to provide the antenna with adequate RF power to

communicate with other terminals. In this section various architectures are briey introduced

with a short description of their characteristics.

1.1.1 Digital modulation of RF signals

Modern transmitters use a digital scheme to modulate the RF carrier's amplitude (ASK),

frequency (FSK) or phase (PSK). According to the standard, one or more modulations are

used together in order to provide specic features to the signal. While rst generations

applied only phase modulation, leading to a constant signal amplitude, the third (3G) and


Chapter 1 : State-of-the-art of wideband radio transmitters and DC/DC converters

fourth (4G) use both amplitude and phase modulations to increase the data rate and hence

access or deliver more data.

Throughout the evolution of standards not only the modulation format changes but also

the average RF power delivered to the antenna, decreasing for high data rate standards

compared to low data rate ones. In the same time, the peak-to-average power ratio (PAPR)

greatly increases in variable amplitude modulations, making the design of the power amplier

(PA) more complex. Indeed the large output power dynamics requires the transmitter to

be functional and ecient over a wide power range. While operating at an average output

power, the PA should be able to deliver peak power which may be 10 dB higher, without

signicant signal distortion.

One metric of signal dis torsion is the Error Vector Magnitude (EVM) which is the

distance of the received symbols to the ideal constellation nodes. Another consequence of

signal distortion is power leakage in neighbour channels dedicated to other transmissions. As

it cannot be avoided, there are thresholds dened by the Adjacent Channel Leakage Ratio

(ALCR).

1.1.2 Architectures of radio transmitters

From the beginning of radio communication to nowadays, the architecture of radio trans-

mitter followed the evolution of standards, the technology and the specications of handsets.

The primary objective in designing a radio transmitter is to ensure functionality what means

a correct signal transmission. Then comes the eciency which is a metric to compare the

radiated microwave energy to the transmitter energy consumption.

A signal is always transmitted with some corruption that may prevent its correct decoding

by the receiver. Every standard assumes that condition and xes a maximum distortion

rate that can occurs to a signal. Regarding RF signals, one source of distortion is the

power amplier of the transmitter. Thus working with a low distortion PA is critical in

communication but most of the time low distortion is obtained with the penalty of an

overhead in power consumption. The design of an ecient radio transmitter is a trade-o

between signal integrity and energy saving.

1.1.2.1 Typical radio transmitters

They amplify the RF modulated signal through a linear power amplier (classes A and

AB), according to the typical diagram in Fig. 1.1. As the dynamic range of the input

signal increases, so does the static consumption of the PA to accommodate the linearity

requirement, consequently the eciency drops.

A saturated PA (class D or E) can be used to raise the eciency but any information

on the input signal amplitude is lost. In standards using constant-envelope modulation like

GSM or Bluetooth this may be a way to enhance the eciency.



Fig. 1.1. A typical radio transmitter

Fig. 1.2. Doherty power amplier

The complex variable envelope digital modulations used in today communication systems

necessitate class-AB PAs that are inecient because they work far below the supply voltage.

In order to address such signals, various architectures are used in the state-of-the-art. Their

aim is to achieve a large eciency with an acceptable signal distortion.

1.1.2.2 Doherty power amplier

Depicted in Fig. 1.2, it combines two PAs to amplify the input signal over the whole

dynamics. The carrier amplier (class B) is optimized for low-to-average output power while

the peak amplier (class C) is optimized for peak power. PAs are biased with reasonable

power consumption and the overall eciency improvement is substantial. This is a simple

trade-o between linearity and eciency: the achievable eciency is still that of a linear

class PA and is thus below that of a switched-class PA.

1.1.2.3 Envelope tracking (ET)

Sometimes called power tracking, it is a technique that adjust the supply voltage of a

linear PA according to the amplitude of the input signal so the ratio between the amplitude

of the output voltage and supply voltage, which scales directly the eciency, comes close to

1. The eciency is close to the maximum achievable by the PA. However a margin between

the output amplitude and the supply voltage is necessary to keep the amplier in linear



Fig. 1.3. Envelope tracking PA

operation (Fig. 1.3). ET is widely employed as a way to achieve good eciency with a

linear PA. An implementation is provided in [5] that applies ET to a Doherty amplier for

further eciency enhancement.

1.1.2.4 Envelope Elimination and Restoration (EER)

EER or Kahn-technique is based on the decomposition of an RF signal into its polar

coordinates, according to eq. 1.1:

S(t) = I(t) cos (ωRF t) +Q(t) sin (ωRF t) = A(t) cos (ωRF t+ ϕ(t)) (1.1)

A (t) =√I2 (t) +Q2 (t)

ϕ (t) = arctan[Q(t)I(t)

] (1.2)

The DSP block provides both cartesian (I and Q) and polar (A and ϕ) coordinates,

according to eq. 1.2. The narrow-band envelope A(t) is amplied through a highly ecient

modulator and applied as the supply voltage of the RF PA; the input of the PA is fed with

the constant-amplitude phase modulated RF signal. Since the envelope of the input signal

does not carry information, the RF PA does not need to be linear; therefore a saturated class

PA can be used to attain higher eciency. The envelope is restored at the output thanks to

the mixer-like behavior of the PA (Fig. 1.4).

Compared to ET, the power dissipation due to the necessary margin between supply

voltage and the PA maximum output voltage is eliminated; besides the PAs commonly used

in EER belong to class-E which are more ecient than class-AB PAs of ET. The theoretical

eciency is 100%, according to [6], when a SMPS is used as the supply modulator instead

of a Linear Drop-Out regulator (LDO).

However according to the actual implementation, the performance varies widely from

the theory. For example the peak eciency of the best SMPS is around 90-95% while

the practical maximum eciency of class-E PA is 70-80%. The overall eciency of the



Fig. 1.4. EER transmitter

transmitter is computed as follow:

ηtrans = ηsm · ηPA (1.3)

where ηsm and ηPA are the eciency of the supply modulator and the RF PA, respectively.

Thus a transmitter eciency of 63% is achieved when using a supply modulator and a PA

of 90 and 70% eciency respectively. The eciency enhancement obtained with this tech-

nique is high because typical commercial RF transmitters exhibits peak eciencies around

30%.

1.1.2.5 Supply modulator

In recent past years, dierent implementations of the supply modulator have been exper-

imented. The aim is to provide high eciency over the output power range while fullling

the requirement in bandwidth (Tab. 1.1). The best suited voltage regulator to handle such

bandwidth would be the linear drop-out regulators (LDO), but they exhibit poor eciency

at large back-o1 where the mobile handsets operate most of the time. In [7] an LDO is used

in series conguration with a SMPS which brings the supply of the LDO close to the output

envelope voltage. The resulting eciency is higher than with a stand-alone LDO but the

large output lter is not an asset for integration. The series conguration is also proposed

in [8] for an EER base-station where a multi-level is used to supply an LDO. Although the

eciency is improved compared to a LDO in low power condition, the peak eciency is not

very high for a discrete power management system.

Recent works [9, 10, 11, 12, 13] focus on combining a linear class-AB amplier with

a SMPS in master/slave conguration where the linear amplier controls the SMPS. In

this modular architecture, the low frequency components of the load (RF PA) current are

provided by the SMPS while the linear amplier takes care of the high frequency ones and

also compensates for the ripple current from the SMPS. The eciency can be raised when the

SMPS has enough bandwidth to provide most of the load current. The linear amplier still

1the back-o is dened as the ratio of battery voltage to the peak envelope voltage



Fig. 1.5. Digital PA

Standards Modulation Channel PAPR Max. Pout

bandwidth BW0 (MHz) (dB) (dBm)

EDGDE 8-PSK 0.27 3.2 30

CDMA2000 QPSK/BPSK 1.25 4-9 28

8-PSK/16-QAM

WCDMA QPSK 3.84 3.5-7 24

IEEE 802.11g WLAN QPSK/BPSK 20 10 17

64-QAM/OFDM

Tab. 1.1. Power and bandwidth requirements of modern standards

needs to compensate for the ripple current of the SMPS, leading to extra power dissipation.

In contrast to the previous multi-circuit architectures, a single DC/DC converter can be

used as the supply modulator. A demonstrator designed for WCDMA has been proposed in

[14] and achieved 15 MHz bandwidth. No equivalent circuit exists in the state-of-the-art for

a higher channel bandwidth modulation like OFDM because for a switched-mode DC/DC

converter, the bandwidth comes at expense of power dissipation which limits the practical

use of these converters in modulating a wideband envelope signal. This issue will be detailed

further when we discuss the design of DC/DC converter in section 1.2.

An alternative to large bandwidth supply modulator, is the so-called digital PA (DPA)

which performs envelope reconstruction dierently. Indeed the input signal envelope is

tracked by an ADC that controls an array of linear PA [15]. The output signal enve-

lope is modulated when some units PA, working as controlled-current source, are switched

on or o (Fig. 1.5). The main advantage of this architecture is to be multi-standard as the

array of PA may be recongured, but the eciency will be less than that of the architecture

using a supply-modulated class-E PA.



Work Topology Process Standard BW Pout E. PAE

(MHz) (dBm) mod.(%) (%)

[5] Doherty ET 0.13-µm CMOS 5-MHz WiMAX - 24.22 - 38.6

2-µm HBT GaAs

[9] Hybrid 0.35-µm CMOS EDGE >10 33.52 88.3 -

[11] Hybrid 65-nm IEEE 802.11g 285 22.7 87.5 -

CMOS WLAN

[12] Hybrid 0.13-µm CMOS EDGE - 27.8 84 45.3

2-µm HBT GaAs WCDMA - 29 84 46

5-MHz WiMAX - 23.9 75 34.3

[13] Hybrid 0.35-µm CMOS WCDMA - 33 89 -

[14] EER 0.25-µm BiCMOS WCDMA 15 27 83 49

[16] Digital 0.13-µm EDGE - 21.7 - 38

SOI CMOS WCDMA - 21.7 - 38

5-MHz WiMAX - 15.3 - 22

Tab. 1.2. Wideband radio transmitters

1.1.2.6 Multiple standard capability

It is often desired that a radio transmitter designed for a specic standard be able to

address another one. In that way evolutions in communication may occur without leading

to frequent change of terminal . The discrepancies in output power, EVM, ACLR, etc.,

make it hard for a single radio to operate eciently with multiple standards, even with some

trimmings. This is why there are few examples of multiple standard radios. In [12] a polar

transmitter for EDGE, WCDMA and 5-MHz WiMAX is proposed. In this case, the output

power does not change much from one standard to another and the bandwidths of the latter

two standards are very close. A similar multistandard transmitter in digital implementation

is proposed in [16] with less performance.

1.1.2.7 Conclusion of the state-of-the-art of wideband transmitters

The state-of-the-art of wideband radio transmitters is summarized in Tab. 1.2. In [9,

11, 12, 13] a hybrid architecture is used to address wideband standards but are implemented

with technologies that cannot handle a battery voltage, unlike [14] that is designed with

Drain Extension transistors. The multistandard capability is demonstrated in [16, 12] with

good power eciency for the dierent standards. But due to the low input voltage allowed

by the technologies these transmitters would exhibit lower eciencies in a battery-powered

application because they required a rst voltage converter to scale down the battery voltage.

An EER transmitter with a large bandwidth supply modulator directly connected to the

battery can address more eectively wideband standards with a high power eciency. A

high frequency DC/DC converter can be such a supply modulator.



Fig. 1.6. Linear drop-out regulator

1.2 Trends in HF DC/DC converters design

The second key part of a polar transmitter beside the PA, is the supply modulator that

is usually realized by a DC/DC converter. Indeed according to eq. 1.3 the eciency of this

block is as much important as that of the PA for the overall eciency of the transmitter. Since

wideband modulations are addressed here, high frequency DC/DC converters are required

to amplify the envelope component of the RF signal. A high frequency operation is also in

line with our objective of decreasing the size of passive devices.

This section presents the fundamentals of DC/DC conversion. This is followed by a

review of the state-of-the-art solutions, which introduces some recent works on the topic.

Through this analysis we also point out the architecture that is the most suitable to our

application, i.e. the EER.

1.2.1 Types of DC/DC converters

1.2.1.1 Linear regulator

Linear Drop-out Regulators (LDO) are the simplest circuits that provide a DC voltage

with the lowest distortion (Fig. 1.6). The transient response is usually fast and can be

improved at the cost of DC power consumption. However they exhibit poor eciency in

back-o condition since the eciency is directly proportional to the output voltage (eq.

1.4).

ηLDO =VoutVDD

(1.4)

This is a fundamental limit to the LDO that cannot be improved by the design. Thus the

supply of low-voltage circuits (0.9-1.2 V) from a battery voltage of 3.6 V occurs with a great

eciency penalty as the eciency cannot exceed 25-33%. The state-of-art LDOs [17, 18] are

designed to avoid further power dissipation due to the bias of the op-amp and the output

transistor while achieving a large regulation bandwidth (a fast transient response).



Fig. 1.7. Switched-capacitor DC/DC converter

1.2.1.2 Switched-capacitor converter

Switched-capacitor DC/DC converter performs voltage conversion by switching an array

of capacitors in series or parallel conguration (Fig. 1.7). Like the linear regulator, it can

be integrated in CMOS technology but has a low current handling capability that can be

improved when increasing either the total switched capacitance or the switching frequency

as shown in [19]. Variable output voltage can be obtained only by changing the topology

of capacitor array. But the voltage ratio cannot vary continuously hence the application to

polar modulation necessitates a complementary LDO with the limitations inherent to such

a voltage regulator.

1.2.1.3 Inductive SMPS

The DC input voltage is converted to a lower or higher DC voltage by switching the

voltage over an inductor. Thanks to the linear operation of the power switches, no energy

is wasted in biasing. The achieved eciency is usually high, what makes it t high power

conversion. The step-down voltage converter in this class, called the buck converter, is the

object of this thesis. Its principle of operation is detailed in next subsection.

1.2.2 Principle of operation of a buck converter

As shown in Fig. 1.8, the power transistors are alternatively switched on or o, yielding

a square wave at the input of the LC tank (Fig. 1.9a). The LC tank, designed with a cut-o

frequency below the switching frequency, lters high frequency components of the square

wave. The output voltage of the buck converter is then the low frequency component with

some ripple due to switching and is given by eq. 1.5 where d is the duty cycle of the LX

node voltage.

Vout = dVbat (1.5)

A nonoverlapping or dead-time is introduced between the gate to source voltages of

the high-side transistor (or control transistor) and the low-side transistor (or synchronous

transistor) in order to prevent a cross-conduction that may be destructive for the buck

converter. During this dead-time the current of the inductor ows through the body-diode

(Drain to Bulk) of the synchronous transistor, consequently the voltage at the LX node is



Fig. 1.8. Buck converter

s s

LXbat

L

out

0

0

(a) Ideal waveforms (b) Nonoverlapping and body-diode conduction

Fig. 1.9. Typical waveforms of a buck converter

about 0.7 V (Fig. 1.9b).

1.2.2.1 Spurious emission

The ripple voltage may become a serious concern when the DC/DC converter is used to

supply a sensitive circuit like an op-amp, a LNA, a RF PA, etc.; so lowering its amplitude

becomes necessary. Analog and RF circuits for example must be supplied with very low

noise voltage which may be obtained by increasing either the values of the LC lter, hence

its size, or the switching frequency which leads to increasing dynamic losses.

In EER application the harmonics of the switching frequency in the output voltage com-

bine with the carrier frequency of the RF PA and generate a HF noise in channels used

by some other communication standards. Usually ltering masks are dened to limit the

amplitude of the spurious frequencies.



Vbat

RL L

C Rload

MCTRL

MSYNC

LX Vout

Fig. 1.10. Buck converter with parasitic components

1.2.2.2 Power loss mechanisms

Although the power switches operate in linear region, their channel resistance causes

some I2R power losses that impact the eciency of the converter. Also the periodic charge

and discharge of their parasitic capacitance results in dynamic power losses (Fig. 1.10). The

challenge in the design of a buck converter is to minimize those losses and achieve large

bandwidth without sacricing the eciency. Therefore a good modeling of the sources of

power dissipation is necessary to perform an optimization of the DC/DC converter.

The ohmic loss in the channel resistance Rdson of the power transistors and the series

resistance RL of the output inductor, are respectively modeled by eqs. 1.6 and 1.7 where I load,

ILRMS, F s, CMOS and V DD are respectively the load current (or output current), the RMS

current across the inductor, the switching frequency, the equivalent parasitic capacitance of

the transistors and the gate to source voltage swing of the power transistors.

PΩ = dRdsonI2load (1.6)

PL = RLI2LRMS

(1.7)

The switching losses due to parasitic capacitors depicted in Fig. 1.10 are modeled by

eq. 1.8 where CMOS is the equivalent parasitic capacitance. Since the switching losses are

proportional to the switching frequency, they are the major concern in the design of high


Psw = FsCMOSV2DD (1.8)

Another source of power dissipation is due to the conduction of the body-diode (Drain-

Bulk) of the synchronous transistor and is modeled by eq. 1.9 where τ d and V d are re-



spectively the duration of the dead-time and the voltage drop across the body-diode. The

dependence upon the switching frequency requires to keep the dead-time as small as possible

(compared to the switching period T s).

Pd = FsτdVdIload (1.9)

1.2.3 Architectures of high frequency buck converter

While boosting the eciency is the the main concern in designing a DC/DC converter,

the ripple voltage and the voltage handling capability are also important features in most

applications.

For a conventional buck converter, the peak-to-peak ripple current through the inductor

can be expressed as:

∆I =VDDd(1− d)

LFs(1.10)

where d, L and F s are respectively the duty cycle, the lter inductance and the switching

frequency.

This ripple current is integrated in the output capacitor and results in an output ripple

voltage:

∆V =∆I

2CFs=VDDd(1− d)

2LCF 2s

(1.11)

where C is the lter capacitance.

The multiphase interleaved and cascode architectures are proposed to manage the ripple

and the voltage handling issues respectively.

1.2.3.1 Multiphase interleaved buck converter

In order to keep the ripple voltage low without increasing the lter elements or the

switching frequency, the multiphase-interleaved topology (Fig. 1.11a) has been proposed in

[20]. Compared to a conventional buck converter, the ripple voltage is lower and is canceled

for duty cycles that are equal to a multiple of 1/N, where N is the number of phases as

shown in Fig. 1.11b. However the ripple current in each inductor is usually large because of

the lower inductance.

Canceling the ripple voltage is useful in voltage regulation but in variable output voltage

application like EER, this technique does not bring much benet because the duty cycle

is time-variant. Besides the increased number of inductors cannot be justied. Though

[21] introduces a novel implementation of multiphase-interleaved technique that cancels the

ripple at any duty cycle, the issue can be handled by a conventional buck converter with

appropriate switching frequency and output lter. Also increasing the number of inductors



Vbat

L1

C

Vout

Vbat

LN

∆T=3600/N

(a) Schematic

0 20 40 60 80 1000

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Duty cycle (%)N

orm

aliz

ed ∆

I

Single phase2−phase4−phase

0 20 40 60 80 1000

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Duty cycle (%)N

orm

aliz

ed ∆

I

Single phase2−phase4−phase

(b) Ripple current through capacitor C for single and multi-phase interleaved buck converters

Fig. 1.11. Multiphase interleaved buck converter

raises the problem of magnetic coupling between the inductors which is a major concern in

multiphase-interleaved power stages.

1.2.3.2 Cascode power stage

The voltage handling capability is a key factor in designing a power management circuit.

As CMOS technology shrinks leading to very low nominal voltage, the power requirements

does not follow the same variation and even increases for some applications making high

voltage necessary in order to keep the current consumption acceptable. For instance front-end

PAs are still supplied with voltages as high as 5-V (battery). In order to supply the PA with

such voltage, the DC/DC converter switches should be able to support the corresponding

voltage stress. Clearly a short-channel transistor cannot do. A cascode power stage (Fig.

1.12) was proposed in [22, 23] to handle twice the process nominal voltage. The high side

cascode PMOS in these circuits suers from voltage stress during body-diode conduction.

Further increase in the number of cascoded-devices may be a solution to the voltage stress

but will increase the total resistance in the current path as well as the complexity of the bias

generation of the cascode devices.

The use of Drain-Extension and diused channel MOSFET, when available in the fabri-

cation process, is a fair solution to the voltage stress. Unlike a cascode bridge, the control

is simple and similar to that of a conventional power stage. The breakdown voltage of such

device is around 8v15 V, i.e. several times the battery voltage. This is useful since the

switching of the power stage may cause large overshoot on the internal supply voltage. A

complete polar transmitter including the PA, using NLDEMOS transistors for operate with

3.6 V is presented in [14] (Tab. 1.2).



Fig. 1.12. Buck converter with cascode power stage

In portable battery-powered devices, an external DC/DC converter is used to bring the

battery voltage down to the process nominal voltage before the internal circuit pins. The use

of Drain-Extension MOSFETs in internal power management blocks makes this front-end

voltage regulator useless.

1.2.4 Control method

1.2.4.1 Feedback loop

Accuracy and transient response are important features in voltage regulator module. The

accuracy is a metric to estimate how close the output voltage is to the desired voltage and

the system needs to respond to load variations with velocity and a good accuracy. To achieve

a good accuracy in reference tracking a feedback loop must include an integrator.

The PID controller has the advantage of high precision and tunable response time. It

can be implemented by sensing either the output voltage or the inductor current, since

both contain the information on load variation. Even if current mode is said to be faster,

voltage mode is easier and more accurate. Indeed an accurate sensing of the inductor current

requires the insertion of a series resistance that increases the ohmic loss. This power wasting

can be avoided by mirroring the current owing through the power transistors [24] but this

technique has a limited accuracy.

In EER the load impedance is constant, so the regulation bandwidth should be at least

equal to the reference signal bandwidth. The design of the PID controller needs only to

achieve this bandwidth in close-loop. Faster transient response could be obtained with

hysteretic controller [20, 25, 26] but is not necessary here. However this interesting feature

of the hysteretic controller is overshadowed by a relatively high spurious emission because

of a variable switching frequency [10].



Fig. 1.13. Digital PWM

1.2.4.2 Power stage switching

Switching at xed frequency with a PWM signal of the power stage keeps the switching

losses constant in any load condition. As a consequence, the eciency is heavily impacted

at low load current. The variable switching frequency techniques such as PFM or hysteretic

control aim to enhance the eciency at light load condition by lowering the switching fre-

quency. Combining PFM with PWM helps to achieve a good eciency at any load current

as demonstrated in [27, 28].

The main drawback of variable switching frequency techniques in RF circuits is the

nonlocalized spurious frequencies along with higher low frequency noise unlike PWM. In

new communications standards, there are stringent spurious emission rules that are hard to

cope with when the spurious frequencies are not well known.

With modern circuit environment dominated by digital signal processing, digital imple-

mentation of PWM controller has been investigated (Fig. 1.13). The multimode capability

is one of the advantages of digital circuits and allow a simple programming of the digital

PWM controller bandwidth and/or control law according to the targeted application. Such

feature is highly desired on multistandard RF radios because multiple standards could be

addressed by a single DC/DC converter acting as the envelope modulator. The limitation

of the DPWM is the low switching frequency which does not facilitate the full integration of

the converter. Indeed for a PWM frequency F s and n-bit precision, the clock frequency is

given by Fclk = 2nFs and may become too high. For instance, a 10-bit resolution at 1-MHz

switching frequency leads to 1024 MHz clock frequency. Although [29] proposed a method

to increase the eective resolution, the achievable switching frequency is far below that of

analog PWM circuits.

Like their analog counterparts digital controllers can combine both PWM and PFM for

eciency enhancement [30, 31].

1.2.5 Integration

Full integration of power management unit is a key factor to resolve supply voltage

integrity issues in ICs. In terms of energy eciency, it saves the energy otherwise wasted in



Fig. 1.14. 3D-stack of active and passive dies

interconnects, especially when large currents are driven.

In fact many fully integrated DC/DC converters have been demonstrated in the sate-

of-the-art, based on dierent approaches. Full CMOS integration is the most common one

and leads to a single chip where the power management circuit and the targeted load are

designed on the same substrate. Thick back-end metals are used to implement air-core

inductors; however the quality factor2 is low because of poor conductivity, due to limited

metal thickness, and the lack of magnetic core. The resulting series resistance gets high and

impacts the eciency of the converters using such approach.

The lter capacitor can be integrated more easily than the inductor though the area over-

head is quite high. Even with advanced deep submicron CMOS technologies, the capacitive

density is around few fF/µm2 which is low when it comes to integrate nF-range capacitors.

For instance in [32] a total output capacitance of 2x8.22 nF occupies 2.71 mm2 whereas the

active devices and the load occupy 1.07 mm2.

3D-stack is another technique used to integrate the DC/DC converter, the load and the

passive elements in a single package of multiple chips (Fig. 1.14). In that way, the converter

and the load are realized in an advanced CMOS process while the LC lter is designed with

an appropriate passive process [3] or cheap CMOS process [33]. Compared to the single

chip solution, higher quality passive devices are obtained and the eciency is not too much

impacted.

The design and integration of high-quality passive devices is a key factor for the integra-

tion of HF SMPSs and will be discussed in chapter 5.

1.2.6 Conclusion

The state-of-the-art of DC/DC converters shows a wide variety of power stage architec-

tures and control methods. The advantages and drawbacks of each depend on the objectives

of the application. The recent results are summarized in Tab. 1.3.

For polar modulator application the reference tracking can be achieved by a PID con-

2dened as the ratio of the inductance to its equivalent series resistance



Work Process Topology Control Freq. Vin Vout Iout L C ηmax Passive

(MHz) (V) (V) (mA) (nH) (nF) (%) devices

[20] 90-nm 4-phase hysteresis 233 1.4 1.1 300 4x6.8 2.5 84.5 C on-chip

2005 CMOS L o-chip

[34] 0.35-µm 1-phase PWM 100 3.5 1.5 300 18.9 6.1 73.8 L and C

2005 CMOS on-chip

[25] 0.18-µm 2-phase hysteresis 45 2.8 1.8 200 2x11 6 64 L and C

2007 BiCMOS on-chip

[33] 0.35-µm 1-phase PWM 200 3.3 2.3 60 22 2.5 62 LC die

2007 CMOS stacked

[21] 130-nm 2-phase PWM 170 1.2 0.9 350 2x2 2x5.2 77.9 L and C

2008 CMOS on-chip

[32] 0.18-µm 2-phase PWM 200 1.8 0.9 500 2x2.14 2x8.22 64 L and C

2009 BiCMOS on-chip

[3] 65-nm 1-phase PWM 100 1.2 0.85 80.6 11 30 87.5 LC die

2009 CMOS ip-chipped

Tab. 1.3. Recent works on HF DC/DC converters

troller designed according to the bandwidth specication. The PID controller allows to

choose a PWM switching-mode for the power stage, hence giving constant spurious frequen-

cies.


Chapter 2

Design methodology

Overview

2.1 Specications of the SMPS . . . . . . . . . . . . . . . . . . . . . . 23

2.2 Circuit optimization . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.3 Methodology summary . . . . . . . . . . . . . . . . . . . . . . . . 44

The aim of this chapter is to show how the requirements of EER translate to the spec-

ications of the main building blocks of the SMPS. A general design methodology is then

proposed for their optimization.

2.1 Specications of the SMPS

2.1.1 Power specications

The power rating of the DC/DC converter comes from both the power requirement of

the application and the stand-alone eciency of the RF PA. In the fth column of Tab.

1.1 is given the maximum average RF output power, P out,max, fed into the antenna for

some communication standards. The maximum peak power is obtained as the product of

the maximum average RF power and the PAPR. This is the maximum output power that

the transmitter should be able to provide to the antenna. Otherwise the envelope signal is

clamped which causes third order distortion and increases the EVM. Given the PA eciency,

the maximum average and peak power supplied by the DC/DC converter are:

Pav,max =Pout,maxηPA

(2.1)

Ppeak,max =Pout,max + PAPR

ηPA(2.2)

The equations 2.1 and 2.2 show how the eciency of the RF PA eciency impacts the

output power specication of the SMPS. Depending on this eciency the required maximum


Chapter 2 : Design methodology

−50 −40 −30 −20 −10 0 10 200

0.5

1

1.5

2

2.5

3

3.5

4

4.5

Output power (dBm)

PD

F (

%)

Urban

Suburban

(a) CDMA2000 PDF

−10 −5 0 5 10 15 20 250

10

20

30

40

50

60

70

Output power (dBm)

PA

E (

%)

(b) Typical class-E PA power-added eciency

Fig. 2.1. CDMA probability density function (PDF) in urban and suburban areas, andclass-E PA eciency

output power of the SMPS can be very high compared to the maximum RF power transmitted

by the antenna. Also comes the question: for which power level should the converter be

optimized since high eciency cannot be achieved over a wide power range?

The probability density function (PDF) of the RF power (on the antenna), in most cases,

is almost gaussian-shaped and exhibits a maximum at large back-o from the maximum

power (Fig. 2.1a). This means that the mobile handset operates most of the time with

low power and requires large power in very rare conditions. Clearly the eciency should be

higher for output power range with the highest probability; however for maximum power

which occurs with a low probability, the eciency should not be too low because the battery

life-time depends on the average overall eciency which is power-weighted and may be

expressed as:

ηav =

∫ Pmax

Pmin

PRF · pr (PRF ) dPRF∫ Pmax

Pmin

PRF

η(PRF )· pr (PRF ) dPRF

(2.3)

where PRF , pr (PRF ) and η (PRF ) are respectively the output RF power, the probability

density of working at PRF output power and the eciency of the transmitter at PRF output

power (dened by eq. 1.3). Giving a typical class-E PA eciency of Fig. 2.1b the resulting

average eciency is only 10.4%.

EER is specially useful with medium to high output power as the high switching losses

of the SMPS transistors heavily impact the eciency at low output power. So optimizing

the DC/DC converter for maximum PA average output power is a reasonable choice. At

system-level this implies a power-sharing scheme where another PA deals with low output

power. Such study is outside the scope of this thesis and therefore is not addressed here.



Fig. 2.2. WCDMA envelope in time domain

2.1.1.1 Output voltage and load current ranges

The large dynamic of signal envelope poses a challenge to the supply modulator to achieve

a moderate distortion. For instance WCDMA envelope (gure 2.2) has a 29.54-dB dynamics1

and thus requires the same dynamic for the output voltage of the supply modulator. In a

buck converter, the output voltage is tuned with the duty cycle of the power stage. Because

of IR drops through the high side switch and the inductor series resistance, the maximum

output voltage Vout,max = dmaxVbat is lower than V bat. A practical value of dmax is 80∼90%;

this gives a minimum duty cycle dmin = dmax

10(29.54/20) = 3% for WCDMA envelope.

The specication of the output current of the SMPS requires the determination of the

equivalent resistance of the PA. Whereas a linear PA behaves like a current source, a satu-

rated PA acts as a resistance with respect to the power supply. As long as the PA remains

saturated this resistance is almost constant and can be determined from the battery voltage,

the maximum average output power, the PAPR and the PA eciency (eq. 2.4). Indeed

the DC/DC converter provides a peak power when the output voltage reaches its maximum

value, V out,max.

RPA =V 2out,max · ηPA

(Pout,max + PAPR)watt(2.4)

Tab. 2.1 gives practical PA equivalent resistance for CDMA2000, WCDMA and IEEE

802.11g WLAN, assuming a 50%-ecient PA and a maximum DC/DC output voltage of 80%

of the 3.6-V battery voltage. Knowing the equivalent load resistance, it becomes possible to

determine the current range of the SMPS output stage.

As it can be deducted from eq. 2.4, the resistance depends on the available battery

voltage. When operating under low battery voltage, the PA resistance may be low leading

to a high current required to achieve the power demand. This situation happens typically

when a low-voltage CMOS process is used to design the transmitter. The higher the current,

the higher the ohmic losses due to chip interconnect resistance.

1dened as the ratio of the peak to the lowest value



Standards PAPR Max. Pout RPA

(dB) (dBm) (Ω)

CDMA2000 4 28 2.61

WCDMA 3.5 24 6.9

IEEE 802.11g WLAN 10 17 8.27

Tab. 2.1. PA equivalent resistance

Fig. 2.3. Closed-loop buck converter

2.1.2 Control loop

This subsection presents the specication of the frequency response of the SMPS in

closed-loop condition (Fig. 2.3).

2.1.2.1 Frequency response

The frequency behaviour of the buck converter is shaped by the output LC lter which is

a second order low-pass. The PID controller intends to tune the SMPS response for a proper

envelope reconstruction and maintain the system stable in the closed-loop condition. The

closed-loop frequency response is given by eq. 2.5 where β is the DC gain and ω0 = 2πf0.

A ne analysis of the inuence on the radio spectrum of the small signal bandwidth f 0, the

group delay τ and the damping factor ξ is provided in [6] for WCDMA.

H (s) =β

s2 + 2ξω0s+ ω20

(2.5)

The envelope signal bandwidth is higher than the channel bandwidth given in Tab. 1.1

when cartesian to polar coordinates conversion is performed (eq. 1.2 and Fig. 2.4). In

fact the actual bandwidth is four to ve times the channel bandwidth, hence forcing the

supply modulator to exhibit a similar bandwidth f 0 to lower the distortion and meet EVM

requirements. Indeed the distortion resulting from low bandwidth appears as a noise near

the carrier frequency that may aects the correct demodulation. Besides a near-band noise

appears in adjacent channels where ACLR rules must be successfully passed (Fig. 2.5). A

rule of thumb is to set f0 to four times the channel bandwidth.

The determination of L and C is less straightforward because many frequency and tran-

sient parameters depend on them. In order to avoid attenuation in the large signal band-



(a) Envelope (b) RF spectrum

Fig. 2.4. WCDMA envelope and RF spectra

Fig. 2.5. WLAN RF spectrum for modulator bandwidth f 0 equal to one, two and fourtimes the channel bandwidth



width, the LC cut-o frequency (eq. 2.6) has to be higher than the channel bandwidth.

FLC =1

2π√LC

(2.6)

Output RF spectrum is sensitive to the group delay hence to the damping factor of the

lter ξ and the bandwidth f 0 (eq. 2.7).τ = dϕH(iω)dω

≈ ξπf0

for ω ω0

ξ = 1RPA

√LC

(2.7)

Like electromagnetic wave packets crossing a transmission medium (air, vacuum, etc.), a

variation of group delay causes distortion in the packets. Similar process happens to the

envelope signal through the supply modulator. As shown by Pinon [6], both overdamping

and underdamping make the group delay vary within the bandwidth; the optimum damping

factor was found to be 0.7 which corresponds to a maximally at second-order lter.

So depending on the PA equivalent resistance and the required bandwidth, both the

product and the ratio of L and C must be adjusted for optimum damping.

The delay between the EER envelope and phase path is another important source of

distortion and thus requires a good synchronization of both paths. This is done typically

by inserting delay in the phase path that is faster than the envelope path. This issue is not

addressed here.

2.1.2.2 Switching frequency selection method

In this section, an analysis of the noise induced by the PWM on the envelope signal is

performed to select a correct switching frequency.

A single tone modulating signal is used to establish the Fourier series decomposition of

the PWM signal at node LX (eq. 2.9). It is assumed that the modulating signal with tone

frequency fmod yields duty cycle d(t) in the power stage (eq. 2.8):

d(t) =α

2(1 + sin (2πfmodt)) (2.8)

xpwm(t) =Vbatα

2+Vbatα

2sin (2πfmodt) +

∞∑n=1

Vbatπn

sin (2πnFst)

−∞∑n=1

Vbatπn

±∞∑k=±1

Jk(−nπα) sin (2π (nFst+ kfmod) t− nπα) (2.9)

where Jk is a Bessel function of the rst kind. For a multi-tone signal like an RF envelope,

the analysis is very hard though [35] proposes a method to determine an equivalent single

tone. Nonetheless eq. 2.9 is useful to estimate the eect of PWM noise on the SMPS



Fig. 2.6. PWM spectrum for single tone modulation at 200 MHz switching frequency

output signal, in particular it shows that no harmonics contribution of fmod is present in

the spectrum and most of the noise is concentrated in high frequency around the harmonics

of the switching frequency F s (Fig. 2.6). However some aliasing spurious (nFs ± kfmod)appear in low frequency as the PWM is a sampling process and therefore increase the overall

near-band noise. In order to minimize both the near-band and the high frequency noise, the

switching frequency F s has to be increased so the corresponding spurious frequencies fall in

the frequency range where the attenuation of the LC lter is high enough. Even with high

F s, spurious frequencies due to the fourth term of eq. 2.9 fall close to the baseband but with

very low magnitude since the Bessel functions are scaled by 1/n!.

For instance with fmod = 10 MHz, Fs = 100 MHz and α = 0.5, the intermodulation of

the 9th harmonic of fmod with F s aliases to fmod and has a magnitude of −VbatπJ−9

(−π

2

)=

9.37× 10−8 ≈ 0

As a criterion for switching frequency selection, the ratio of the signal amplitude (second

term of eq. 2.9) to the amplitude of the aliased signal is a good gure of merit, both

normalized to V bat. The upper bond of this amplitude is given in eq. 2.10, considering

that the most signicant aliasing occurs when harmonics of fmod intermodulate with the

fundamental of F s.

Amax = −J−kalias (−πα)

π=Jkalias (πα)

π(2.10)

where kalias is the order of the harmonic that aliases with fmod and is computed as:

kalias =Fsfmod

− 1 (2.11)

A signal-to-alias ratio is dened as:

SAR =πα

2Jkalias (πα)(2.12)



Standards Channel fmod F s

bandwidth (MHz) (MHz) (MHz)

CDMA2000 1.25 5 35

WCDMA 3.84 15.36 107

IEEE 802.11g WLAN 20 80 560

Tab. 2.2. Optimum switching frequency

As αmax = 1, the worst case ratio is:

SARmin =π

2Jkalias (π)(2.13)

This criterion is optimal compared to the usual rule that sets F s to ten times fmod and

more pertinent than that of [35]. In the application to continuous spectrum envelope signal

in EER, the modulating frequency to consider is the highest signicant frequency component.

In subsection 2.1.2.1 that frequency is set to four times the channel bandwidth and denes

also the supply modulator bandwidth. The optimal switching frequencies yielding a 40 dB

minimum SAR are listed in Tab. 2.2 for CDMA2000, WCDMA and IEEE 802.11g WLAN

standards: this results in an order of the Bessel function of kalias = 6 using eq. 2.13. The

ratio between switching frequency and modulating frequency is computed from eq. 2.11 and

is 7. This number compares to 10, the ratio given by the rule of thumb .

Even with the restrictive evaluation proposed here, Tab. 2.2 indicates that EER with

WLAN standard is hardly possible using a single SMPS as supply modulator.

2.1.2.3 High frequency PWM noise

The selection of a switching frequency does not only depend on low frequency noise

considerations. As high frequency noise components appear around the harmonics of the

switching frequency (the third and fourth terms of eq. 2.9), the ltering of this noise has

an inuence on the choice of the switching frequency. When the envelope is restored at the

output of the PA, the HF noise is mixed with carrier frequency and the intermodulation spu-

rious frequencies fall in a frequency range dedicated to other communications. For instance

a 150 MHz switching frequency mixed with a 1.8 GHz carrier yields a spurious frequency in

channels around 1.95 GHz. The total power that is tolerated in those channels is specied

by the communication standard.

Selecting a higher switching frequency brings two benets:

the intermodulation products are pushed into higher frequency range, i.e. non-adjacent

channels.

the number of intermodulation products is smaller (less spurious frequencies are gen-

erated), they are farther one from the other and the total power is largely spread.


2.2 Circuit optimization

Fig. 2.7. Linear model of the buck converter

The chance to generate a spurious frequency with a critical magnitude in an adjacent

channel is largely reduced.


In this section, the optimization of the circuit is performed according to the global spec-

ications of the previous section.

2.2.1 Controller and output lter

2.2.1.1 Linear model of the buck converter

A linear model of the SMPS is established for the purpose of PID controller and LC lter

design (Fig. 2.7). Though the power stage is a non-linear system, a low frequency AC model

is computed considering that eq. 1.5 stands as long as the duty cycle of the PWM signal is

varied at a rate lower than the closed-loop bandwidth f 0. Under this condition the power

stage is simply a buer with a gain of V bat.

The PWM signal is generated through a high gain comparator which inputs are the error

signal from the controller and a high frequency ramp as depicted in Fig. 2.8. A voltage-

to-time conversion occurs that yields the duty cycle i.e. signal's on-time varying from 0 to

100% as the error signal goes from the minimum to the maximum of the ramp. The resulting

gain for the AC model is:d

Verr=

1

V ppramp(2.14)

where Vppramp is the peak-to-peak voltage of the ramp signal.

The overall gain of the PWM and the power stage is given by eq. 2.15 and is constant

for a certain battery voltage. This voltage varies on a mobile platform from 2.7 V (depleted

battery) to 4.3 V (fully charged battery). For stability purpose the peak-to-peak voltage of



Fig. 2.8. Pulse width modulator

the ramp signal must track this variation to ensure a constant gain in the control loop.

G =Vbat

V ppramp(2.15)

For an accurate PWM, the comparator must have a high gain at the switching frequency

and a sucient slew-rate to guarantee the shortest pulses corresponding to the minimum

and the maximum duty ratio.

2.2.1.2 Controller

The cut-o frequency of the LC lter can be set to the large signal bandwidth BW0 of

the modulation to fulll frequency specication. Individual values for L and C are obtained

by combining this condition with the damping factor of eq. 2.7, leading to eq. 2.16:LC =(

12πBW0

)2

LC

= (ξRPA)2⇒

L = ξRPA

2πBW0

C = 12πBW0ξRPA

(2.16)

When applied to WCDMA, this gives 200 nH and 8.6 nF respectively. However the cut-

o frequency can be chosen higher than the large signal bandwidth in order to have a smaller

lter as long as the ripple current and/or the ripple voltage does not become excessive.

The PID controller features two zeros and two poles that are used to ensure that the

closed-loop transfer function is very close to eq. 2.5. Dierent poles and zeros placement

strategies exist in the theory of system control to design a robust PID controller. As the

design parameters such as PA equivalent resistance, lter inductance and capacitance, may

shift from nominal values during the operation, the pole-zero cancellation strategy is not

interesting here because it requires a precise pole and zero placement. Instead the zeros are

placed around the double-pole of the output lter and the non-zero pole is positioned such

that the open-loop unity-gain frequency corresponds to the maximum of controller phase

thus optimizing the closed-loop phase margin (Fig. 2.9).

The open-loop transfer function is the product of controller transfer function (eq. 2.17),

the PWM and power stage gain and the LC lter transfer function. For stability analysis, the

criteria are based on the open-loop transfer function delay margin and magnitude margin,

derived from phase margin and gain margin respectively.



105

106

107

108

−60

−40

−20

0

20

40

60

Mag

nit

ud

e (d

B)

Frequency (Hz)

Controller

Open−loop

Open−loop without controller

Fz1

Fz2

Fp2

FLC

Fig. 2.9. Poles and zeros placement

Hctrl (s) =(s+ 2πfz1) (s+ 2πfz2)

s (s+ 2πfp2)(2.17)

where fz1, fz2 and fp2 are respectively the rst zero, the second zero and the second pole of

the controller, the rst pole being at DC frequency.

On Fig. 2.10 are plotted the Bode diagram of the controller, the open-loop and closed-

loop transfer functions for WCDMA. The delay margin is computed using eq. 2.18 and

consists of a pure delay at unity-gain frequency. Although most stability analysis assume a

450-phase margin as a good criterion to dene a stable system, the delay margin indicates a

pure delay that can make a system unstable. If such delay has not been taken into account

in the AC model and exists indeed in the loop, the system becomes unstable no matter

the phase margin is. Since a system is usually modeled with some approximations and

uncertainty on its parameters, the delay margin constitutes a more selective criterion than

the phase margin. A practical condition is a delay margin higher than the delay through the

comparator and the power stage τPWM (eq. 2.18).

∆T =∆ϕ

2πf0dB

> τPWM (2.18)

where ∆ϕ and f 0dB are respectively the phase margin and the open-loop unity-gain frequency.

The second stability criterion is based on magnitude margin ∆M that is more restrictive

than the gain margin. Indeed the magnitude margin indicates how close the gain is to the

critical point (0 dB, -1800) when frequency varies. On a Nyquist diagram the magnitude



−30−20−10

01020304050

Mag

nitu

de (

dB)

105

106

107

108

−180

−135

−90

−45

0

45

Pha

se (

deg)

Frequency (Hz)

Controller

Open−loop

Closed−loop

∆φ

Fig. 2.10. Bode diagram of the controller, the open-loop and the closed-loop transferfunction

margin is the radius of the circle centered at (-1,0) and tangent to the open-loop transfer

function (see Fig. 2.11). A fair stability criterion is:

∆M > 0.5 (2.19)

The system has a closed-loop gain β in order to have the input reference voltage V ref in

a voltage range that is compatible with the control circuit. Indeed the output voltage of the

SMPS can be as high as the battery voltage whereas the control circuit may be designed in

a CMOS process with a maximum voltage lower than the battery voltage. Another reason

is that the reference voltage is supplied at system-level by a DAC whose output range does

not exceed 1 to 2 V. With a nominal battery voltage of 3.6 V a loop gain β = 3 limits the

reference voltage range to 1.2 V which is compatible with CMOS technologies down to 65nm.

Further increase of β alleviates the burden of the circuit that provides the input reference

voltage but makes the stability harder to achieve.

2.2.2 Power stage

The optimization of the power stage focus on fullling the power specications with the

minimum power loss and the appropriate velocity in switching at very high frequency.



−1 −0.8 −0.6 −0.4 −0.2 0 0.2−3

−2

−1

0

1

2

3

Real Axis

Imag

inar

y A

xis

∆M

Fig. 2.11. Nyquist diagram of the open-loop transfer function

2.2.2.1 Power switches size

Minimizing the power loss requires to optimize the size of the power transistors. Actually

only the width needs to be optimized because the switching losses are proportional to it

whereas the ohmic losses are inversely proportional to it (Fig. 2.12). Both gate capacitance

and channel resistance are proportional to the channel length which must therefore be set

to the minimum allowed by the technology. For a given switching frequency f s and gate to

source voltage swing V DD, the optimum width W opt is obtained at the minimum of eq. 2.20.

Ploss =R0on

WI2RMS +WfsC

0swV

2DD (2.20)

where IRMS, R0on and C0

sw are respectively the RMS current across the transistor, the unit

width resistance and the unit width transistor capacitance that includes gate capacitance

and drain-body capacitance. The optimum width thus obtained leads to equal switching

and ohmic losses (eq. 2.21).

Wopt =

√R0onI

2RMS

fsC0swV

2DD

(2.21)

The RMS current IRMS to consider is the RMS load current I load plus the RMS ripple

current across the inductor, scaled by the duty cycle d for the high-side transistor (eq. 2.22)

and by (1-d) for the low-side transistor.

I2RMS = d

(I2load +

∆I

12

2)(2.22)

Since the transmitter is to be optimized for the maximum output power (see subsection

2.1.1), the load current in eq. 2.22 should be the PA maximum input current, IPA,max.



0 5 10 15 20 25 30 35 400

50

100

150

200

250

Width (mm)

Pow

er (

mW

)

Total power loss

OhmicSwitching

Optimal width

Fig. 2.12. Ohmic, switching and total power losses variation with the width

pW

nW

pa W⋅

na W⋅

1Npa W− ⋅

1Nna W− ⋅

Fig. 2.13. Gate driver

2.2.2.2 Power switches drivers

A typical power switch driver is a chain of weighted-size CMOS inverters (Fig. 2.13). The

number of stages as well as the tapering factor, i.e. the size ratio between consecutive stages,

must be optimized for switching velocity and energy dissipation. Indeed the last inverter

stage should be larger enough to switch the power transistor on and o with a reasonable

speed. But a larger inverter also adds some extra capacitance to the gate capacitance of the

power transistor, increasing further the switching losses. The optimum number of stages N

and the tapering factor a depend on the power transistor gate capacitance Cgate,MOS and

the gate capacitance of the rst inverter stage Cinv1 according to eq. 2.23.N = ln

(Cgate,MOS

Cinv1

)a =

(Cgate,MOS

Cinv1

) 1N

= e1 ≈ 2.7(2.23)



2.2.3 Impact of the increase of switching frequency

The methodology developed in this section leads to a DC/DC converter optimized in

terms of bandwidth and power eciency. One aim of this thesis is to push for a complete

integration of the transmitter, i.e. the PA with the DC/DC converter. The approach adopted

in this work is to increase the switching frequency in order to decrease the required output

lter inductance and capacitance down to values that can be integrated on-chip. The topic of

chapter 5 deals with the dierent technologies available today to integrate passive devices.

But for now it is essential to analyze the impact of switching the DC/DC converter at a

frequency higher than the optimum determined by eqs. 2.11-2.13.

As the ripple current through the inductor is inversely proportional to the switching

frequency and the inductance, a decrease of the former must be followed by a proportional

increase of the latter in order to keep its value constant. Thus the lter capacitance is also

decreased by the same factor as the inductance to keep the output voltage ripple current

constant.

2.2.3.1 Impact of the increase of switching frequency on the control circuit

The bandwidth specication of the control circuit is determined only by the considered

modulation format and is not aected by an increase of the switching frequency. So the

poles and zeros placement remains unchanged.

The PWM comparator must exhibit a high gain at the new switching frequency because

the pulse duration corresponding the minimum and the maximum duty cycle become very

small. This large gain-bandwidth necessitates a larger DC bias; however this does not impact

the eciency of the converter since the overall power consumption of the control circuit is

tiny compared to that of the power stage.

2.2.3.2 Impact of the increase of switching frequency on the power stage

An increase of the switching frequency leads to a decrease of the optimal size of power

transistors according to eq. 2.21. Consequently the channel resistance increases as well as

the IR drop because the current specications remain the same. Ultimately this voltage drop

reduces signicantly the maximum voltage available at the output and therefore prevents

the transistor width from getting further small whatever high the switching frequency may

be.

A straightforward computation using eq. 2.23 shows that drivers' size decreases also

following that of power transistors' size. But a special attention should be paid to the rise

time tr and the fall time tf of the gate-source voltage of the power transistors because they

determine the minimum duty cycle achievable by the power stage. When the switching

period T s shrinks, an equivalent shrink in gate-source voltage transition time is necessary to



(a) lond dead-time (b) short dead-time

Fig. 2.14. Power dissipation due to the dead-time

keep constant the minimum duty cycle (eq. 2.24).

dmin =tr + tfTs

(2.24)

The commutation of the power transistor is equivalent to an RC charge and discharge

with a time constant of τ = RNCgate, where RN and Cgate are respectively the channel

resistance of the last inverter stage of the driver (assuming both PMOS and NMOS have the

same resistance i.e. the PMOS is three times as large as the NMOS) and the gate capacitance

of the power transistors. The rise/fall time depends on process parameters R0on and C

0sw, and

design parameters W power and WN which are respectively the width of the power transistor

and that of the last inverter:

tr,f = 2.2τ = 2.2R0onC

0sw

Wpower

WN

(2.25)

Typical values are R0on = 3000Ω.µm and C0

sw = 2.5fF/µm. With a driver tapering factor

of 2.7 (eq. 2.23), the minimum duty cycle for a 400-MHz switching frequency is dmin = 7%.

2.2.4 Adaptive dead-time control

At very high switching frequency the power losses due to the body diode conduction

(eq. 1.9) become high if the dead-times are not controlled precisely. Indeed a large dead-

time td2 increases the total diode conduction time τ d whereas a too short dead-time leads

to the discharge of the capacitance CLX (Fig. 2.14) by the low-side switch, that causes

signicant extra switching losses (eq. 2.26) since this capacitance is usually as high as the

gate capacitance of power transistors.

PCLX= fsCLXV

2bat (2.26)



Fig. 2.15. Variation of the discharge time of CLX with load current

Thus an optimal dead-time at this transition is the discharge time of capacitance CLX

which varies with load current. Unlike td2 the dead-time td1 does not depend on load current

and should be optimized dierently.

As dead-time cannot be avoided for safety reason, a rule of thumb is to have the body

conduction lasting less than one tenth of the switching period, so dead-time losses remain

negligible compared to switching and ohmic losses.

The optimization of dead-time can save as much as half the switching losses of the

capacitance CLX . Indeed this capacitance is charged through the high-side switch and

discharged through the inductor. Only the charge step results in power losses unlike the

discharge which is a charge transfer between the capacitance and the inductance.

2.2.4.1 Optimization of dead-time td2

The dependence of the discharge time of capacitance CLX on load current is illustrated

in Fig. 2.15. In particular the discharge time is high for low current and small for large

current.

In earlier works on low switching frequency DC/DC converters, a constant dead-time

is implemented by delay cells in drivers and does not cause signicant power losses. For

high switching frequency and variable load current applications such as EER, this technique

is not optimal because it requires a large dead-time to ensure that capacitance CLX is

not discharged when load current is minimum. The optimization must therefore take into

account the loading condition to set the appropriate dead-time, i.e. to perform an adaptive

dead-time control.

The adaptive dead-time control has been used in DC/DC converters switching at fre-

quencies around few MHz [36, 37]. An approach based on sensing the voltage at LX node

was then adopted. The driver of the synchronous transistor is activated (after the control

transistor is turned o) only when the LX voltage reaches 0 V or 1/2V bat. Inevitably there

is a loop delay that increases the body diode conduction time and hence contributes to power

losses. The loop delay due to the sense signal propagation through the CMOS logic gates to

the gate of the synchronous transistor is negligible when switching period is hundreds of ns



100

101

102

5

10

15

20

25

30

Switching frequency (MHz)

Rel

ativ

e de

ad−

time

pow

er d

issi

patio

n (%

)

Fig. 2.16. Contribution of the body diode conduction losses as a function of switchingfrequency

to few µs but becomes a major drawback for converters switching at tens to hundreds MHz.

Fig. 2.16 plots the contribution to the total power losses of 1-ns body diode conduction time

for a buck converter optimized around 350 mA load current in a standard CMOS process.

Even with advanced CMOS technologies, the loop delay is around hundreds of picoseconds

that may be acceptable for switching frequency of tens MHz but is not suitable when the

switching frequency is beyond 200∼300 MHz (T s < 5ns). An alternative to LX node sense is

proposed in [38] and demonstrated for only 200-kHz switching frequency. It is an algorithm

that needs multiple switching cycles to perform a calibration of the dead-time each time a

load variation occurs.

Both previous techniques do not t a HF SMPS with variable load condition like in EER.

Instead the approach used in this thesis is based on a continuous tuning of dead-time from

load transient. The optimal dead-time is obtained by setting a delay equals to the discharge

time of capacitance CLX that is:

τLX = CLXVbatILmax

(2.27)

with ILmax as the peak inductor current, given by:

ILmax = Iload +∆IL

2≈ Iload (2.28)

considering that the ripple current is negligible compared to load current. So eq. 2.27

can be rewritten as:

τLX = CLXVbatIload

(2.29)

Instead of sensing load current to determine the delay given by eq. 2.29, the SMPS input

reference voltage V ref is used as the load in EER is modeled by a resistance. Hence eq. 2.29

becomes:

τLX = CLXVbatRPA

Vout= CLX

VbatRPA

βVref(2.30)



A circuit implementing this last equation is presented in chapter 3. It requires the

instantaneous input reference voltage and the values of the indicated design parameters.

An extraction from simulation results is necessary to determine precisely CLX and RPA.

A tracking of the battery voltage variation can be designed but it is not relevant since its

relative variation (from the nominal value 3.6 V to the full charge 5 V and depletion charge

2.7 V) does not exceed 40% and then does not impact too much the actual discharge time.

The approximation leading to eq. 2.30 and the lack of accuracy in the knowledge of CLX

and RPA make the delay slightly dierent from the discharge time. A longer delay increases

body diode conduction whereas a shorter delay causes a partial discharge of CLX by the

synchronous switch but both cause negligible power dissipation.

This adaptive dead-time control cannot eliminate completely the body diode conduction

but highly attenuates its related power losses.

2.2.4.2 Optimization of dead-time td1

Since this dead-time is independent of load condition, it does not need an adaptive control.

Instead the delay is xed to avoid a cross-conduction of the power transistors. Because of

loop delay, a feedback scheme with a sense of LX node is not possible at very high frequency

even if this is a more reliable way to prevent cross-conduction. Here again is the dilemma

between safety and eectiveness.

A practical value for td1 is the rise/fall time of the gate voltage of power transistors:

td1 = tr,f (2.31)

2.2.4.3 Power transistors control signals

The input signals of the power transistors drivers are generated from the PWM signal by

the logic circuit depicted in Fig. 2.17. This circuit is simple and involves few components.

It is assumed that the drivers are matched and thus have the same delay.

For very low duty cycle, i.e. small output current, the circuit generates unwanted pulses

because the dead-time becomes longer than the high-side switch pulse duration. Another

nonoverlapping scheme must handle small duty cycle with a xed dead-time, just enough to

avoid cross-conduction and the discharge of CLX by the low-side switch. Anyway the energy

losses resulting from body diode conduction is low for small load current.

2.2.5 Eciency analysis

The increase of switching frequency leads to higher power losses even with shrinked

devices. Indeed the optimal power transistors width hence the gate capacitance decreases by1√fs

but the switching losses proportional to switching frequency making the overall power



(a) block-diagram (b) waveforms

Fig. 2.17. Dead-time control

losses to increase as showed by eq. 2.32.

Psw = fsCMOSV2DD ∝ fs

1√fsV 2DD =

√fsV

2DD (2.32)

For a power transistor both switching and ohmic losses at the optimal load current are

obtained using eqs. 2.20 and 2.21.

PΩ = WoptR0onI

2RMS = VDDIRMS

√R0onC

0swfs (2.33)

Psw = WoptfsC0swV

2DD = VDDIRMS

√R0onC

0swfs (2.34)

The switching losses due to the driver must be incorporated since the driver brings an

extra capacitance to the gate capacitance. This extra capacitance is computed by considering

the total width of the driver stages:

Wdriver =N∑i=1

Wopt

ai=Wopt

e

1− e−N

1− e−1≈ 0.6Wopt (2.35)

with N and a given by eq. 2.23. The approximation of eq. 2.35 assumes N ≥ 2, which is

usually the case, and shows that the driver adds a capacitance of nearly 60% of that of the

power transistor itself. Therefore the total power losses of a power transistor are:

Ptrans = PΩ + 1.6Psw = 2.6VDDIRMS

√R0onC

0swfs (2.36)

The intrinsic power losses of the SMPS is two times P trans and can be used to determine

the intrinsic maximum eciency for an SMPS output power, P out:

ηopt =Pout

Pout + 2Ptrans=

VoutIout

VoutIout + 5.2VDDIRMS

√R0onC

0swfs

(2.37)

Eq. 2.37 indicates that the intrinsic maximum eciency depends only on the time con-



100

101

10265

70

75

80

85

90

95

100

Switching frequency (MHz)

Eff

icie

ncy

(%)

0.25−µm BiCMOS (NLDEMOS)0.25−µm BiCMOS (Standard)90n−CMOS65n−CMOS

Fig. 2.18. CMOS technologies eciency comparison for Vout=1 V and Iout=500 mA

0 20 40 60 80 100−14

−12

−10

−8

−6

−4

−2

0

← ∆η=−1/8*∆f/f

η (%)

∆η (

%)

Fig. 2.19. Eciency drop due to switching frequency increase

stant τ = R0onC

0sw of the technology node and is enhanced with process shrinking as illus-

trated by Fig. 2.18. As this time constant shrinks with process, the eciency is always high

with advanced CMOS technologies but the drawback is the maximum voltage that can be

handled with such technologies which is low compared to the battery voltage in portable

devices.

With the same technology node an increase of the switching frequency results in a decrease

of the intrinsic maximum eciency that is worthwhile to determine when considering to

switch at a frequency higher than the optimum specied previously. The eciency variation

∆η derived from eq. 2.37 is a good metric to estimate the eciency penalty due to frequency

increase (see eq. 2.38).

∆η = −1

2η(1− η)

∆fsfs

(2.38)

∆fs is the dierence between the new switching frequency and the original switching

frequency f s where the eciency is η. As shown in Fig. 2.19 the eciency penalty is small

when the original eciency is already high.

The eciency analysis done in this subsection does not take into account the ohmic

losses of the series resistance of the inductor because they are not intrinsic to the DC/DC



converter but rather depends on the choice of the inductor process. As discussed in chapter

5 commercial surface-mounted inductors exhibits series resistance very low compared to

transistors channel resistance, unlike integrated inductors whose series resistance is usually

high. Power losses due to body diode conduction are also excluded because they can be kept

negligible with an appropriate control of dead-time.

2.3 Methodology summary

The methodology developed in this chapter is formal and almost independent of the

actual technology used to implement the converter. The specications for some modern

wideband standards have been presented.

A practical usage and implementation of this methodology is given in the next chapter

with a CMOS technology.


Chapter 3

Design of the SMPS in CMOS

Overview

3.1 Preliminary optimization for WCDMA standard . . . . . . . . 45

3.2 Control circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.3 Dead-time controller . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.4 Power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.5 Assembling and layout . . . . . . . . . . . . . . . . . . . . . . . . 56

3.6 Top-level simulation results . . . . . . . . . . . . . . . . . . . . . 61

3.7 Measurements results . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.8 Discussion and conclusion . . . . . . . . . . . . . . . . . . . . . . 75

The design of a buck converter for WCDMA standard in 0.25-µm BiCMOS process is

presented here to illustrate the methodology developed in the chapter 2. This technology

is used to design the RF PA to be fed by the DC/DC converter. It is therefore crucial

that the DC/DC converter be designed with the same technology for integration purpose.

Each subcircuit is designed according to the specications of chapter 2. The appropriate

devices are used for each block in order to take advantage of the features of the fabrication

process that provides bipolar, standard MOSFETs and drain-extension transistors. More

precisely most circuits are designed with a combination of bipolar transistors and standard

MOSFETs. For this reason the supply voltage of these blocks is xed to 2.5 V (Fig. 3.1).

Only the power stage is fed with battery voltage and requires high-voltage devices. The last

section of the chapter deals with measurement results and the comparison with simulation.

3.1 Preliminary optimization for WCDMA standard

A quick determination of WCDMA specications gives the gures in Tab. 3.1. To

further decrease the size of lter components the switching frequency is set to 200 MHz.

With the switching frequency almost doubled, the new optimal inductance and capacitance


Chapter 3 : Design of the SMPS in CMOS

Fig. 3.1. Block-diagram of the SMPS

Inputs parameters Outputs parameters

RPA Large signal Small signal Voutmax L C Fs Ioutmax

(Ω) BW(MHz) BW (MHz) (V) (nH) (nF) (MHz) (mA)

6.9 3.84 15 3 200 8.6 107 434

Tab. 3.1. Buck converter specications for WCDMA standard

are 100 nH and 4.3 nF respectively. The actual lter is implemented with commercial SMDs

and has 51 nH and 4.7 nF. Consequently the poles and zeros of the controller (Fig. 3.2) are

placed according to this LC lter.

The maximum ripple current resulting from this switching frequency and this inductance

is ∆I = 88 mA, assuming a battery nominal voltage of 3.6 V. This ripple current is not too

high compared to the maximum output current.

3.2 Control circuit

3.2.1 Controller

The controller is designed as depicted in Fig. 3.2 using an op-amp and RC tanks. The

pole and zero frequencies of eq. 2.17 are given by RC combinations and therefore can be

used to compute the values of resistance and capacitance according to eq. 3.1 with a degree


3.2 Control circuit

Fig. 3.2. PID controller

of freedom on Cint:

Rint = 12πfp1CintA0

Rdrv = 12πfz1Cint

R3 = Rint1

1+fp2fz2

Cdrv = 12πfp2R3

Rdiv = Rint

β−1

(3.1)

The pole at origin is not located exactly at DC frequency but at fp1 because of the

nite DC gain A0 of the op-amp. However the variation of the fabrication process causes

an unpredictable shift of the resistance and the capacitance. Therefore the actual poles

and zeros may be placed somewhere else than the desired frequency. The robustness of the

controller should then be checked through a Monte Carlo simulations where process corners

are varied according to the Monte Carlo's scheme.

3.2.1.1 Operational amplier

The op-amp must have sucient gain and bandwidth to make sure that its intrinsic

nondominant poles frequencies are higher than fz1, fz2 and fp2, and therefore do not inuence

the low frequency behavior of the controller. Consequently the op-amp gain should be above

the gain of the ideal controller (eq. 2.17) for any frequency up to fp2. However it must be

small at the switching frequency because the ripple on the feedback voltage should not be

amplied by the controller. Thus the gain-bandwidth product is bounded by a minimum

of 2πfp2 · |Hctrl(fp2)| and a maximum of 2πFs · |Hctrl(fp2)|. The actual controller exhibits

a third pole at the intersect of the op-amp and the ideal controller transfer functions (Fig.

3.3).

A high DC gain is needed for a sucient regulation of the output voltage, without of

course sacricing the bandwidth. In CMOS circuit design a high DC gain is achieved usually

with telescopic op-amp which exhibits low output voltage swing. The folded-cascode op-amp



101

102

103

104

105

106

107

108

109

−100

−80

−60

−40

−20

0

20

40

60

80

100

Mag

nitu

de (

dB)

Frequency (Hz)

Open−loop

Op−amp

Actual controller

Fp1

Fig. 3.3. Bode diagram of the operational amplier and the actual controller

(Fig. 3.4) is a good candidate as its DC gain and bandwidth can be tuned independently

unlike the basic amplier [39].

In this work we choose a folded-cascode amplier that combines both bipolar and CMOS

devices. The input pair consists of two P-type bipolar transistors that achieve higher

transconductance than MOSFETs for the same bias current [40]. A common source output

stage is added to the folded-cascode amplier in order to decrease the output impedance.

The overall DC gain after simulation is 90 dB and the GBW is 700 MHz for 470µW of power

consumption.

3.2.1.2 Stability analysis

The stability criteria dened in chapter 2 are checked on the basis of a linear model

including the controller, the output lter and the linear model of the pulse-width modulator

and the power stage (Fig. 3.5). The system consists of two loops: the main loop goes from

the output of DC/DC converter to the input of the controller, FB, and the secondary loop is

the local feedback of the op-amp performed by Rdrv and Cint. An interesting stability analysis

function called lstb is provided by the IC simulator Eldo. Stability analysis is performed

by the insertion of an AC voltage source in the target loop during an AC simulation. The

advantage of this function is to keep the same impedance at each side of the loop breaking

point.

When performed on the main loop of Fig. 3.5 the lstb function gives the open-loop

transfer function of Fig. 3.6. A phase margin of 490 is obtained at the unit-gain frequency of

24 MHz; this results in a delay margin of 5.6 ns which is higher than the 550 ps delay of the


3.2 Control circuit

Fig. 3.4. Folded-cascode amplier

(a) Simulation schematic

(b) Main loop (c) Secondary loop

Fig. 3.5. Linear model used for the stability analysis



-120.0

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80.0

100.0

120.0

140.0

Mag

nitu

de (

dB)

-340.0-320.0

-300.0

-280.0

-260.0

-240.0

-220.0

-200.0

-180.0

-160.0

-140.0

-120.0

-100.0

-80.0

-60.0

-40.0

-20.0

0.0

Pha

se (

degr

ees)

Gain Margin : 40.061 dB

0 dB

Gain Crossover : 24.979 MEGHz

Phase Margin : 49.175 degrees

Phase Crossover : 522.67 MEGHz

db(LSTB)

cphase(LSTB)

1.0 10.03 100.030 1.0K300 10.0K3 100.0K30 1.0MEG300 10.0MEG3 100.0MEG30 1.0G300 10.0G3

Frequency (Hz)1.0

Fig. 3.6. Open-loop transfer function of the main loop

Fig. 3.7. Nyquist diagram of the open-loop transfer function

power stage. Though a 40 dB gain margin is indicated on the Bode diagram, the magnitude

margin found with the Nyquist diagram is only 0.8, which is yet sucient (Fig. 3.7).

Though the stability criteria are fullled, only transient simulations are close to the actual

operating condition of the system. Thus transient simulations of the whole circuit including

the power stage and pulse generator have to be performed at process corners to check the

stability against the spread of the fabrication process.

3.2.2 Pulse width modulator (PWM)

3.2.2.1 Ramp signal generator

The ramp signal is obtained by integrating a square-wave voltage from an external clock

thanks to a pass-band lter (Fig. 3.8). In this way a symmetric ramp voltage is generated


3.2 Control circuit

(a) Block-diagram (b) Band pass lter

Fig. 3.8. Ramp generator

independently of the duty ratio of the input clock. The average voltage of the ramp is set

by resistors Rb1 and Rb2 that duplicate the base-emitter voltage of the bipolar transistor.

As discussed in subsection 1.2.1 of chapter 2 a tracking of the battery voltage variation

by the peak-to-peak voltage V ppramp of the ramp is necessary in order to have a constant

PWM gain. Thus a calibration circuit adjusts the peak value of the input pulse according to

the battery voltage by controlling the supply voltage of a buer that is inserted between the

external clock input, CLK, and the pass-band lter. The peak-to-peak voltage of the ramp

is then proportional to the supply voltage V DD,buffer of the buer (eq. 3.2). This technique

is more eective than trimming the resistance Ri or the capacitance Ci. In this way the

battery voltage is continuously monitored and any change is handled.

V ppramp =VDD,buffer2πFsRiCi

(3.2)

In order to prevent the bipolar transistor and the PMOS current source from entering

in their respective ohmic regions and also relax the input voltage swing of the comparator,

the maximum and the minimum voltage of the ramp are limited to 2.2 and 1 V respectively

when the battery voltage is at the maximum value of 4.3 V. The resulting peak-to-peak

ramp voltage and PWM gain are 1.2 V and 3.5 respectively.

3.2.2.2 Comparator

The main requirement of the comparator is the input voltage swing that must cope with

the dynamic range of the ramp. As the ramp signal is shifted toward the 2.5-V supply

voltage an N-type pair forms the input (Fig. 3.9). Like in the design of the op-amp of the

controller, a bipolar input pair is used for high gain and high bandwidth purpose. Another

benet brought by a bipolar pair is the small coupling of the inputs that prevents a leakage

of the HF ramp to the low frequency error signal from the controller.



Fig. 3.9. PWM comparator

Fig. 3.10. Delay cell

A 63 dB DC gain is achieved for a power consumption of 720 µW , and the gain is 51 dB

at 200 MHz. The comparison delay is about 450 ps, which is very small compared to the

delay margin computed in paragraph 3.2.1.2. Pulses as short as 5% of the switching period

can be provided since the PWM signal has less than 100 ps rise/fall time.

3.3 Dead-time controller

A nonoverlapping scheme is applied to avoid a simultaneous conduction of power tran-

sistors during the transition of the PWM signal. The aim of the dead-time controller, which

realize this nonoverlapping, is to manage the two independent dead-times described in para-

graph 2.2.4. The control voltages for both the high-side and the low-side drivers are produced

by logic operations on the PWM signal from the comparator and two delayed copies of this

signal (Fig. 2.17). Signals Vgs,ctrl and Vgs,sync refer to the gate-source voltage of respectively

the control (or high-side) transistor and the synchronous (or low-side) transistor.

The delay cell consists of a chain of inverters with a controlled bias current (Fig. 3.10). A

constant bias current is applied to the inverters of the delay cell that produces td1 whereas a

variable bias current depending on the input reference voltage V ref is applied for td2 thanks

to a transconductance amplier (Fig. 3.11).


3.4 Power stage

Fig. 3.11. Transconductance amplier

An appropriate transconductance is needed for an optimum delay td2 dened by eq. 2.30

in chapter 2. The delay ∆tinv of the chain of inverters is inversely proportional to the bias

current Ibias according to eq. 3.3 where k is a process-dependent factor that is computed by

simulation.

∆tinv =k

Ibias(3.3)

The bias current corresponding to the optimum delay is given by eq. 3.4 and leads to

the required transconductance Gm.

Ibias =kβ

CLXRPAVbatVref = GmVref (3.4)

The transconductance resulting from these design parameters is approximately 100 µS.

The implementation is performed with the resistance Rgm of 10 kΩ and the ratio of 10

between the output transistors of the transconductance amplier.

3.4 Power stage

3.4.1 Power transistors

The standard MOSFETs in 0.25-µm BiCMOS have a breakdown voltage of 2.7 V, which

is below the nominal battery voltage and therefore prevents the use of such devices as power

transistors in the power stage. Bipolar transistors may be a solution but have an on-state

voltage drop of approximately 0.3 V which is too high giving the small operating voltage

range of the converter. The Drain-extension MOSFETs, LDEMOS, provided by the process

appear as the good candidate for the power stage.

A view is presented in Fig. 3.12. The gate-source interface is a standard dielectric and

thus operates at 2.5V. Multiple dopings extend the drain zone and decrease the electric eld

between the gate and the drain silicided contacts. A voltage as high as 15 V can be applied

on the drain with respect to the gate and the source.



Fig. 3.12. Cross section view of a NLDEMOS designed in ST 's 0.25-µm BiCMOS

Both P and N-types drain-extension transistors are available; but as usually the P device

is three times as big as the N device for the same current capability and channel resistance.

For this reason an NLDEMOS is used to implement both hide-side and low-side switches.

Besides this choice saves an extra process mask since the PLDEMOS requires one more layer

than the NLDEMOS.

The optimal width of 7.4 mm is computed using eq. 2.21 with the following inputs:

R0on = 2828 Ω.µm, C0

sw = 1.6 · 2.5 fF/µm, V DD = 2.5 V , F s = 200 MHz , d = 0.5 and

IRMS =√dIload = 306 mA (I load is given by Tab. 3.1). The actual duty cycle is 0.8 but

it would lead to dierent sizes for the low-side and the high-side switches. Instead taking a

duty cycle of 0.5 gives a same size for both switches (slightly dierent from the optimum)

and increases the eciency at low output power.

By the time the test-chip was layouted, power transistors of width of 7 mm were used

instead of the value indicated above.

3.4.2 Driver

The optimal number and sizes of inverters of the driver are determined by the equivalent

gate capacitance of the power transistor and that of the rst inverter (width of 13 and 4 µm

respectively for the PMOS and the NMOS). Both values of capacitance are obtained from

a large signal transient simulation: 17 pF for the gate of the power switch and 42 fF for the

rst inverter. This leads to a 6-stage buer.

The transistors of the hide-side driver are layouted inside an isolated well because they

operate in a oating voltage domain as explained hereafter and therefore cannot share the

same substrate as the those of the low-side driver.

3.4.3 Boostrap supply

With a dual N-type power stage it is necessary to generate a extra voltage level for the

control of the hide-side transistor. A boostrap supply (Fig. 3.13) is designed to ensure the

control of this switch with the appropriate gate-source voltage. When the hide-side switch is

turned on, its source voltage is close to the drain voltage. The gate voltage must therefore be


3.4 Power stage

(a) schematic (b) waveforms

Fig. 3.13. Boostrap supply

higher than the drain voltage by a voltage oset close to V DD. When the hide-side transistor

is turned o, its source is grounded (connected to the LX node) by the low-side transistor;

its driver then clamps the gate to the LX node.

The capacitor Cboost provides the charge required to turn on the transistor and maintains

a supply voltage of Vbuffer,hs ≈ VDD − Vsht ≈ 2.3 V over the driver, with Vsht (≈ 0.2 V )

as the forward voltage across the Schottky diode. At switching time the voltage across the

capacitor Cboost drops by the ratio Cgate/(Cboost +Cgate). In order to have sucient voltage

headroom over the driver during the on-state, Cboost should be at least ten times as large as

the gate capacitance Cgate. But a too large Cboost would make hard to integrate it on-chip,

which is necessary since the fast transients of the switching do not allow to use an external

capacitor connected through bondwires. For this test-chip Cboost is xed to about 300 pF

and costs 220 µm*180 µm; the voltage swing of the hide-side transistor during the on-state

is 2.2 V.

3.4.4 Voltage level-shifter

A voltage level shifter is the interface between the hide-side driver and the dead-time

control because theses two circuits do not share the same supply rails. The signal from

the dead-time controller switches between V DD and the ground whereas the input of the

high-side driver is between the LX voltage and the boostrap voltage V boost.

As the switching frequency becomes very high, it is imperative to have a fast switching

of the output of the level-shifter, i.e. short rise/fall time for the output signal. Conventional

static voltage level-shifters are attractive since they have no DC power consumption. But

they have a slow transient response. Instead a level-shifter with a DC bias provides short

rise/fall time at output with an small power consumption. As shown in Fig. 3.14 it is

basically a dierential pair with an output stage connected between V boost and the LX node.

Though the voltage V boost can be as high as 7 V the top devices experience no voltage stress



Fig. 3.14. Schematic of the voltage level-shifter

thanks to capacitor Cboost which acts as a decoupling capacitor and keeps the dierential

voltage Vboost−VLX almost constant ; only the input pair transistors have their drain voltage

at Vboost − Vgs,pmos = Vbat + Vbuffer,hs − Vgs,pmos = 3.6 + 2.3 − 0.8 = 5.1 V when the high-

side transistor is on. For this reason the input pair is designed with NLDEMOS transistors

and does not require a matching of transistors that is otherwise not easy with NLDEMOS

transistors. The overall DC consumption, 1.2 mW, is negligible when compared to the

hundred of mW due to the switching of the power stage.

Though unnecessary, a voltage level-shifter is inserted in front of the driver of the syn-

chronous switch for delay matching with the driver of the control switch.

3.5 Assembling and layout

The assembly of the dierent blocks of the SMPS requires to take into account the

packaging and test conditions for blocks placement because the converter consists of analog

circuits with a dierent sensitivity to ground noise, delay through interconnects and path

resistance. Parasitic eects such as bond wires inductance and resistance, capacitance due to

bond pads have to be modeled and simulated before validating the SMPS. Their impacts on

the eciency and the stability of the converter can then be estimated. This approach allows

to test the robustness of the system and determine a decoupling strategy. Like PCB and

package parasitics, layout parasistics also need to be checked. Most EDA simulators provide

a Post-Layout Simulation (PLS) that includes a ne modeling of interconnects resistance,

capacitance and inductance as well. This simulation can be performed along with parametric

simulations based on temperature and process spread. For sensitive circuits like op-amps,

the best checking way is still a Monte-Carlo PLS. Yet the bottleneck in the design of the

SMPS remains the layout of the power stage, the placement of the blocks and the ground



Fig. 3.15. Layout of the SMPS

planes connection.

3.5.1 Blocks placement and layout

The priority in block placement goes to the power stage that needs to be very close

to the bond pads in order to minimize the resistance in the current path. Multiple pads

are necessary for power stage input and output pins to decrease both bond wire equivalent

resistance and inductance. Indeed the pulse current of the power stage creates large spikes on

the internal supply voltage when the bond wire equivalent inductance is signicant. Besides

decreasing the bond wire inductance helps to reduce the required decoupling capacitance as

will be discussed in paragraph 3.5.3. Another benet of multiple bond pads is the resulting

low bond wire resistance, so its power dissipation remains small. Usually two or three bond

pads are necessary because a typical bond wire resistance is 100 mΩ which is far from being

negligible when compared to power switches 400 mΩ resistance.

As shown in Fig. 3.15 the power transistors and their drivers are disposed very closely

to the bond pads. The circuits that carry low currents can be placed far away from their

respective pads without a signicant consequence. Only the clock input's 50-Ωtermination

resistor needs to be very close to the bond pads in order to prevent a ground bounce, due

to its large pulse current, near other analog circuits.

Large metal paths are required to access drain and source pins of power transistors.

Fortunately a thick copper layer is available in ST 0.25-µm BiCMOS process and is used for

the routing of all power paths. The parasitic capacitance added by the large interconnects

is very low compared to the transistor intrinsic parasitic capacitance.

The low power logic and analog circuits are layouted and interconnected with bottom

metal layers that are more resistive than the thick copper.

3.5.2 Ground planes connection

The dierence of sensitivity to ground noise requires a global management of ground

planes on-chip and on the test printed circuit board (PCB). The ringings of the supply rail

and the ground plane due to the input pulse current of the power stage are incompatible



Fig. 3.16. Ground planes connection

with the analog circuits and can hardly be handled with a reasonable decoupling. The

approach adopted is to design a separate ground plane for the low power logic and analog

circuits. A supply rail is therefore dedicated to analog circuits and low power logic blocks

while the power stage is connected to the battery voltage and to a secondary ground plane

(Fig. 3.16). Though working under the same voltage (2.5 V) as the analog parts, the low-

side switch's driver is supplied with a separate rail and shares the same ground plane as the

power transistors.

For a good regulation of the output voltage the load's ground plane should be connected

to the controller's ground plane. As the controller and the load are respectively on-chip and

o-chip, the connection of their ground planes is performed through a bond wire. The load

ground plane is therefore dierent from the power stage ground plane in order to prevent

large spikes to appear in the vicinity of the controller. Such ground planes allocation makes

the internal ground plane of the power transistors less disturbed with respect to load ground

plane because the current through the bond wire lbvss1 is nearly constant (and equal to the

lter inductance's current).

3.5.3 Decoupling method

The decoupling of supply voltage is essential for a switching system like the SMPS to

be fully operative and compatible with other circuits sharing the same supply source. For a

buck converter the ringings on supply voltage are caused by the input pulse currents passing

through the parasitic inductance of the PCB and the bond wires. With a fast switching power

stage, the overshoots on internal supply voltage due to the LpdIdtmay be destructive for power

stage transistors. Usually a series of decoupling capacitors are placed on the PCB between



Fig. 3.17. Simulation of the internal supply voltage spikes without an on-chip decoupling

the chip and the battery to decrease the impedance of the PCB's parasitic inductance. Large

SMD capacitors can be used for an ecient decoupling of the supply voltage on the PCB.

But the bottleneck in high frequency decoupling is the bond wire equivalent inductance that

cannot be arbitrarily low. Ultimately a lower limit is xed by the package size and the leads'

length. A typical bond wire equivalent inductance is around 1 nH (for a 1-mm long bond

wire or package lead); this value can vary depending on the type of package. Increasing the

number of bond pads is a way to decrease this inductance but it is not always possible to

allocate more than two pads to a single signal on a complex multipins chip. At 200 MHz

switching frequency that inductance has an impedance of 2.5 Ω (both upper and lower supply

rails are connected through an 1-nH inductance). Fig. 3.17 shows the spikes of the internal

supply voltage due to such inductance for a 200MHz switching frequency and 400 mA load

current, assuming an appropriate decoupling on the PCB. This example shows clearly that

an on-chip decoupling capacitor is necessary for an internal supply voltage integrity.

Two requirements determine the sizing of the on-chip decoupling capacitance: the rst

one is its limited size due to the area penalty and the second one is the damping of the

resonance with bond wire inductance. Because of the poor density of on-chip capacitor,

the decoupling usually takes a very large area on analog circuits. The issue becomes more

complicated with a switching circuit that generates additional noise on the supply voltage.

The resonance of the decoupling capacitor with the bond wire inductance is damped by

inserting a resistor in series with the capacitor. The optimal resistance (eq. 3.5) corresponds

to a maximally at frequency response:

Rs > 2

√2LbondCdec

(3.5)

where Lbond and Cdec are respectively the bond wire equivalent inductance for one supply

pin and the on-chip decoupling capacitance. The capacitance should be suciently high to

guarantee that the resonance frequency is lower than the switching frequency (Fig. 3.18).

In this way the decoupling impedance is dominated by the resistor beyond the resonance

frequency and the input AC current ows through the resistor and the capacitor instead of

owing through the bond wires. This is very convenient because the converter then pulls

only a DC current from the battery and does not therefore bring any signicant noise on



(a) impedance for two dierent on-chip decouplings (b) internal supply voltage

(c) schematic

Fig. 3.18. Decoupling network

the PCB's supply rail. With 1 nH bond wire inductance and 500 pF on-chip capacitance

the optimal series resistance is 4 Ω. The power dissipation due to such a resistance may

be high in heavy load condition and causes a signicant eciency drop. For a 400 mA

load current and an output voltage equals to half the battery voltage (the worst case), the

power dissipated by a 4 Ω series resistance is 160 mW according to eq. 3.6. This represents

more than 20% of the output power for a 3.6 V battery voltage and is too much because

it is higher than the intrinsic power losses such as the switching losses (98 mW) and the

conduction losses (64 mW) of the power transistors.

PRs = RsI2loadd(1− d) (3.6)

The decoupling capacitance must be increased in order to maintain its series resistance

to an acceptable value that satises eq. 3.5. A maximum power dissipation of 40 mW,

for instance, corresponds to a 1 Ω resistance and thus requires a 4 nF on-chip capacitance.

In 0.25-µm BiCMOS technology the area occupied by such a capacitor designed with MIM

capacitors of 5-fF/µm2 density is 0.8 mm2. This surface is at least four times as large as the

power stage of the converter.


3.6 Top-level simulation results

3.5.4 ESD protection

The protection of ICs against Electrostatic Discharge (ESD) is a necessary measure to

guarantee the reliability. In this test-chip, ESD protection is used only on the low power

2.5V part of the pads ring. It cannot be used on the supply nodes connected to battery of

the power stage and the LX node because the switching of the power stage may lead to false

alarms and prevent the correct operation of the SMPS.


The design robustness is veried through top-level simulations where most of the para-

sitics are modeled. For instance the output lter is implemented with commercial surface-

mounted inductor and capacitor that are dierent from the simple devices provided by EDA

tools libraries. Fortunately models provided by manufacturers, either in RLC elements or in

S -parameters format, give accurate details. The simulations performed with these parasitic

eects allow to check the circuit sensitivity to PCB parasitics, temperature and fabrication

process variation.

The integrity of the control signals is preserved as shown in Fig. 3.19 which plots the main

signals of the SMPS for a DC reference signal. Most signals in this gure can be observed

at PCB level except the coil current and the PWM signal. An accurate measure of the coil

current can only be done through a series resistor that creates more power dissipation. Also

probing the PWM signal or the gate voltage of the power transistors brings a large amount

of capacitance on those nodes and impacts the transient performance of the SMPS. Those

nodes are therefore only checked in simulation to ensure that rise and fall times and the

voltage swing are acceptable.

3.6.1 Eciency

The eciency η is dened as the ratio of the power supplied to the load to the total

input power drawn from the battery (eq. 3.7). Although in polar modulation the SMPS

operates with variable output voltage, the eciency analysis is carried out for a DC output

voltage. For a variable reference an average eciency can be computed instead over the

output voltage range [vmin, vmax] according to eq. 3.8.

η =Vout · IoutPbat

(3.7)

ηavg =1

vmax − vmin

vmax∫vmin

η (v) dv (3.8)

The power supplied by the battery consists of the SMPS input power P in = Vbat · Iin, thepower consumption of the drivers P drv = Vbat·Idrv and that of analog circuits P ana = Vbat·Iana



-1.00.0

1.0

2.0

3.0

4.5

Vol

tage

(V

)

-0.20.20.61.01.41.82.22.6

Vol

tage

(V

)

-0.20.20.61.01.4

2.0

Vol

tage

(V

)

260.0M

300.0M

340.0M

400.0M

Cur

rent

(A

)

Vlx

Vgsctrl

Vgssync

Ramp

Verror

PWM

Vout

Vref

IL

4.360U 4.362U 4.364U 4.366U 4.368U 4.370U 4.372U 4.374U 4.376U 4.378UTime (s)

Fig. 3.19. Simulation with layout and PCB parasitic eects

(controller, modulation, dead-time controller, ...). Though the drivers and the analog circuits

are biased with 2.5 V, we take into account the fact that this voltage is generated by an

LDO (not implemented in this test-chip). Hence the resulting power consumption is higher

than what is obtained when 2.5 V is considered.

Since the SMPS is optimized for high output power, the eciency is poor in light load

condition because of the switching losses (Fig. 3.20). At large output power (or output

current) the eciency goes high and is further increased for large duty cycles when the low-

side switch is no longer turned on, thus decreasing the switching losses. The comparison

with the theoretical eciency of an LDO shows a larger eciency for the SMPS despite the

very high switching frequency (Fig. 3.20).

3.6.2 Frequency response

The analysis of the SMPS in frequency domain is an important step in quantifying the

inuence of the variation of the parameters of the LC lter and the controller because of the

fabrication process or the temperature. Moreover it allows a quick check of the consequences

of the arbitrary choices of the designer. But transient simulations must be performed to

validate the impact on the operation of the SMPS.

The lter parameters selected in section 3.1 make the frequency response of the SMPS

to dier from the optimum discussed in chapter 2. Since the damping factor of about 0.5

(resulting from the 51 nH inductance and the 4.7 nF capacitance) is below the optimal value

of 0.7, it is worthwhile to determine the shape of the actual frequency response through

an AC simulation. The plot of Fig. 3.21 shows indeed an increase of the closed-loop gain



50 100 150 200 250 300 350 400 450 5000

10

20

30

40

50

60

70

80

90

Output current (mA)

η (%

)

LDO

SMPS

Low−sideswitch off

Fig. 3.20. Simulated eciency of the buck converter for a 6 Ω load resistance andVbat=3.6 V

around 18 MHz as a consequence of the underdamping of the lter. However the relative

gain variation obtained in transient simulation is negligible from DC up to 10 MHz (Fig.

3.21b). The peak gain around 18 MHz is 4.4 and thus is not too far from the target gain of

β = 3. Besides the largest gain variations occur in a frequency range far beyond the large

signal bandwidth of the WCDMA envelope.

Like the closed-loop gain the group delay is nearly constant in the bandwidth (Fig. 3.21c)

and experiences a relative variation of about 50% only at frequencies beyond the large signal

bandwidth of the envelope. The simulation with the WCDMA envelope shows a correct

amplication of the signal with few distortion (Fig. 3.22).

3.6.3 Duty cycle and output voltage range

The dynamic range of the output voltage i.e. the duty cycle of the LX voltage is a key

parameter for signal integrity. In EER an insucient dynamic range results in a saturation

i.e. a clipping of the output voltage which increases the harmonic distortion. In order to

avoid the clipping of the output voltage, the maximum input reference voltage is limited to

dmaxVbat/β.

Another consequence of insucient output voltage range is the pulse-skipping phenomenon.

Because of the dead-time the duty cycle of the LX voltage is lower than the actual duty cycle

of the PWM signal. When the duty cycle of the PWM signal reaches its maximum value of

about 95%, the corresponding duty cycle for the LX voltage is only about 75% which leads



0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

Vol

tage

(V

)

-180.0-160.0

-140.0

-120.0

-100.0

-80.0

-60.0

-40.0

-20.0

0.0

Pha

se (

degr

ees)

Gain

Phase

100.0K 1.0MEG500300200 10.0MEG5432 100.0MEG50403020

Frequency (Hz)100.0K

(a) AC simulation

106

1070

1

2

3

4

5

Frequency (Hz)

Gai

n

(b) Gain computed from transient simulation

106

1070

5

10

15

20

Frequency (Hz)

τ (n

s)

(c) Delay computed from transient simulation

Fig. 3.21. Simulated frequency response of the SMPS

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

Vol

tage

(V

)

VPA

VREF

1.0U 1.5U 2.0U 2.5U 3.0U 3.5U 4.0U 4.5U 5.0U 5.5U 6.0U 6.5UTime (s)

1.0U

Fig. 3.22. WCDMA envelope tracking


3.7 Measurements results

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Vol

tage

(V

)

0.45612

0.16903

2.56736

0.87428

VPA

VREF

2.5U 3.0U 3.5U 4.0U 4.5U 5.0U 5.5U 6.0U 6.5U 7.0U 7.5U 8.0UTime (s)

C1: 3.84471UC2: 7.37103U (dx = 3.52632U)

2.5U

Fig. 3.23. Simulated output voltage range without pulse-skipping (Vout is top and Vref isbottom

to an output voltage of 0.75Vbat. Therefore a pulse-skipping occurs for any output voltage

above this value.

The pulse-skipping leads to a sub-harmonic switching of the power stage. As a conse-

quence, the ripple noise then increases, as shown in Fig. 3.23 beyond the second cursor. In a

spectral point of view, spurious frequencies localized around 1/2, 1/2, 2/3 ... appears in the

spectrum of the output signal. This may overshadow the benet of high switching frequency

because sub-harmonics spurious frequencies fall in near channels. For signal integrity it is

necessary to keep the output voltage within the dynamic range where pulse-skipping and

voltage clipping do not occur.


The buck converter was tested, unpackaged, on a PCB to which it was connected through

bond wires (Fig. 3.24). Main results obtained from the test chip called PLUTONIUM are

presented in this section. The measurements conditions have a strong inuence on the results

and have been taken into account during top-level simulations before the chip was sent for

fabrication.

3.7.1 Measurements setup

Two kinds of probing are performed during the measurements: the I-V measurements

through volt- and amperemeters, and the observation of input/output signals with an oscil-

loscope and a spectrum analyzer. The I-V measurements are intended for accurate compu-

tation of the eciency and thus require a dedicated amperemeter to determine the current



(a) Test board

(b) Chip connection to the PCB

Fig. 3.24. Measurements board



through each block: the power stage, the control circuit and the load, and a voltmeter for

the output voltage measure. Drivers current is measured separately from the SMPS input

current in order to determine switching losses variation with frequency and drivers supply

voltage.

A large bandwidth oscilloscope, terminated by 50 Ω impedance, is used to probe the LX

node voltage, the output voltage and the clock signal on the PCB because of the relatively

high switching frequency. A sine wave input is used for the clock signal instead of a square

wave that would generate unwanted high frequency harmonics on the PCB in the vicinity

of low-power signal traces such as the reference voltage. As the output voltage exhibits

low ripple voltage, the spectrum analyzer allows to estimate the magnitude of the spurious

frequencies.

All measurements are carried out with a 5.6-Ω resistor substituted to the PA since this

is the closest normalized value to the PA equivalent resistance.

Important notice: A major concern with this test-chip, is the insucient on-chip decou-

pling capacitance, which is only 64 pF and is designed with 15 Ω damping resistance. This

decoupling capacitance is not optimized because the test-chip was sent to fabrication before

the development of the decoupling method presented in the paragraph 3.5.3. The perfor-

mance of the SMPS is then impacted, especially in terms of power eciency, as we will see

it in this section. A large voltage drop and a long settling time of the internal power supply

voltage are also among the consequences of this weak decoupling. These issues lead us to

perform some measurements, such as dead time, in at switching frequencies lower than 200

MHz.

3.7.2 Steady-state measurements

The dynamic range of the output voltage is measured in both open-loop and closed-

loop situations. As discussed in subsection 3.6.3, the dynamic range corresponds to the

output voltage values without any pulse-skipping of the power stage. In our measurements,

a spectrum analyzer is connected to the output of the SMPS and allows to check when

the pulse-skipping occurs because this phenomenon is accompanied by the presence of sub-

harmonics of the switching frequency (200 MHz) in the spectrum of the output voltage.

In open-loop condition with a battery voltage of 3.6 V, a square wave with variable duty

cycle is applied to the clock input of the SMPS (Fig. 3.25). The measured output voltage

can vary between 0.4 V and 2.4 V without any pulse-skipping. Whereas in closed-loop the

dynamic range seems slightly larger. In this case a sawtooth signal of 1 kHz is used as the

reference voltage. The resulting output voltage is shown in Fig. 3.26 where the output goes

from about 0.3 to 2.8 V. Indeed the dynamic range is slightly larger because the controller

imposes the output voltage to track the reference voltage and attenuates the eect of the

pulse-skipping when it occurs.



(a) d=0.2 (b) d=0.55

(c) d=0.75

Fig. 3.25. Input clock (200 MHz) and resulting LX voltage in open-loop condition

Fig. 3.26. Measured output voltage range using a 1 kHz sawtooth reference voltage



(a) Fs=120 MHz

(b) Fs=139 MHz

Fig. 3.27. Reduction of the dead-time with the implemented control

3.7.3 Dynamic measurements

The probing of the output node LX shows an undershoot followed by an overshoot when

the signal goes from low to high because of the oscillation between the bond wires and the

on-chip decoupling capacitor. Although the internal supply node is not probed directly, it

can be seen from the shape of the LX node voltage that the supply voltage drops seriously

when the high-side transistor is switched on (Fig. 3.25c). The issue becomes more evident

with a large load current because the decoupling impedance causes a high drop. Thus it was

not possible to reach very low and large duty cycles, as required by the specications for

WCDMA polar modulation.

Thanks to our dead-time control, the body diode's conduction is reduced though not as

much as we could expect with regards to simulation results. The measures shown in Fig.

3.27a and 3.27b are performed with respectively 120 and 139 MHz of switching frequency,

and not at 200 MHz in order to show clearly the duration of the body diode's conduction.

Two waveforms are displayed: one when the SMPS works with a xed dead-time and another

with a controlled dead-time.

3.7.4 Reference tracking

During measurements, we found an instability of the feedback loop of the SMPS for large

output voltage. Afterwards, simulations, have shown that the instability is due to the local



(a) simulation (b) measure

Fig. 3.28. Output voltage for a 2 MHz sine reference signal

Fig. 3.29. Spectrum of the output voltage for a 2 MHz and 411 mVpp sine voltage

feedback around the error amplier. This issue is partially arranged by decreasing the bias

current of that circuit, hence decreasing the regulation bandwidth of the DC/DC converter.

The SMPS has then been tested with DC and variable reference voltage. The experimen-

tal waveforms observed on the oscilloscope show a good correlation with the simulation as

can be seen in Fig. 3.28. The spurious frequencies are localized around the intermodulation

frequencies of the switching frequency and the reference signal frequency as predicted by the

analysis given in paragraph 2.2.2 (Fig. 3.29). However the spectrum exhibits second and

third order harmonics but they are at least 30 dB below the reference tone.



3.7.5 Measured eciency

The eciency of the SMPS is computed according to eq. 3.7 in DC output voltage

condition, without the pulse-skipping phenomenon. The computation procedure described

in paragraph 3.6.1 corresponds to the raw eciency of the converter taking into account

all subcircuits added for the test. Dierent values of the battery voltage and the supply

voltage of the drivers have been applied in order to check the impact on the eciency.

When compared to the simulation, the measured eciency shows a substantial decrease

for large output current (Fig. 3.30). This is the consequence of the power losses in the

on-chip decoupling. Indeed whereas an on-chip decoupling capacitance of as much as 4

nF is needed because of the bond wire parasitic inductance of about 2 nH, only 64 pF

has been implemented. By the time this test-chip was designed, the on-chip decoupling

capacitance was not selected according to the recommendation made in section 3.5.3. The

series resistance required to damp enough the resonance of this tiny capacitor with the bond

wire is 15 Ω, which is quite high and results in very high ohmic power dissipation. For

instance in simulation we found a power dissipation of 130 mW through this series resistor

when the output power of the SMPS is 820 mW.

Knowing that this ohmic dissipation is only due to an ineective decoupling of the chip

and is thus not part of the intrinsic power dissipation of the SMPS such as the power losses

of the power transistors or the ohmic losses of the lter inductor, we then de-embedded it

from our measurements afterwards. There can be some claims about the fairness of this

approach, but we insist that the decoupling, though necessary, is not a key element of

a SMPS and therefore should not be considered as participant to its eciency. Thus the

simulated eciency is presented in Fig. 3.30 along with the measured eciency in both cases

the dissipation of the decoupling is included and is de-embedded. The dierence between

the de-embedded eciency and the simulated eciency comes from the switching losses

which are lower in measurements, probably because of a lower gate voltage swing than in

simulation. The close correlation of the two curves shows the good accuracy of the Design

Kit and the parasitics models.

3.7.5.1 Eciency variation with battery voltage

In this series of measurements the eciency of the DC/DC converter is measured when

the battery voltage is varied from 3 V (depleted) to 4.3 V (charged). The available output

voltage swing is dierent for each battery voltage because of the large overshoot on the

internal supply voltage node, due to insucient on-chip decoupling capacitance, that makes

it impossible to reach high output voltage. With a battery voltage of 3.6 V the output

voltage cannot be higher than 2.4 V (with a maximum output current of 364 mA, slightly

less than the 440 mA specied). Whereas a maximum output power of about 1300 mW

could be reached with a battery voltage of 4.3 V, it is only about 650 mW when the battery

voltage is 3 V.



0 200 400 600 800 100010

20

30

40

50

60

70

80

90

Output power (mW)

η (%

)

Simulation

De−emb. meas.

Emb. meas.

Fig. 3.30. Comparison of measured and simulated eciencies (Vbat=3.6 V)

0

10

20

30

40

50

60

70

80

90

0 200 400 600 800 1000 1200 1400

Output power (mW)

Effic

ienc

y (%

)

Vbat=3 V Vbat=3.6 V

Vbat=4.3 V

Fig. 3.31. Corrected eciency for dierent battery voltages

Although the supply voltage of the drivers is 2.5 V during all the measurements (on the

PCB), the switching losses increases with the battery voltage. As shown in Fig. 3.31, this

impacts the eciency at low output power for a high battery voltage. The peak eciency is

about 79% and can be higher, like in simulation, if high output power could be reached with

an eective decoupling. Indeed subsequent analyses have shown a close correlation between

the extracted parasitics and the models of the Design Kit.

3.7.5.2 Power dissipation breakdown

The analysis of the eciency curves in the previous section shows a heavy impact of

switching losses, especially from low to medium output power. A breakdown of the total

power loss of the DC/DC converter conrms their overwhelming contribution in this power

range (Fig. 3.32a). Even around 1 W of output power, the switching losses still make about

half of the overall power losses (Fig. 3.32b). This illustrates how dicult it is to design a

power converter that is ecient over a wide range of power.

The ohmic losses in Fig. 3.32 consist of the channel resistance of the power transistors

(Rdson), the series resistance of the inductor (RL) and the bond wires resistance (Rbond).



Pdrivers

Pohmic

12

Rdson

Pdiode

Panalog

•Ploss

=198.66 mW

•η=41.77%

•ηLDO

=39.44%

1:Rbond

2:RL

1 2 3 40

0.1

0.2

0.3

0.4

0.5

0.6

(a) Pout=325 mW (Vout=1.42 V and Iout=229 mA)

Pdrivers

Pohmic

RbondR

L

Rdson

Pdiode

Panalog

•Ploss

=256.83 mW

•η=77.96%

•ηLDO

=64.36%

1 2 3 40

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

(b) Pout=820 mW (Vout=2.32 V and Iout=354 mA)

Fig. 3.32. Breakdown of the total power loss (Ploss) of the SMPS with Vbat=3.6 V

Their contribution is proportional to the output power and determines the eciency at large

output power. But they are not the only contributors of some importance. The conduction

losses of the body-diode during the dead-time, estimated to around 1/10 of the switching

period, is not as low as we found in the simulation.

Analog circuits have a constant power consumption that is very small compared to those

of the other contributors. So there is no reason to make some economy on the bias current

of these circuits, especially the error amplier, the comparator and the ramp generator.

The theoretical eciency of a LDO is given in Fig. 3.32 to show the advantage of the

SMPS, despite its complexity.

3.7.6 Parasitics extraction

The extraction of parasitics is worthwhile because it helps to estimate the accuracy of

Design Kit models and also the approximation made on the models of package and PCB

parasitics. We used dynamic and static tests to determine some relevant parasitics DC

resistance and capacitance respectively. The aim is to improve the quality of the design, the

layout and the test board for subsequent projects.

3.7.6.1 Resistance extraction

The test bench of Fig. 3.33 was designed to determine the channel resistance of the

power transistor, the interconnects resistance and the DC resistance of bond wires. The

synchronous switch is turn-on and operates in the linear region; a xed current source is

substituted to the load resistor. A voltmeter is successively connected in ve dierent con-

gurations (between positions A, B, VSS and Ground) that results in combinations of power

transistor's channel resistance, the bond wire resistance and the series resistance of the in-

ductor. The values obtained are 364 mΩ, 100 mΩ and 75 mΩ respectively for the channel



Fig. 3.33. Test bench designed for parasitic resistance extraction

resistance of the power transistors, the bond wire resistance and the series resistance of the

inductor. The simulation with the Design Kit models gives 366 mΩ for the power transistor's

channel resistance and the datasheet of the Coilcraft surface-mounted inductor indicates a

75 mΩ series DC resistance. The AC resistance cannot be determined with this technique

but it is not relevant because the value given in the datasheet is not signicant.

3.7.6.2 Capacitance extraction

The measure of the drivers' power consumption is a way to estimate the equivalent gate

capacitance of the power transistors. The approach adopted here is based on the linear

variation of this power consumption with the switching frequency (fsCV2). The capacitance

can be determined from the slope of the curve in Fig. 3.34. As discussed in section 2.2, nearly

62% of this capacitance is due to the power transistors and the remain part to the drivers.

This makes a 15.5 pF of gate capacitance for each power transistor, considering a voltage

swing of 2.5 V. The result is close to the 17 pF evaluated by simulation (see paragraph 3.4.2).

The equivalent capacitance on the LX node can be estimated by two ways: either from

the discharge time of this node on the oscilloscope or from the input power of the SMPS at

no load condition. This last technique is more accurate because the discharge is too short,

about few hundreds of ps, to be measured with great accuracy on the oscilloscope. When

the load resistor is disconnected, the input power of SMPS consists of the switching power

losses of the capacitance CLX and the ohmic losses of the channel resistance of the power

transistors due to the ripple current of the lter inductor. These ohmic losses are negligible

(less than 1 mW), so in our case the input power of the SMPS, which is about 47 mW,

consists mainly of the switching losses of the capacitance CLX . With a battery voltage of

about 3.6 V, we found the capacitance CLX approximately equal to 19 pF. This value also

is quite close to 17 pF obtained from the simulation, which is used to design the adaptive


3.8 Discussion and conclusion

y = 0.3101x + 1.6156

0

10

20

30

40

50

60

70

100 120 140 160 180 200 220Switching frequency (MHz)

Switc

hing

loss

es (m

W)

Fig. 3.34. Variation of gate drive losses vs. the switching frequency

dead-time controller.


In this chapter we have demonstrated the practical use of our methodology for the design

of a high-frequency SMPS. The simulation and measurements results come from the rst test-

chip designed during this thesis and therefore as such, does fully follow the recommendation

specied later in the methodology. Yet the results are interesting as they illustrate some key

elements of the design of the SMPS and are useful for future projects on the topic of high


The schematics proposed here to implement the building blocks of the control circuit (er-

ror amplier, ramp generator, dead-time controller, ...) can be improved for more robustness

to temperature, devices mismatch and fabrication process variations. But the design and

the layout of the power stage remain the backbone of the SMPS. While the performance of

the control circuit is improved with a little more power consumption, only a change of archi-

tecture can overcome the fundamental limits in terms of eciency of the conventional power

stage. The aim of the new architecture is to enhance the eciency, especially in light load

condition, while maintaining the high switching frequency and its subsequent advantages.

3.8.1 Eciency improvement

The improvement of the eciency requires the reduction of the main sources of power

dissipation presented in Fig. 3.32. Among these, the switching losses are the most signicant

and are responsible of the low eciency obtained for low output power. In order to decrease

the switching losses, a direct and eective way is to reduce the switched gate capacitance or

the gate voltage swing of the power transistors. The rst technique consists of adjusting the

width of the power transistors according to the operating point. A small width is selected

when the SMPS supplies a low output power, hence decreasing the switching losses. The



Technology 0.25-µm BiCMOS

Switching frequency (MHz) 200

Vin range (V) 3∼4.3

Vout range (V) 0.3∼2.4

Max. output current (mA) 451

Filter inductance (nH) 51

Filter capacitance (nF) 4.7

Eciency max. (%) @ Vin=3.6V 79.15

Chip area including pads 1.6x0.6 mm2

Tab. 3.2. Performance summary of the SMPS

width is increased when a large output power is required. A dynamic control can then be

implemented to select the optimal width by a sense of the output voltage or the output

current.

The second technique consists of decreasing the supply voltage of the drivers from the

nominal voltage of the process. For instance a 10% decrease of the voltage swing leads to

20% decrease of the switching. However the increase of the channel resistance prevents to

decrease the gate voltage swing further.

The approach followed in this work is the recycling of the gate drive energy thanks to a

resonant gate driver that is substituted to the conventional driver. A detailed description of

the resonant gate driver is provided in the next chapter.

A global reduction of the switching losses can combine these three techniques as a single

technique cannot provide a high eciency over a large output power range. Instead the

contribution of multiple strategies can bring an eective solution to the eciency of a HF

DC/DC converter working in variable load condition.

3.8.2 Comparison with previous works

Tab. 3.2 summarizes the performance of the fabricated DC/DC converter. A comparison

with the state-of-the-art is given in Tab. 3.3. The switching frequency is almost the same

as in the previous works cited here, except for [14]. But the input voltage range is very

dierent; indeed these works are designed in low-voltage processes that cannot handle the

battery voltage unlike our converter. Therefore they are not suitable for the supply of a PA.

The eciency gures presented in [20, 33, 32] must also take into account the eciency of

the front module that converts the battery voltage to the input voltage, which impacts the

overall eciency.



Work [20] [33] [14] [32] This

2005 2007 2008 2009 work

Process 90-nm 0.35-µm 0.25-µm 0.18-µm 0.25-µm

CMOS CMOS BiCMOS BiCMOS BiCMOS

F (MHz) 233 200 130 200 200

Vin (V) 1.4 3.3 3.6 1.8 3.6

Vout (V) 1.1 2.3 3.25 0.9 2.4

Iout (mA) 300 60 663 500 380

L (nH) 4x6.8 22 110 2x2.14 51

C (nF) 2.5 2.5 10 2x8.22 4.7

E. (%) 84.5 62 83 64 79

Output C on-chip LC die LC LC LC

lter L o-chip stacked o-chip on-chip o-chip

Tab. 3.3. Comparison with previous works


Chapter 4

Resonant gate drivers

Overview

4.1 Fundamentals of the resonant gate driver . . . . . . . . . . . . . 79

4.2 Design of the resonant gate driver . . . . . . . . . . . . . . . . . 83

4.3 Test-chip design and optimization . . . . . . . . . . . . . . . . . 87

4.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . 94

4.5 Discussion and conclusion . . . . . . . . . . . . . . . . . . . . . . 98

The conclusion of chapter 3 emphasizes the need for a reduction of switching losses when

increasing the switching frequency. Among the proposed solutions the resonant gate drivers

constitute an interesting topic. In this chapter the fundamentals and the design of resonant

gate drivers are explored. A comparison with a conventional driver, i.e. a chain of inverters,

is performed through a test chip designed in 0.25-µm BiCMOS.

4.1 Fundamentals of the resonant gate driver

4.1.1 State-of-the-art

The basic idea of a resonant gate driver is the charge of the gate capacitance of a power

transistor through an inductor instead of a resistor as it is the case in the conventional

driver. In this way no energy dissipation occurs during both charge and discharge unlike to

a conventional driver. Moreover the energy stored into the inductor can be recovered in the

supply source which further increases the eciency of the driver. Indeed when a capacitor

C is charged through an inductor up to a voltage V, an equal amount of energy is stored

in both devices i.e. 0.5CV 2 (Fig. 4.1a). Similarly when the capacitor is discharged from a

voltage V to 0 through an inductor, its energy is transfered to that inductor. The aim in the

design of a resonant gate drive scheme is to transfer to the supply source the energy stored

in the inductor once the capacitor is charged or discharged. Thus theoretically this charge

and discharge process cost no energy to the supply source.


Chapter 4 : Resonant gate drivers

(a) LC prole (b) RC prole

Fig. 4.1. Charge and discharge of a gate equivalent capacitance

When a capacitor is charged through a resistor to a voltage V, the energy dissipated by

this resistor is equal to the energy stored in the capacitor, 0.5CV 2. During the discharge of

the capacitor this energy is also dissipated, which makes a total energy of CV 2 lost by the

supply source (Fig. 4.1b).

Another dierence between the resonant gate driver and the conventional driver is the

waveform of the output voltage, i.e. the voltage applied to the gate of the power transistor.

The LC charge and discharge produce an oscillating voltage that must be clamped to either

the supply voltage or the ground if a quasi-square wave is desired to control the power

transistor, which requires additional switches and causes some power dissipation. In [41] a

sine wave voltage is applied to the gate of the power transistor in a class-E boost DC/DC

converter switching at 50 MHz. The same paper introduces also a resonant gate driver that

produces a quasi-square wave voltage on the gate of the power transistor. The converter

that employs this driver is also a class-E boost DC/DC converter switching at 110 MHz

and achieves 87% eciency. Unfortunately the paper does not provide a gure allowing to

estimate the power saving compared to a conventional driver. A low frequency burst control

is used to regulate the output voltage of the converter which creates a large ripple current and

is hardly compatible with the spurious ltering in polar modulation. The drivers are designed

with multiple inductors and capacitors in the range of tens of nH and nF respectively that

cannot be easily integrated and are in fact on the PCB.

On the opposite the design in [42] is realized with a single inductor and four switches,

forming an H (Fig. 4.2). Mpower is the power transistor that has an equivalent gate

capacitance, Cgate. The charge of this capacitance starts when switches M1 and M2 are

respectively turned on and o. The inductor's current rises as well as the gate voltage of the

power transistor until it is clamped by diode D1 (time t1). Then M1 is turned o and the

current owing through the inductor is directed to the supply source thanks to the diode D1

and the body diode of M2. The discharge of the gate capacitance occurs in a similar way;

M2 is turned on and the energy of the gate capacitance is transferred to the inductor. When

the gate capacitance is fully discharged (time t2), M2 is turned o and the inductor's current

is directed to the supply source through D2 and the body diode of M1. Compared to [41]

the driver's schematic is more simple and the gate voltage is a quasi-square waveform like in


4.1 Fundamentals of the resonant gate driver

(a) schematic (b) waveforms

Fig. 4.2. Resonant gate driver

Fig. 4.3. Proposed resonant gate driver

a conventional driver. A gate drive loss reduction of 45% is reported in [42] with respect to

a conventional driver with 500 kHz of switching frequency and 470 nH of inductance. The

circuit is designed with discrete components on a PCB.

The approach followed in this work is based on a modied version of the schematic of Fig.

4.2. Indeed the diodes D1 and D2 have a forward voltage drop of about 0.7 to 1 V that is

not too signicant when the supply voltage is 5 V as in [42] but is no longer negligible when

a low-voltage CMOS process is considered. Thus a new schematic is proposed where the

diodes are replaced by transistors that provide lower voltage drop during conduction (Fig.

4.3). The principle of operation is described in paragraph 4.1.2. Similar schematics are also

proposed in [43, 44] but apply dierent control sequences and are switched only at 1 MHz.

The impact of the control sequence on the driver's eciency is discussed in section 4.2. As

much as 70% and 24.8% switching loss reduction are reported in [43] and [44] respectively.

4.1.2 Principle of operation

The operation of the proposed resonant gate driver is similar to that of [42] cited previ-

ously, with a dierence due to the control of transistors M3 and M4 that are substituted to

the diodes. A waveform diagram depicted in Fig. 4.4 shows the circuit operation along with

the switches conduction times.

Starting with the power device turned o with its gate voltage clamped to ground voltage

by M4, the charge of the gate begins at t0 when M1 and M4 are respectively turned on and



Fig. 4.4. Waveforms of the proposed resonant gate driver

o, with M2 and M3 remaining o. The transistor M1 is maintained on from t0 to t1 during

which the gate is charged to the supply voltage V DD through the inductor. At t1, M1 is

turned o and M3 is turned on in order to clamp the gate to the supply rail. The inductor's

current then ows to the supply source through M3 and the body diode of M2 from t1 to t2.

Let's note that this electromagnetic energy is equal to the energy of the gate capacitance.

The time interval from t2 to t3 corresponds to the power transistor's on-time.

The discharge of the gate starts when M3 is turned o and M2 turned on. The energy

stored in the gate capacitance is transferred to the inductor from t3 to t4. Once the gate

is fully discharged, M2 and M4 are respectively turned o and on. The energy acquired by

the inductor from the gate capacitance is transferred to the supply source through M4 and

the body diode of M1 from t4 to t5. M4 remains in on-state in order to clamp the gate to

ground voltage during the power transistor's o-time (Fig. 4.4).

The on-time of M1 and M2 is equal to the gate voltage rise/fall time tr,f and can be

computed from the inductor's current expression:

iLR (t) = VDD

√CgateLR

sin

(t√

LRCgate

)(4.1)

tr,f =π

2

√LRCgate (4.2)

The channel resistance of M1-4, the series resistance of the inductance and the gate access

resistance introduce some discrepancies in the charge and discharge proles, and cause also


4.2 Design of the resonant gate driver

some ohmic power losses. In order to maintain a resonant drive of the gate, it is necessary

to x the characteristic impedance of the LC circuit, Z0 (eq. 4.3) largely above the total

resistance in series with the inductor.

Z0 =

√LRCgate

(4.3)

The inuence of Z0 on the eciency of the resonant gate driver compared to the conven-

tional driver is discussed in next section. But it already appears that while a large inductance

is required for an ecient drive, it also increases the transition time of the gate voltage and

ultimately limits the achievable duty cycle range.


The design of an optimal resonant gate driver requires a careful analysis of the power

loss mechanisms and the trade-o between velocity and eciency. Unlike the previous works

that operate at relatively low frequency, timing issues and additional switching losses become

critical with switching frequencies in the range considered in this thesis, i.e. above 100 MHz.

Therefore modeling the power losses and evaluating timing mismatch impacts on the energy

recovery are essential to optimize the resonant gate driver.

4.2.1 Modeling of the power losses

The energy dissipation in the resonant gate driver occurs in two ways: conduction and

switching. The rst one is due to the channel resistance of the switches, the series resistance

of the inductor, the gate access resistance and the conduction of the body diodes; while the

second ones is the gate drive loss of switches M1-4. Like the power transistor in chapter

2, the sizing of the these switches requires the determination of their RMS currents from

the conduction diagram (Fig. 4.5) and using the eq. 2.21. The overall power loss of one

transistor is computed from eq. 2.36. Tab. 4.1 summarizes the power loss of each device

or parasitic element of the resonant gate driver including the conduction losses of the series

resistance RLR of the inductor, the gate access resistance Rg and body diodes BD1 and BD2.

All currents listed in the second column are RMS except for the current of the body diodes

(average current).

A quick analysis of Tab. 4.1 shows that all power losses decrease with the characteristic

impedance, i.e. the resonant inductance for a given gate capacitance. Also power losses of

the body diodes become signicant with low-voltage CMOS devices as the forward voltage

drop of the diodes, V d (≈ 0.7V ) is no longer negligible compared to the supply voltage V DD

(2.5 V in our case). As will be discussed in the next paragraph, increasing the resonant

inductance costs some penalties. A fair optimization of the resonant gate driver means to

compare its overall power loss to that of the conventional driver. It is the only basis that



Fig. 4.5. Conduction diagram of driver's components

Device Current Width Power loss

M1-M2 VDD

2

√πfsCgate

Z0

√πR0

onCgate

4C0swZ0

1.3V 2DDfs

√πR0

onC0swCgate

Z0

M3-M4 VDD

√VDDfsCgate

3(VDD+Vd)Z0

√VDDR0

onCgate

3C0sw(VDD+Vd)Z0

2.6V 2DDfs

√VDDR0

onC0swCgate

3(VDD+Vd)Z0

BD1-BD2V 2DDfsCgate

2(VDD+Vd)(average) -

VdV2DDfsCgate

2(VDD+Vd)

RLR VDD

√fsCgate(7VDD+3Vd)

6(VDD+Vd)Z0- RLR

V 2DDfsCgate(7VDD+3Vd)

6(VDD+Vd)Z0

Rg VDD

√πfsCgate

2Z0- Rg

πV 2DDfsCgate

2Z0

Tab. 4.1. Resonant gate driver's power dissipation

may possibly justify the use of such a complex circuit instead of a simple buer. In fact the

optimization consists of nding a resonant inductance that leads to lower power dissipation

with respect to a conventional driver because this is the only variable in the table that can

be tuned.

4.2.2 Comparison with a conventional driver

The criterion used to compare both types of driver and quantify the relative eciency of

the resonant gate driver, is the relative power saving:

ηrel = 1− Ploss,resPloss,conv

(4.4)



where P loss,res and P loss,conv are the power losses of respectively the resonant gate driver and

the conventional driver, given by:

Ploss,res = 2.6V 2DDfs

√πR0

onC0swCgateZ0

+ 5.2V 2DDfs

√VDDR0

onC0swCgate

3 (VDD + Vd)Z0

+VdV

2DDfsCgate

VDD + Vd+RLR

V 2DDfsCgate (7VDD + 3Vd)

6 (VDD + Vd)Z0

+RgπV 2

DDfsCgate2Z0

(4.5)

Ploss,conv = 1.6fsCgateV2DD (4.6)

When reporting eqs. 4.5 and 4.6 into eq. 4.4, the relative eciency of the resonant gate

driver can be expressed as:

ηrel = 1− 1.6

√πR0

onC0sw√

LRCgate− 3.25

√VDDR0

onC0sw

3 (VDD + Vd)√LRCgate

− Vd1.6 (VDD + Vd)

−RLR7VDD + 3Vd

9.6 (VDD + Vd)

√CgateLR− π

3.2Rg

√CgateLR

(4.7)

This model (eq. 4.7) is used in this work to design the resonant gate driver. It allows

to determine the contribution of the power dissipation sources to the degradation of the

eciency of the driver. The second and third terms of the equation correspond to the switches

M1-4 power dissipation and are the main contributors. While those two contributions can be

lowered by increasing the resonant inductance for a given gate capacitance, the fourth term

relates to the body diode conduction losses which are independent of the resonant inductance

and may become predominant for low supply voltage. But increasing the resonant inductance

also increases the contribution of the conduction losses of its series resistance which is roughly

proportional to the inductance value for an integrated air-core inductor, RLR = a · LR. A

typical value of a for an inductor realized with a thick copper layer is 250 mΩ/nH. The last

term is the contribution of the gate access resistance that can be minimized by an appropriate

layout of the circuit. It is the least important contributor.

Another consequence of eq. 4.7 is that the resonant gate driver is ecient when the gate

capacitance is signicant. Otherwise the inductance has to be high in order to achieve a

reasonable eciency as can be seen in Fig. 4.6 that plots the eciency of the resonant gate

driver compared to a conventional driver as function of the resonant inductance and the gate

capacitance. It is assumed that the series resistance is proportional to the inductance and a

1 Ω gate access resistance is considered.

A practical use of the model is performed in section 4.3 for a HF DC/DC converter.



02

46

810

010

2030

4050

−10

0

10

20

30

40

50

LR

(nH)Cgate

(pF)

η (%

)

−5

0

5

10

15

20

25

30

35

40

Fig. 4.6. Relative eciency of the resonant gate driver vs. the conventional driver

4.2.3 Duty range and switching frequency limitation

The enhancement of the eciency of the resonant gate driver by increasing the resonant

inductance, leads to a long rise/fall time of the gate voltage of the power transistor as

predicted by eq. 4.2 and illustrated in Fig. 4.8. As demonstrated by eq. 2.24 in chapter 2,

the rise and fall times set the minimum achievable duty cycle and therefore the switching

period must be large enough in order to have a large duty cycle range. This means that the

switching frequency is limited by the desired duty cycle range.

The issue can be approached from the other side: for a given switching frequency, the

desired duty cycle range determines a limit to the resonant inductance and therefore the

achievable eciency. This is one inconvenient of the resonant gate driver because the ef-

ciency comes at the cost of the duty cycle range unlike to the conventional driver. For

instance, a 40% relative eciency in Fig. 4.6 corresponds to about 620 ps of rise/fall time in

Fig. 4.8. If a 10% minimum duty cycle must be achieved then the switching period should

be 12.4 ns (from eq. 2.24), i.e. a switching frequency of 80.64 MHz.

For a given switching frequency (and thus a given power transistor gate capacitance from

eq. 2.21) a targeted duty cycle range constraints the value of the rise/fall time (eq. 4.2).

This yields the resonant inductance value hence the achievable relative eciency. Fig. 4.7

plots the achievable relative eciency with respect to the switching frequency and targeted

duty cycle range. The reduction in switching losses is higher when the duty cycle range is

smaller. The resonant gate driver will give the maximum benet for xed voltage regulator

than large voltage-range regulator, i.e. the application discussed here.

In applications like EER where a large duty cycle range is required, the minimum duty


4.3 Test-chip design and optimization

50 100 150 200 250 3000

10

20

30

40

50

Fs (MHz)

Red

ucti

on r

atio

(%

)

dmin

=10%

15%

20%

LR

=2.4nH

8nH

34nH

Fig. 4.7. Relative eciency of the resonant gate driver vs. the switching frequency

cycle determines the allowable rise/fall time of the gate to source of the power transistors.

Therefore the optimization of the DC/DC converter and its resonant gate drivers must take

this requirement into account when selecting a resonant inductance.


A buck converter using resonant gate drivers has been designed to demonstrate the theory

developed in this chapter. The aim is to illustrate the design methodology presented here

in a practical case and a comparison with a conventional driver. For a fair comparison the

resonant gate driver is used in a buck converter with the same features as that presented

in chapter 3, i.e. the switching frequency, the controller, the pulse-width modulator, the

adaptive dead-time controller, the LC lter and the power transistors are identical.

This section presents the optimization of the resonant inductor for a switching frequency

of 200 MHz, the design of the control circuits of the switches of the resonant gate drivers,

the simulation results and the layout of the drivers along with the buck converter. Unlike

the previous works on resonant gate driver, this work aims to design resonant gate drivers,

including resonant inductors, integrated on-chip with the power transistors.

4.3.1 Optimization of the resonant inductor

The selection of a resonant inductance depends on the requirement on the duty cycle range

and the targeted eciency of the driver. As those two constraints are opposite, a trade-o



02

46

810

010

2030

4050

0

200

400

600

800

1000

1200

LR

(nH)Cgate

(pF)

t r,f (

ps)

200

300

400

500

600

700

800

900

1000

1100

Fig. 4.8. Rise/fall time of the gate voltage of the power transistor

becomes necessary to satisfy the duty cycle requirement while still achieving an acceptable

eciency that may justify the area penalty due to the integrated resonant inductors. This

area penalty is also a concern and prevents to use large inductors even in the case of a weak

duty cycle requirement.

In our case, with 17 pF of power transistor gate capacitance (paragraph 3.4.2) and 5 ns of

switching period as input parameters, a 30% relative eciency are interesting since it leads

to a 3.4 nH resonant inductance (Fig. 4.9a) and about 370 ps of rise/fall time, i.e. a 15%

minimum duty cycle (Fig. 4.9b). Compared to a conventional driver, this rise/fall time is

higher and results in a smaller duty cycle range, but it is necessary to guarantee a sucient

resonant inductance for eciency purpose. A relative eciency higher than 30% could be

obtained but at the cost limited duty cycle range.

4.3.2 Control of the switches of the driver

The substitution of transistors M3 and M4 to diodes D1 and D2 in Fig. 4.2, makes

the control of the driver less simple. Two more gate signals have to be generated by the

control circuit, and this requires an accurate timing control to avoid a cross-conduction of

two transistors activated just one after the other. Besides the logic equations of the gate

voltage of the transistors M1-4, the timing mismatch through their respective buers is also

a key factor for a successful energy recovery of the resonant gate driver. When the gate

of the power transistor is grounded by M4, it is necessary to turn o this transistor before

M1 is activated otherwise a portion of the coil's energy is wasted in M4's channel resistance

instead of being directed to the gate capacitor. In the same way when the gate voltage is



1 2 3 4 5 6 7 8 9 105

10

15

20

25

30

35

40

45

LR

(nH)

η (%

)

(a) Eciency of the driver

1 2 3 4 5 6 7 8 9 10200

250

300

350

400

450

500

550

600

650

LR

(nH)

t r,f (

ps)

(b) Transition time of the gate voltage

Fig. 4.9. Eciency and gate voltage rise/fall time for 17 pF of gate capacitance

Fig. 4.10. Control signals of M1-4

clamped to the supply voltage by M3, this device must be switched o before M2 is switched

on. This timing mismatch is obtained by adding in the buers of M3 and M4 two or more

extra inverter stages compared to those of M1 and M2.

The logic equations of the gate voltage of M1-4 are extracted from the timing diagram

in Fig. 4.10 and are presented in Tab. 4.2 with the size of devices computed from Tab.

4.1. The signal referred to as PWM, is the output of the voltage level-shifter introduced in

chapter 3. It is delayed by a time equal to tr,f (eq. 4.2) through a circuit identical to the

delay cell presented in section 3.3.

4.3.3 Layout

The layout of the power transistors and the controller of the buck converter using resonant

gate drivers is identical to that of the conventional buck converter as presented in chapter



Switch Width (µm) Control signal

M1 1050 PWM + PWMdelay


M3 608 PWM · PWMdelay


Tab. 4.2. Logic equations and size of switches M1-4

3. Due to the large area of the resonant inductors, the drivers are layouted in such a way

to minimize the parasitic eects on-chip that may aect their correct operation or their

performance. Among such parasitic eects is the distance between the resonant inductor,

the switches M1-4 and the gate of the power transistor that results in an additional series

resistance and gate resistance. Because of the size of the resonant inductors, it is hardly

possible to have short paths; but the total resistance can be minimized by using a wide thick

metal routing and possibly a stack of available interconnect metal layers. The parasitics of

the inductors are a major concern as they impact not only the eciency of the driver, but

also its frequency characteristics. A proper handling of their eects requires a careful layout

of the inductor.

4.3.3.1 Layout of the resonant inductor

The inductance of 3.4 nH selected in paragraph 4.3.1 is low enough for an on-chip inte-

gration. The priority is for a compact and low series resistance topology and thanks to a

tool SELF developed at STMicroelectronics, it is possible to compare the dierent air-core

planar inductor topologies such as square, circular and octagon spirals. A second require-

ment to take into account involves the coupling to the substrate through parasitic capacitors

and the interwinding capacitors. For this reason the spacing of spirals must be sucient and

the rst (or the two rst) metal layer should not be used as they have the highest coupling

capacitance to the substrate. The thick metal layers can be stacked to achieve a low series

resistance without too much impact on the substrate coupling.

Fortunately the tool SELF oers a great exibility of tuning and produces the series

resistance, the frequency of the resonance due to the parasitic capacitors, the Spice model

and the layout of the inductor. As the current through the inductor is pulse-shaped and thus

has many harmonics content, the resonant frequency due to the parasitic capacitors must be

at least higher than the tenth harmonics of the switching frequency of the buck converter.

It is important to shield the inductor by providing a low impedance path to the current

through the substrate coupling capacitors. This is done by connecting the substrate beneath

the inductor to the ground plane of the chip.

The actual resonant inductor designed for this test-chip is shown in Fig. 4.11. It has 8

nH of inductance and 1.5 Ω of series resistance for a size of 400 µm*400 µm. This choice is

dictated by eciency consideration but it sacrices somewhat the duty cycle range.



Fig. 4.11. Resonant inductor with shielding

Fig. 4.12. Layout of the buck converter

4.3.3.2 Assembly of the buck converter

The assembly of the buck converter using resonant gate drivers is similar to that of the

conventional buck converter, except for the placement of the resonant inductors. In order to

limit eddy currents, no metal line passes beneath the inductors. Therefore the area occupied

by the inductors is free of metal dummies. The routing resistance from the power transistors

to the inductors is decreased thanks to wide interconnect metals that bring nearly 1 Ω extra

series resistance.

The overall size of the converter is almost doubled by the inductors. A 1200 µm*1000

µm area is occupied though much empty space exists between the blocks (Fig. 4.12).

4.3.4 Simulation results

The main features of the buck converter using resonant gate drivers are checked in sim-

ulation in the same way as that in chapter 3 using conventional drivers. This paragraph

presents the relative eciency obtained in simulation and how close it is to the prediction

of the model in paragraph 4.3.1. As with the conventional buck converter, features such

as output voltage range and regulation bandwidth are important and have been estimated



150 200 250 300 35060

70

80

90

100

110

120

Output current (mA)

Swic

hing

loss

es (

mW

)

Conventional

Resonant

(a) Switching losses of SMPSs

150 200 250 300 3500

5

10

15

20

25

30

35

40

Output current (mA)

η (%

)

(b) Relative eciency of the resonant gatedrivers

Fig. 4.13. Switching losses and the reduction due to resonant gate drivers

during the simulation.

4.3.4.1 Relative eciency of the resonant gate driver

A relative eciency of 40% is predicted by the model with the selected resonant induc-

tance of 8 nH (Fig. 4.9). The simulation shows a good correlation with this prediction since

the switching losses are reduced by more than 35% over the SMPS output current range as

shown in Fig. 4.13. When compared to the conventional buck converter, the global eciency

is improved by as much as 5% in light to medium load conditions which are dominated by

the switching losses as mentioned in chapter 3 (Fig. 4.14). At large load current both con-

verters, exhibit nearly the same eciency because the total losses become dominated by the

ohmic losses which should be the same since the converters have identical power transistors.

For SMPS output current larger than 450 mA, the conventional SMPS stops operating

in synchronous (see section 3.6). The resonant gate driver stops working since the maximum

duty cycle is reached.

4.3.4.2 Output voltage range and regulation bandwidth

The rise/time resulting from an 8-nH resonant inductance is about 580 ps and yields a

minimum duty ratio of 23% which is quite above that obtained with the conventional driver

and the requirement of a WCDMA envelope as discussed in chapter 3. But it is low enough

to perform a variable envelope tracking with the buck converter.

A sine-wave reference is applied to the converter to check both the dynamic range of the

output voltage i.e. the duty cycle, without any pulse-skipping in the power stage, and the

regulation bandwidth (Fig. 4.15). Indeed the converter does not operate properly below a

duty cycle of 23% because the high-side switch is not completely turned on by its resonant

driver. A maximum duty cycle of about 90% is achieved by the power stage though the

low-side switch is no longer turned on when large duty cycles are applied.



0 100 200 300 400 50010

20

30

40

50

60

70

80

90

Output current (mA)

η (%

) Resonant

Conventional

Fig. 4.14. Simulated eciencies comparison

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

Vol

tage

(V

)

VPA

VREF

7.1U 7.2U 7.3U 7.4U 7.5U 7.6U 7.7U 7.8U 7.9UTime (s)

Fig. 4.15. A 4-MHz sine-wave reference tracking



Fig. 4.16. Microphotograph of the test-chip

4.4 Experimental results

The experimental setup of the buck converter using resonant gate drivers is identical to

that described in the previous chapter. Indeed both converters are layouted within the same

test-chip for eciency comparison (Fig. 4.16).

The decoupling issue aroused in the previous chapter happens also with this converter

because the decoupling tank is the same for both. Like with the buck converter using

conventional drivers, the small on-chip decoupling capacitance impacts the eciency and

the transient performance of the buck converter using resonant gate drivers.


The range of the output voltage is estimated with the buck converter working in open-

loop condition by applying a variable duty cycle clock signal. Thus we obtained an output

voltage varying between 0.4 and 2.5 V without pulse-skipping (for an output current varying

from 57 to 377 mA).


The buck converter using resonant gate drivers exhibits a similar transient behavior as

its counterpart using conventional drivers. The supply voltage's overshoot and undershoot

observed on the LX node voltage show the same sensitivity to assembly parasitics (Fig.

4.17). Although the voltage undershoot due to the Ldidt

is smaller with the resonant gate

driver because of large turn on time of the high-side power transistor.

The dead-time controller yielded a small dead-time for both transitions of the LX node

voltage, hence low body-diode's conduction losses. Each dead-time is reduced to about 300

ps, which represents a total body-diode's conduction time of about 12% of the switching

period (Fig. 4.18). At light load condition the total dead-time is still less than 20% of the

switching period (Fig. 4.19). Although this is not negligible, the resulting power dissipation

is not signicant because of the small output current.



Fig. 4.17. Overshoot on the output voltage of the power stage

(a) td2=275 ps

(b) td1=350 ps

Fig. 4.18. Dead-time obtained at both transitions of LX voltage



(a) td2=400 ps (b) td1=475 ps

Fig. 4.19. Dead-time in low output current condition

4.4.3 Eciency

The main goal of the test-chip is to compare the eciency improvement obtained with

resonant gate drivers at low output power. Thus the switching power losses of both buck

converters are compared in order to determine the improvement due to the resonant gate

driver.

In simulation the resonant gate drivers lead to a gate drive losses reduction of nearly

35% . During the measurement a reduction of 30% is obtained at light load condition and

an average 20% reduction from light to medium load condition (Fig. 4.20). In terms of

eciency, this reduction of switching losses corresponds to an eciency enhancement of as

much as 5% from low to medium output power (Fig. 4.21). The dierence between the

simulation and the measure is probably due to some parasitics that have been taken into

account such as the routing resistance of the resonant inductors, which adds to their series

resistance. Other parasitic eects such as the skin eect or the eddy currents are probably of

less importance because the resonance frequency of the inductors is about some GHz, quite

beyond the 200 MHz switching frequency and its signicant harmonics.

Because of the duty cycle limitation, it was not possible to carry out measurements at

very low output power, i.e. around tens of mW, where the eciency improvement would be

the highest because of the decrease of the switching losses that dominate in this power range.

Nonetheless the reduction of switching losses obtained here is interesting and illustrates the

advantage of the resonant gate driver over the conventional driver. The eciencies plotted

on Fig. 4.21 are almost equal at large output power where the ohmic losses dominate and

are equal for both converters.



Gate drive losses comparison

40

50

60

70

80

90

100

110

0 100 200 300 400Pout (mW)

Switc

hing

loss

es (m

W)

resonantstandard

Fig. 4.20. Switching losses comparison at low to medium output power for Vbat=3.6 V

Efficiency comparison @ Vbat=3.6V

50

55

60

65

70

75

80

85

100 300 500 700 900 1100Pout (mW)

Eff

icie

ncy

(%)

resonantstandard

Fig. 4.21. Eciency comparison



Technology 0.25-µm BiCMOS

Switching frequency (MHz) 200

Vin range (V) 3∼4.3

Vout range (V) 0.33∼2.95

Max. output current (mA) 442

Filter inductance (nH) 51

Filter capacitance (nF) 4.7

Eciency max. (%) @ Vin=3.6V 77.93

Chip area including pads 1.6x1.6 mm2

Resonant inductors area 2x0.44x0.44 mm2

Tab. 4.3. Performance summary of the buck converter using resonant gate drivers


The analysis and design of a resonant gate driver for HF DC/DC converters have been

presented in this chapter. The practical use of the methodology is given through the design

of a demonstrator.

The reduction of switching losses achieved in the demonstrator is smaller compared to

early works on energy recycling, but a fundamental dierence is the very high switching

frequency that allowed the integration of the entire resonant gate driver on-chip. Whereas

the other works, working around 1 MHz of switching frequency, are designed with an external

inductor.

The area overhead can be acceptable if the target load is very larger than the buck

converter. A performance summary is presented in Tab. 4.3, including the main features of

the DC/DC converter.


Chapter 5

Integrated passive devices for power

management systems

Overview

5.1 State-of-the-art of integrated inductors . . . . . . . . . . . . . . 100

5.2 State-of-the-art of integrated capacitors . . . . . . . . . . . . . . 105

5.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

The important place occupied by passive devices in power management circuits, especially

in SMPSs, motivates this chapter, though the design of passive components is not part of

this thesis. Recent developements in the integration of high-quality passive devices have

accompanied the research on HF DC/DC converters. This chapter intends to introduce

some of these developments and explore how their contribute to ecient power management

systems. The rst section introduces the role of passive devices in power management. The

state-of-the-art of integrated inductors and capacitors is presented in sections 5.1 and 5.2

respectively. A conclusion is given in section 5.3.

The passive devices referred to are the inductors and the capacitors that are used for l-

tering and decoupling in DC/DC converters. The key factors of SMPSs such as the eciency,

the regulation bandwidth and the HF noise ltering are related to the output lter and the

decoupling capacitors. It is therefore important to have high-quality passive components in

the converter. This requirement of high-quality passive devices in power conversion mod-

ules have not been so far fullled by the standard CMOS technologies. Indeed the density

proposed in these technologies is too low to allow the integration on -chip of capacitors and

inductors with values in the range of tens of nF and tens of nH respectively. Even though

capacitance density of few fF/µm2 is proposed in deep-submicron CMOS technologies, the

capacitors hence designed cannot operate with a voltage as high as the battery voltage (3.6

V). So far in power management circuits, high voltage decoupling is ensured by MIM capac-

itors, which have a limited density to consider reasonably the integration of more than 1 nF.


Chapter 5 : Integrated passive devices for power management systems

(a) Capacitor (b) Inductor

Fig. 5.1. Surface-mounted devices (SMD) used in power management

Yet as shown by the discussion about on-chip decoupling in chapter 3, it is very important

to have a large on-chip decoupling capacitor.

The density issue exists also for power inductors. The specications usually relate to the

series resistance, which must be low to minimize the ohmic power losses. Most of the CMOS

technology nodes includes silicon integrated inductors for RF applications. But like those

presented in chapter 4 for the resonant gate driver, they are designed as air-core devices and

thus do not achieve enough density to allow the integration of higher values of inductance.

Typical values used for RF baluns and choke inductors are limited to few nanohenries and

the area occupied is usually large, compared to active circuits. Thus it is not realistic to

consider the integration of air-core inductance in the range of tens of nanohenries as used in

HF DC/DC converters. Moreover EMI issues arise with current in the 1-A range.

The parasitic eects and the density issue are the main reason for the use of discrete

o-chip capacitors (Fig. 5.1a) and inductors (Fig. 5.1b) in power management systems.

5.1 State-of-the-art of integrated inductors

5.1.1 Requirements on the output inductor in a HF DC/DC con-

verter

The high series resistance is a major concern with silicon integrated inductors because of

the limited thickness (few µm) of the copper tracks used to design the windings. A signicant

eciency drop is due to this series resistance for high output current (eq. 1.7). Some recent

works [25, 21, 32] report fully integrated DC/DC converters with air-core inductors but they

consider only low supply voltage (1.2 to 1.8 V) instead of battery voltage (up to 4.8 V) and

have output power limited to hundreds of mW. Otherwise the large DC series resistance

reported (485 mΩ for 2 nH inductance in [21]) would cause high AC and DC ohmic power

losses.

Although the series resistance of an inductor (Fig. 5.2) consists of a DC component

and an AC component (eq. 5.1), the rst one causes usually more power losses than the



Fig. 5.2. A simple model of inductor

020406080

100120

Pow

er lo

ss(m

W)

1 2 3 4 5 6

Drivers

Rdson

Dead-time

Rdc

Rac

CLX

Fig. 5.3. Breakdown of the power losses for a 200 MHz SMPS

second one in a DC/DC converter. For instance in a buck converter (with the following

parameters: NLDEMOS power stage, Fs=200 MHz, Rdson=414 mΩ, Vbat=3.6 V, L=50 nH,

C=5 nF, a dead-time of 400 ps, Iout=445 mA, ∆I=69 mA), an inductor with Rdc=300 mΩ

and Rac=10 Ω at 200 MHz, leads to the breakdown of the power losses in Fig. 5.3.

RL = Rdc +Rac(f) (5.1)

The power dissipation due to Rac (4 mW) is tiny compared to those due to Rdc (80 mW)

and the other contributors because of a relatively low RMS ripple current. The power losses

due to Rdc and Rac are respectively given by eqs. 5.2 and 5.3.

PRdc = Rdc ·(I2out +

∆I2

12

)(5.2)

PRac = Rac ·∆I2

12(5.3)

Therefore the AC resistance is not really a concern in a SMPS with a low ripple current

but the DC component can cause a power dissipation as high as that of the channel resistance

of the power transistors. It is then necessary, in the design trade-o of an integrated inductor,

to give the priority to the DC resistance.

An increase of the width of the windings even though it decreases the DC series resistance,

also decreases the total inductance and again requires a larger area to achieve the initial

inductance. Besides the parasitic coupling capacitor Cc becomes large and thus the resonance



Fig. 5.4. SiP approach to assembly active and passive chips

frequency of the inductor is reduced, which is not compatible with a HF DC/DC converter,

especially in a RF application. Indeed a low resonance frequency decreases the eectiveness

of the HF switching noise ltering and may prevents the polar transmitter to fail to meet with

the specications on spurious frequencies. An inductance (almost) constant up to several

times (5×) the switching frequency is necessary to ensure a good noise ltering and a stable

operation in closed-loop.

The use of a magnetic core brings a satisfactory solution to both area and series resistance

issues, which are correlated. Indeed the high density obtained with a magnetic core, decreases

the required number of turns and therefore the total resistance of the routing metal. The

next paragraph introduces some integrated inductors with a magnetic core.

5.1.2 Integrated inductors with a magnetic core

The magnetic core enhances the total inductance of a winding by collecting the magnetic

eld lines through a low reluctance path formed by the magnetic circuit. In principle the

inductance enhancement is proportional to the permeability of the core. Other parameters

like the geometry of the core have an impact on the inductance.

So far the fabrication on silicon of fair quality magnetic material has prevented the inte-

gration of inductors with large values. The dierent process steps required for the fabrication

of magnetic materials are hardly compatible with standard CMOS technologies. In [45] is

detailed the fabrication of an integrated inductor with a NiFe core. The impact on the

inductance of the geometry of the magnetic core and the windings is investigated. But the

process requires an annealing temperature that cannot be supported by CMOS technolo-

gies. Therefore alternative approaches have been based on building the inductor with the

magnetic core on a separate silicon substrate, which is connected to the power management

active circuits, either through bond wires (Fig. 5.4) or by ip-chip technique (Fig. 1.14).

This System-In-Package (SiP) approach is the main lead followed in the research community

for the integration of magnetic-core inductors with DC/DC converters.

5.1.2.1 Fabrication of magnetic cores

Many magnetic cores reported in the literature are fabricated with an alloy of NiFe,

which is deposited over a silicon wafer. Compared to the ferrite used in discrete inductors, the

ferromagnetic alloy has a larger saturation magnetic induction (>1.4 T) and a high relative



Fig. 5.5. Micro-inductor with a magnetic core from Tyndall Lab.

Fig. 5.6. Sandwiched magnetic core inductor (Credit: B. Orlando [1])

permeability (up to few thousands), which makes it well suited for power applications at

medium switching frequency where power density is an important factor.

The magnetic material can be deposited by electroplating like in [46] where a thin lm

(4.2 µm) of Ni45Fe55 alloy is electroplated on the substrate and insulated from the copper

windings that are also electroplated and sandwiched by the magnetic material (Fig. 5.5). The

insulation of the magnetic material from the copper windings is important for the dynamic

performance of the inductor because the conductivity of magnetic alloy is not always negli-

gible. The proposed inductor has an inductance of 150 nH and an area of 4.13mm*1.8mm.

A DC series resistance of 250 mΩ is reported with 50 µm of copper thickness.

Instead of encapsulating the copper spirals by the magnetic alloy, the magnetic circuit is

surrounded by the copper spirals in [1] (Fig. 5.6). In this way the deposition of the Ni80Fe20

alloy is realized by Physical Vapor Deposition (PVD) in one step unlike the previous cited

work in which the magnetic core is fabricated in two steps. The magnetic core is laminated

and consists of sixteen 1-µm thick layers that are separated by a thin layer (70 nm) of SiO2

used as insulator. The laminated structure reduces the energy loss due to eddy currents

and allows the use of a thick magnetic core at high frequency. The main advantage of this

inductor compared to other reported works, is the closed shape of the magnetic circuit which

enhances the inductance density. Hence an inductance of 500 nH is reported for an area of

5.6mm*5.6mm and a DC series resistance of 110 mΩ.

The operating frequency of these NiFe alloys is relatively low compared to the switching

frequency range addressed in this thesis. Other integrated power inductors with a dierent

magnetic material (CoHfTaPd in [47] and FeBN in [48]) have been reported and demon-

strated in a DC/DC converter but only at a switching frequency below 4 MHz. A microwave

magnetic material (YIG) that can operate above 100 MHz is proposed in [2]. This magnetic



(a) (b) (c)

(d) (e) (f)

Fig. 5.7. Process steps for the fabrication of the inductor with a YIG core (Credit:Martin[2])

material seems to be suitable for HF DC/DC converters. Indeed the relative permeability

though small (between 25 and 45) is constant up to 400 MHz and makes the material more

resistive and therefore less sensitive to eddy currents. The fabrication steps of the inductor is

shown in Fig. 5.7 for a single magnetic material layer. A 100-nm seeds layer is rst deposited

on the magnetic material (b). Then the windings pattern is developed on a dry photoresist

lm (c) before the copper electroplated (d). The seeds layer and the dry photoresist lm

are removed respectively in steps (e) and (f), leaving the copper windings pattern on the

magnetic material. Simulation results give a 25 nH inductance with a 50 mΩ series resis-

tance for a 3 mm2 area. The inductance density can further be increased by as much as the

permeability value when using a double-layer of YIG.

5.1.2.2 Parasitic eects in integrated inductors with a magnetic core

The state-of-the-art integrated inductors feature a thicker copper spirals than CMOS

air-core inductors. In most cited works the copper is deposited on the magnetic core by

electroplating and can be as thick as tens of µm. Thus the series resistance in these devices

is lower than what is usually achieve in CMOS air-core inductors. However the DC resistance

is still higher than that of commercial discrete inductors; an increase of the copper thickness

is a good solution because the winding width is usually limited by the area of the device.

But it seems to be dicult to achieve a copper thickness close to 100 µm. The coupling

capacitor between the windings, that limits the operating frequency range, increases with

the copper thickness. Therefore it is important to take advantage of the high inductance

density brought by the the magnetic material to decrease the required number of turns and

thus the series resistance and the coupling capacitor.

The power losses in the magnetic core due to eddy currents are one of the major drawbacks

in integrated inductors. A wide operating frequency range is usually observed with magnetic

materials that have a signicant conductivity and therefore cause more power losses due to

eddy currents. In [46] eddy currents cause as much as 43% of the total power losses of the


5.2 State-of-the-art of integrated capacitors

inductor. The lamination of the magnetic core is the solution to decrease the impact of eddy

currents but it must not impact too much the performance of the magnetic core.

5.1.3 Comparison of dierent techniques

The integrated inductors presented in the previous paragraphs have a planar structure

that is area consuming. Indeed though the magnetic alloys have a high relative permeability

the area of these inductors is larger than those of discrete devices for the same inductance.

The magnetic alloys deposition techniques have not reached a reliable level for very small

areas (<1 mm2) for SiP packaging with a DC/DC converter switching beyond the 100 MHz

range.

Many gures of merit exist in literature to compare inductor, but we use here the in-

ductance to DC resistance and to area ratio to characterize respectively the power losses

and the inductance density. The quality factor that is usually computed to estimate the

performance of RF inductors, is not suited for DC/DC conversion because a power inductor

transfers almost only DC power. The comparison of some reported integrated inductors is

presented in Tab. 5.1. A discrete Surface-Mounted inductor from Coilcraft is added to the

table for comparison with a commercial discrete inductor.

Considering the gures of merit, integrated inductors have a long way before competing

with discrete inductors in terms of power dissipation and occupied area. The frequency

behavior of the inductors in Tab. 5.1 is quite at up to tens of MHz. The operation above

100 MHz range requires specic magnetic materials to guarantee a constant inductance.

Unfortunately available materials present limited permeability and small saturation magnetic

induction. Among the integrated inductors, that reported in [1] presents the highest gure of

merit and an important inductance to DC resistance ratio, though it has a copper thickness

of only 15 µm whereas in [46] the thickness is 50 µm. In [48] though a high permeability

alloy is used (µr=4600), the series resistance is still too high, probably because of the small

copper thickness (10 µm).

These integrated inductors are interesting attempts to address the needs in DC/DC con-

version. In order to cope with the requirements of state-of-the-art HF DC/DC converters,

lower inductance values should also be addressed. But this constitutes a challenge in mag-

netic layer deposition and also in assembly engineering because of the expected small surface

of inductance values in the tens of nanohenries range.


The Metal-Insulator-Metal (MIM) and the MOS capacitors are the main types of ca-

pacitors integrated in standard CMOS technologies. But their density is usually too small

to allow the integration of capacitance values beyond 1 nF in high-voltage applications. In

order to enhance the capacitance of any type of capacitor, one or more terms of eq. 5.4, i.e.



Coilcraft (SMD) [46] [1] [48] [47]0603LS-102X

L (nH) 1000 150 500 1000 960RDC (Ω) 0.81 0.25 0.11 1 0.9

L/ (RDC ∗ Area) (nH/Ω/mm2) 586 80 144 40 66

Tab. 5.1. Comparison of integrated power inductors with a discrete inductor

either the distance between the plates d, the relative permittivity of the dielectric εr or the

surface of the plates S, needs to be tuned.

C =εrε0S

d(5.4)

The thickness of the dielectric is limited by the maximum voltage (or electric eld) that

can be applied, therefore many researches focus on high-permittivity or high-k dielectrics.

Unfortunately such materials do not always interface correctly with silicon like the SiO2. The

approach adopted in trench capacitors is to increase the eective surface of the electrodes

using the third-dimension of the silicon wafer. An array of pores is created in the wafer

and lled with dielectric. Contacts are connected to both sides of the dielectric to form the

electrodes. Thanks to this technique capacitive densities as high as 80 nF/mm2 have been

reported in the state-of-the-art.

5.2.1 Trench capacitors

A simple description of the fabrication of trench capacitors is shown in Fig. 5.8. First

an array of pores is etched in the silicon wafer by DRIE (Deep Reactive Ion Etching) (a).

The dielectric layer is formed on the etched silicon area by oxidation or by LPCVD (Low-

Pressure Chemical Vapor Deposition) if a non-oxide dielectric is used (b). The trenches are

lled with a doped polysilicon to form the top electrode (c). The bottom electrode is created

by connecting the substrate with a low ohmic contact (d).

High aspect ratio pores are necessary in order to optimize the surface of the capacitor.

With the PICS technology from NXP an aspect ratio of 50 is reported in [49]. Pores with 30

µm of height and only 1.5 µm of width are also reported in [3] using the same technology;

this high aspect ratio is combined with a thin (16 nm) dielectric formed by a stack of Ox-

ide/Nitride/Oxide with a breakdown voltage of 15.5 V, which qualies the PICS technology

for battery voltage operation. A capacitive density of 80 nF/mm2 is reported in [3]. Other

devices such as a planar air-core inductor or a planar MIM capacitor are also available in

the technology (Fig. 5.9).

An improvement of the PICS technology is proposed by [4] and consists of a stack of

3 MIM trench capacitors with a high-k dielectric, the Al2O3 (Fig. 5.10). The electrodes

are fabricated with layers of TiN that alternate with dielectric layers. The substrate is



(a) (b)

(c) (d)

Fig. 5.8. A generic design-ow for trench capacitors

Fig. 5.9. Trench capacitor in PICS technology (Credit: NXP[3])

connected on the backside with the bottom electrode. A capacitive density of 440 nF/mm2

is achieved when the three top electrodes are connected together.

5.2.2 Electrical performance

The trench capacitors include some parasitic resistance and inductance that impact the

dynamic performance. Indeed the connection between the bottom electrode and the sub-

strate can be long and very resistive. There are many solutions to decrease the series re-

sistance of the electrode. The rst being to remove the extra silicon on the backside of the

substrate to obtain a thin substrate. In [50] a phosphorous diusion is proposed to decrease

the series resistance, but the reduction of the resistance is still small. A capacitance of 7.45

nF is achieved with a low series inductance of 100 pH but the series resistance is about 400

mΩ, which represents a cut-o frequency of only 53 MHz. The values in [4] are smaller with

a series inductance less than 40 pH and a series resistance about 150 mΩ are obtained thanks



Fig. 5.10. PICS capacitor with 3 MIM layers: dielectric and electrode stack (a), themultilayer capacitor (b) (Credit: Klootwijk[4])

to the good conductivity of TiN electrodes.

When compared to the best discrete capacitors, for instance the low-prole capacitors

from Murata (a series inductance of 120 pH and a series resistance of 50 mΩ), the parasitic

performance of the reported trench capacitors does not qualify them for high frequency

decoupling as required in power management (above 100 MHz). While the series inductance

is low enough, a further reduction of the series resistance is necessary for an operation in a

DC/DC converter switching at hundreds of MHz. For instance a highly doped substrate can

be used along with a low-resistive layer for the electrodes.

5.3 Conclusion

The integration of high-quality passive devices is necessary for the design of compact

power management circuits. The techniques presented in this chapter are interesting leads

to achieve the monolithic integration of DC/DC converter. Their improvement requires the

development and the deposition of new high performance magnetic materials for inductors

and dielectric for capacitors. Besides a compatibility of the fabrication processes with stan-

dard CMOS technologies is necessary for the System-on-Chip (SoC) approach. At short

term, a SiP approach is possible as demonstrated in [3].

3D capacitor technologies have already made a great step toward a high density but there

is still the parasitics issue that impedes a high frequency operation (beyond 100 MHz).

For integrated inductors with a magnetic core, the use of a double layer allows few

windings and therefore leads to lower series resistance and smaller coupling capacitor. But

it requires a magnetic material with stable frequency characteristics.


Chapter 6

Improvement of the eciency at low

output power

Overview

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

6.2 Design of the control of the SMPS . . . . . . . . . . . . . . . . . 110

6.3 Design of the power stage . . . . . . . . . . . . . . . . . . . . . . 111

6.4 Internal power management . . . . . . . . . . . . . . . . . . . . . 118

6.5 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

6.6 Assembling and layout . . . . . . . . . . . . . . . . . . . . . . . . 125

6.7 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . 126

6.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

In this chapter we present design techniques used to improve the eciency of the SMPS for

low output power. The SMPS presented here, in the 0.13-µm CMOS SOI process, is based on

the design methodology introduced in chapter 2. It is intended to achieve EER in WCDMA

standard like the converters of chapter 3 and 4, but with also enough bandwidth for envelope

tracking in WLAN standard. Like in chapter 3 the choice of the technology is determined by

the needs for the design of the RF PA. Along the building blocks of the previous converters,

this one includes also an internal power management system that generates the required

supply voltage levels such the 2.5 V supply for the analog blocks or the drivers of the power

transistors from the battery voltage.

The demonstrator detailed here includes a DC/DC converter switching at 200 MHz and

a WLAN RF power amplier.


Chapter 6 : Improvement of the eciency at low output power

6.1 Introduction

The design of this test-chip has greatly beneted from the previous converters in terms

of specications of building blocks and also in terms of set up for measurements. Despite the

dierence between the 0.25-µm BiCMOS and the 0.13-µm CMOS SOI processes, especially

the lack of bipolar devices, the building blocks have schematics similar to those presented in

chapter 3. Indeed it did not appear after measurements that all these blocks needed much

more attention, therefore the main focus in the design of this second demonstrator is to

improve the eciency of the SMPS in light load condition. In addition to the resonant gate

driver, a dynamic sizing of the power transistors is performed to improve the eciency at

low output power. For further decrease of the switching losses, the supply voltage of the

drivers is xed to 2 V instead of the nominal voltage of the standard MOSFET, i.e. 2.5 V.

A new implementation of the adaptive dead-time control is performed in a digital approach

that is more simple than the analog implementation presented in chapter 3.

The system is designed with GO2 version of the 0.13-µm CMOS SOI process which

includes standard CMOS transistors with a nominal voltage of 2.5 V and a high voltage

N-type drain extension transistor to handle as much as 8 V.

6.2 Design of the control of the SMPS

6.2.1 Controller

The topology of the controller is unchanged (Fig. 6.1a); so we focus on the stability issue

by investigating more on the robustness of the design. The stability analysis is performed

for both loops around the error amplier. Although the emphasis is usually put on the main

loop, it is necessary to ensure that the secondary loop has a sucient phase margin. In this

task, the lstb function of the IC simulator Eldo proves to be very useful. With the error

amplier depicted on Fig. 6.1b, we found a phase margin of 510 (a delay margin of 6.3 ns,

larger than the switching period) and 550 (a delay margin of 617 ps), respectively for the

main loop and the secondary loop (Fig. 3.5b and c). Though the second delay margin is

small, it is unlikely that such delay exists since no device is placed between the output of

the error amplier and the resistor Rdrv (Fig. 6.1a).

The folded-cascode topology is also adopted here for the op-amp design, with a PMOS

input pair, instead of the bipolar pair used in the rst test-chip. Thus in order to achieve the

same GBW, the bias current has to be increased and the DC power consumption rises to 1.4

mW, whereas with bipolar devices it was only 470 µW. Nonetheless this power consumption

is still tiny compared to the power losses of the power stage.


6.3 Design of the power stage

(a) Controller schematic (b) Error amplier

Fig. 6.1. Controller circuit

Fig. 6.2. PWM comparator

6.2.2 PWM

The technology change did not aect much the structure of the PWM circuit. In partic-

ular the ramp generator is designed in the same way as in chapter 3, with CMOS devices

replacing their bipolar counterparts.

The basic comparator of chapter 3 is now replaced by a folded-cascode amplier followed

by a common source amplier, which achieves a large bandwidth and a large gain at the

cost of nearly 350 µW of DC consumption (Fig. 6.2) compared to 720 µW in the previous

bipolar design.


The eciency analysis performed in chapters 3 and 4 shows a relatively high eciency

at large output power. Thus the improvement of the eciency at low output power is the

main focus of the design of the power stage. An approach based on the combination of

three techniques is used in this work: the resonant gate driver, the dynamic sizing of power

transistors and the low voltage swing operation of the drivers. In this section we analysis



the possibilities oered by the last two techniques and how they can be combined with the

resonant gate driver.

6.3.1 Low voltage swing operation of the drivers

The low supply voltage operation is a technique widely used to decrease the power dis-

sipation of digital SoCs when the activity of the system is low. Hence the digital core is

supplied below its nominal voltage with a voltage level that must still be above a minimum

value depending on the technology and the processed task. It has been proposed for DC/DC

converters by [51] with the purpose of reducing the switching losses by decreasing the voltage

swing at the gate of the power devices. Thus a straightforward computation from the well

known formula fCV 2, shows that a 10% decrease of the drivers' supply voltage results in

a 20% decrease of the switching losses. Unfortunately a decrease of the gate voltage of the

power transistor leads to an increase of the channel resistance, so the technique is limited

by the rise of the conduction losses.

The optimal supply voltage corresponds to the minimum of the power dissipation of the

power transistor. Instead of using a complex analysis to determine this optimal voltage,

we used the model provided by the Design Kit. The simulation shows that the channel

resistance of a CMOS transistor in the linear region does not vary signicantly when the

gate to source voltage exceeds 2∼3 times the threshold voltage. As shown in Fig. 6.3 the

channel resistance varies by only 10% when the gate to source voltage goes between 2 and

2.5 V. For a SMPS, an operation with a driver supply voltage of 2 V instead of 2.5 V leads

to an increase by 10% of the ohmic losses and a decrease by 40% of the gate drive losses.

The total energy saving depends on the ratio between the two types of power losses, but as

the switching losses dominates in a large part of the output power range, the increase of the

ohmic losses is compensated by a larger decrease of the switching losses. Thus the supply

voltage of the drivers is xed to 2 V by internal LDOs that are described in section 6.4.

A dynamic adjustment of the supply voltage of the drivers according to the output current

can be adopted to optimize the energy saving. But the resulting complexity of the design

does not worth the extra energy saving it provides.

6.3.2 Dynamic sizing of the power transistors

The dynamic sizing of power devices is sometimes used to improve the eciency of

power management systems and PAs. In systems that deal with a wide range of power, the

adjustment of the power devices size allows to track the optimal operating point and hence

to maximize the eciency over the output power range.

The implementation requires the splitting of a power transistor into multiple smaller

devices that can be connected together to form a unique power transistor (Fig. 6.4). Thus

as the output current varies, so does the width of the power transistor in order to satisfy

eq. 2.21. Clearly the discretization of the power device's width must be as ne as possible.



Fig. 6.3. Channel resistance of a NLDEMOS as a function of gate-source voltage with W=7mm

Fig. 6.4. Multiple transistors forming a single power device

Indeed a maximum eciency tracking can be possible only when the actual size of the power

device is close to the optimum for a given load current.

The main advantage of the dynamic width sizing is to reduce the switching losses at low

output power by the reduction of the amount of gate capacitance of the power devices. When

the output current is low, the decrease of the width of the power transistor causes an equal

decrease of the switching losses. Compared to a conventional power stage, the eciency is

enhanced at low output power and remains identical at large output power when all the

unit devices are activated. Fig. 6.5 plots the simulated eciencies of a conventional buck

converter switching at 200 MHz and its counterpart with an equal width for the power

transistors but divided into 4 unit transistors. In regions 1, 2, 3 and 4 the power transistors

of this converter are respectively made of 1, 2, 3 and 4 unit transistors. Hence the switching

losses are divided by a factor 1/4, 1/2 and 3/4 in respectively regions 1, 2 and 3, whereas

they are equal for region 4. In light load condition (region 1) this results in a global eciency

improvement of as much as 12% for the converter. The eciency is still enhanced in medium

load regions up to the large output power (region 4) where both converters exhibits similar

eciencies. This example illustrates the advantage of the dynamic sizing of the power

transistors. It shows in particular how high the eciency improvement can be by using

more unit devices. But there are two fundamental limitations: the design complexity and

layout placement issue introduced when using more unit devices, and the presence of the

drain-bulk capacitance of inactive transistors that adds to the total capacitance at node

LX. Although the gate capacitance of a unit transistor is not switched when the transistor

is turned o, the drain-bulk capacitance remains connected to node LX and thus causes

additional switching losses.



Fig. 6.5. Simulated eciency of a conventional SMPS and a dynamic width sizing SMPS(Vbat=3.6 V and Rload=6 Ω)

When combined with resonant gate drivers, the dynamic width sizing introduces also a

penalty a silicon area that is discussed in the next paragraph.

6.3.2.1 Combination with the resonant gate driver

When power transistors are divided into multiple devices, it takes an equal number of

inductors to realize a resonant gate drive. Since the gate capacitance of the unit transistors is

small, a large resonant inductor is needed to achieve a substantial energy recovery as shown

by the analysis detailed in section 4.2. In terms of silicon area, it becomes clear that a small

number of unit width must be selected though a larger number is preferable in eciency

point of view. For this reason we used only two unit devices for each power transistor.

Therefore four inductors are necessary for the resonant gate drivers of the power stage.

With two unit transistors forming each power device, the power range consists of two

domains and the switching losses can be divided by two in the low output power range in

addition to the losses reduction oered by the resonant gate driver. The transition point

between the two power domains corresponds to half the maximum output current. When

the buck converter is working with a variable reference, it is necessary to adjust the size of

the power transistors as the load current varies between its low and large values. This task

is performed by a dynamic width sizing controller.

6.3.2.2 Design of the dynamic sizing controller

The dynamic width sizing controller is designed to adjust the width of the power transis-

tors according to the output current. Since there are only two possible sizes, its output is a

1-bit signal. Like in the design of the dead-time controller in chapter 3, the sense of the out-

put current is performed thanks to the output voltage of the SMPS because the PA behaves

as a resistor. Therefore the dynamic width sizing controller is essentially a comparator with



Fig. 6.6. Schematic of the dynamic width sizing controller

a reference voltage equal to half the maximum output voltage of the SMPS, i.e. 1.5 V (Fig.

6.6). A hysteresis is created in order to prevent false alarms since the output voltage of the

SMPS exhibits some voltage ripple. In Fig. 6.6, a voltage shift is introduced thanks to the

source follower formed by the transistor Ms to ensure that the lower limit of the hysteresis

windows is not located at 0 V. Otherwise once at the high state, the comparator will never

go to the low state because the output voltage of the SMPS does never reach 0 V (Fig. 6.7).

In EER the output voltage varies between its lower and upper limits at a frequency that

may be as high as 3.84 MHz for the WCDMA standard. From an eciency point of view, it

is interesting to track the variation of the output voltage and adjust the width of the power

transistors accordingly. But this introduces also a bandwidth constraint on the LDO that

supplies the drivers. An alternative solution is to adjust the width of the power transistors

according to the average output voltage instead of the instantaneous voltage. Since the

average output power of a handset varies at a low rate, so does the width of the power

transistors.

For this demonstrator both fast and slow variations of the width have been implemented

thanks to two RC tanks. The MUX allows to switch between the fast and slow paths of

respectively 20 MHz and 400 kHz of bandwidth. The voltage dividers scale the output

voltage, that may be as high as 3 V, to the voltage range allowed for the devices of the

comparator.

6.3.3 Drivers and power transistors

The specications of the power transistors remain the same as in chapter 3. Since the

NLDEMOS transistor in the 0.13-µm CMOS SOI technology has almost the same character-

istics as that in the 0.25-µm BiCMOS, the optimal width remains about 7 mm. Each power

transistor is then realized by two NLDEMOS transistors of 3.5 mm of width.



Fig. 6.7. Hysteresis and voltage shift of the dynamic width sizing controller

1 2 3 4 5 6 7 8 9 10−5

0

5

10

15

20

25

30

35

LR

(nH)

η (%

)

(a) relative eciency

1 2 3 4 5 6 7 8 9 10100

150

200

250

300

350

400

450

500

LR

(nH)

t r,f (

ps)

(b) rise/fall time

Fig. 6.8. Relative eciency and rise/fall time of the resonant gate driver for a gate capaci-tance of 8.5 pF

The optimization of a resonant gate driver for each of the four NLDEMOS transistors

is performed using the method presented in chapter 4. A quick simulation gives the gate

capacitance of a NLDEMOS transistor of 3.5 mm of width, which is 8.5 pF. The relative

eciency of the resonant gate driver compared to the conventional driver is then plotted

in Fig. 6.8a as a function of the resonant inductance. Compared to the power transistors

of chapter 4, an inductance of about 8 nH is needed to achieve 30% of relative eciency

because the gate capacitance here is as twice as small. The resulting rise/fall time of the

gate to source voltage is 400 ps (Fig. 6.8b), which limits the minimum duty cycle to 16%

for 200 MHz of switching frequency.

6.3.4 Digital dead-time controller

Measurements in chapter 3 show how the adaptive dead-time control is eective to re-

duce the conduction losses of the body diode of the synchronous transistor. In this new

demonstrator a simplied implementation is provided. While it is based on digital circuits,



50 100 150 200 250 300 350 4000

100

200

300

400

500

600

Iout (mA)

τ LX

(ps

)

(a) Discharge time of CLX

50 100 150 200 250 300 350 4000

100

200

300

400

500

600

700

800

Iout (mA)

τ LX

(ps

)

(b) Quantization of the discharge time

Fig. 6.9. Discharge time of the capacitance at the LX node as a function of the outputcurrent

this new dead-time controller is as eective as that presented in chapter 3.

6.3.4.1 Discretization of the delay

The architecture presented in Fig. 3.19a is maintained but the delay td2 is varied dis-

cretely according to the output current to match approximately the discharge time of the

capacitance CLX . Hence a transient simulation of the power stage is performed to estimate

CLX and its discharge time, τLX , as a function of the output current (Fig. 6.9a). The

plot shows that the variation of τLX is not signicant once the output current exceeds 200

mA, while from 50 to 100 mA, the discharge time varies from 600 to 300 ps. Therefore the

discretization of the delay td2 must be ne in the low output current range and can be coarse

in the large output current range.

We used a 3-step discretization for the delay td2. Thus a delay of 780 ps is applied when

the output current is below 100 mA; between 100 and 200 mA, the delay selected is about

520 ps. When the current is beyond 200 mA, a constant delay of 260 ps is applied (Fig.

6.9b). The quantization error reaches its maximum value of 320 ps when the current is 200

mA leads to extra conduction losses in the body diode of 8.4 mW for a switching frequency

of 200 MHz. However this penalty is acceptable compared to the output power (240 mW)

but still costs roughly 1.5% eciency. Sparing this loss penalty must be balanced by the

complexity introduced to implement a larger number of discretization steps.

6.3.4.2 Circuit design

The block diagram of the new dead-time controller is presented in Fig. 6.10. One of

the three copies of the PWM signal delayed respectively by ∆T , 2∆T and 3∆T is selected

by a MUX in order to produce the required dead-time between the gate-source voltage of

the power transistors. The selection of the appropriate delayed PWM signal by the MUX is

performed thanks to the Dead-time Selector, which consists of two comparators (Fig. 6.11)



Fig. 6.10. Block diagram of the dead-time controller

similar to that presented in paragraph 6.3.2.2. Like with the dynamic width sizing controller,

the output voltage is sensed instead of a direct measure of the load current. The reference

voltages corresponding to the current references of 100 mA and 200 mA, are respectively

0.6 V and 1.2 V considering a 6 Ω equivalent load resistance. Both comparators have a

hysteresis behavior to prevent unnecessary changes of dead-time.

The bandwidth of the dead-time controller is limited by the voltage divider R1, R2 and

the capacitor C to approximately 20 MHz, which corresponds to the large signal bandwidth

of a WLAN envelope signal. So the ripple voltage at the output of the converter does not

inuence the dead-time selection.

The delay block consists of a chain of CMOS inverters with a constant bias (Fig. 6.12).

Simulations performed at dierent process corners show no signicant shift of the delay from

a nominal value of 260 ps.

As discussed in chapter 2, the dead-time td1 does not require a dynamic adjustment. It

is therefore realized with a constant delay block.

The simulation results of the dead-time controller are presented in section 6.5. The

advantages of the digital implementation are also discussed.

6.4 Internal power management

Internal LDOs are designed in order to supply the low-voltage circuits from the battery

voltage. Since only power stage devices are realized with NLDEMOS transistors, the other

blocks that are designed with standard transistors can be supplied with a maximum 2.7 V.

Therefore an internal voltage conversion is necessary to achieve a stand-alone SMPS with

a single voltage source. Usually a single LDO handles this on-chip voltage conversion but

that results in noise issues because of the dierence in the behavior of the circuits. Indeed

whereas the current consumption of the analog circuits consists of DC current, the drivers


6.4 Internal power management

5 kΩ55 kΩ

2.5 V

SEL0

Vout

25 kΩ

200 fF 50 kΩ

10kΩ

50 kΩ

2.5 V

SEL1

R1

R2C

Fig. 6.11. Dead-time selector

Fig. 6.12. Delay cell of the dead-time controller



VrefVbat

Analog Digital

VDD=2.5 VHF

noise

Fig. 6.13. Single LDO for on-chip power management

Vref1Vbat

Analog Digital

VDDA=2.5 VHF

noise

Vref2Vbat

VDDB=2 V

Fig. 6.14. Multiple LDOs for a separate supply of analog and digital circuits

draw a switched current from the supply source. In a single LDO scheme, this rejects a HF

noise on the supply voltage, which is not compatible with the controller and the other analog

circuits (Fig. 6.13). Instead separate LDOs are used to supply each block as shown in Fig.

6.14. This allows an optimization of each LDO without extra silicon area and avoids the

noise to be rejected on the analog circuits.

Hence we designed three dierent LDOs for our internal power management. For design

simplicity low power digital circuits of the dead-time controller are supplied by the same

LDO as the PID controller, the ramp generator and the dynamic width sizing controller.

Two separate LDOs supply the high-side and the low-side drivers because of a dierence in

their supply voltage.

6.4.1 LDO for low power circuits

The general structure of the LDOs is depicted in Fig. 6.15. Thanks to the diode stack,

a supply voltage of about 2.4 V is available for the bias of the op-amp. The diode D0 and


6.5 Simulation results

Vref

Vbat

VDDA=2.5 VBangapCircuit

D0

M1

M0

R0

Fig. 6.15. LDO used for the power supply of analog and low power digital circuits

the resistor R0 prevent a large voltage over the PMOS transistor M1. Since the current

consumption of the analog circuits is almost constant, the regulation bandwidth of the LDO

does not need to be large. The output capacitance of the LDO is 195 pF and is integrated

on-chip. In order to achieve a constant output voltage of 2.5 V, a reference voltage of 1.13

V is provided by a bandgap circuit.

6.4.2 LDOs for drivers

The schematic of Fig. 6.15 is modied to cope with the voltage requirements of the

drivers. While an output voltage of 2 V must be generated for the low-side driver, a voltage

of about 2.8 V is required for the boostrap supply of the high-side driver because of the large

voltage drop of the boostrap diode. Indeed the 0.13-µm CMOS SOI technology does not

provide a Schottky diode; hence a standard diode is used. Therefore each driver stage must

have its own LDO.

The op-amp of the LDO is designed to oer a low bandwidth performance. The current

sinked by a driver is taken through the LDO's output transistor for the DC part and from

the LDO's output capacitance for the HF parts. There is a balance between the DC bias

of the op-amp for a higher bandwidth and the silicon area for a larger output capacitance.

The schematics of the LDOs for the control and the synchronous drivers are depicted in Fig.

6.16. The operational ampliers are biased with the output voltage of the LDO designed

for low power circuits. The output stage of the LDO for the high-side driver is a common

source using a PMOS transistor so it can still work when the battery voltages goes down

to 2.9 V. A diode stack is connected between the drain and source terminals to protect the

PMOS from large voltages during the start-up of the LDO. The reference voltages of the

LDOs are generated on the test board for voltage tuning during measurements.


The block diagram of the SMPS is shown in Fig. 6.17 with all the circuits mentioned

earlier . The on-chip decoupling capacitance of the power stage is about 800 pF, realized



Vref

Vbat

VDD1=3 V

M2

M1

M0

R0VDDA=2.5 V

(a) LDO for the high-side driver (b) LDO for the supply of the low-sidedriver

Fig. 6.16. The two LDOs designed for the supply of the drivers

with MIM and MOM capacitors of respectively 700 pF and 100 pF. A resistance of 500

mΩ is inserted in series with the decoupling capacitance for the damping of the oscillation

resulting from the bond wires.

As with the other DC/DC converters designed during this thesis, the main functions are

checked through transient and frequency simulations before the chip is sent for fabrication.

6.5.1 Transient performance

6.5.1.1 Dynamic width sizing of the power transistors

The automatic adjustment of the width of the power transistors is checked in transient

simulations with a 1 MHz sine wave as the reference voltage of the SMPS. Fig. 6.18 shows

the output voltage of the SMPS and the width selection bit for both fast and slow paths.

The selection of the fast path, the width selection bit is changed at the frequency of the

output voltage. When the slow path is selected, the state of the width selection bit varies

only with the average output voltage. The right round marker in the gure indicates the

output voltage threshold when the fast path is selected. Once the power transistors are fully

activated, a lower threshold voltage (left round marker in the gure) is introduced by the

hysteresis. The impact of the width sizing on the eciency of the SMPS is discussed in

paragraph 6.5.2.

6.5.1.2 Adaptive dead-time control

The waveforms of the dead-time control signals are plotted in Fig. 6.19 for 1 MHz

reference voltage. When the output voltage increases, the dead-time between the gate to

source voltage of the power devices is decreased by step to minimize the conduction time of

the body diode. In Fig. 6.19a, the numbers correspond to the output current ranging up



VDDA=2.5 V

VDDB1=2.8 V

Levelshifter

Levelshifter

Dead-timeController

Controllerand

PWM200MHz

Off-chip

Vref

Vbat=3.6 V

Vout

VSSbat

Widthsizing

Controller

2

2

EN

EN

Vout

LDO

LDO

LDOVDDB2=2 V

Vbat=3.6 V

Vbat=3.6 V

Vbat=3.6 V

VDDA=2.5 V

Fig. 6.17. Block-diagram of the SMPS

Fig. 6.18. Width selection signal variation with the output voltage of the converter



(a) Dead-time selection signals and output voltage (b) Control signals in region 1

(c) in region 2 (d) in region 3

Fig. 6.19. Variation of the dead-time with the output voltage and the control signals of thepower transistors

to 100 mA (region 1), between 100 mA and 200 mA (region 2) and above 200 mA (region

3). Fig. 6.19b, c and d plot the control signals generated by the dead-time controller for

regions 1, 2 and 3 respectively. Hence for an output current of 400 mA, the total conduction

time of the body is about 400 ps, which leads to an acceptable power dissipation (22 mW)

compared to the output power of the SMPS. The dead-time td1 is constant and equal to the

implemented delay of 260 ps.

The simulations with respect to temperature and process variations of the delay block of

the adaptive dead-time controller show no signicant variation of the delay.

6.5.2 Eciency analysis

The simulation of the SMPS includes all signicant parasitic elements, especially the

routing and the bond wire resistance and inductance for a fair eciency computation. The

values taken into account are based on the study performed in chapter 3 since the test boards

are identical. The external decoupling capacitors are also the same as in chapter 3 but the

on-chip decoupling capacitance used in this demonstrator is about 800 pF, realized by a stack

of MIM (700 pF) and MOM (100 pF) capacitors. A higher on-chip decoupling capacitance

is required but the actual value is chosen to limit the area to 700µm*600µm. The damping

resistance is 500 mΩ and causes a maximum power dissipation of only 15 mW when duty



30

35

40

45

50

55

60

65

100 150 200 250Output current (mA)

Effic

ienc

y (%

)

Fig. 6.20. Simulated eciency of the converter without the dynamic width sizing and withthe dynamic width sizing

1020304050607080

100 150 200 250 300 350 400 450

Output current (mA)

Effic

ienc

y (%

)

LDO

SMPS

(a) Eciency vs. output current

30

40

50

60

70

80

0 300 600 900 1200 1500 1800

Output power (mW)

Effic

ienc

y (%

)

(b) Eciency vs. output power

Fig. 6.21. Simulated eciency of the SMPS and an LDO for Vbat=3.6 V and RPA=6 Ω

cycle is 50%, which is still low enough.

The eciency plot at low output power range in Fig. 6.20 shows an improvement as

much as 10% obtained by the dynamic width sizing of the power transistors. As expected

from the theoretical analysis, the eciency improvement decreases when the output current

increases and the ohmic losses becomes signicant because of the reduced width of the power

devices. An eciency plot over the full output current range of SMPS is shown in Fig. 6.21a

with the theoretical eciency of an LDO. The eciency of the SMPS is largely above that

of a LDO over the full current range. The peak eciency is 76%, which is lower than those

usually reported in the literature but is high enough for a DC/DC converter connected to the

battery and switching at 200 MHz. The eciency as a function of output power is plotted

in 6.21b.


The layout of this SMPS is similar to that described in chapter 3. The placement gives

the priority to the power transistors and the resonant inductors whose connections are made

as short as possible. Some connections are still long because of the large number of resonant



inductors (4 actually) and their size. But the resistance of the routing metal lines of the

power paths is minimized by stacking the two upper thick metal layers that are available in

the technology (1.7 µm thickness).

The test-chip called SATURN consists of the SMPS and a WLAN RF PA. The layout

and the oor plan are shown in Fig. 6.22. The two circuits are connected only on the PCB

where the output lter of the SMPS is implemented. The description of the PA is not given

here because it is out of the scope of this thesis.


The experimental results of the SMPS are presented in this section. The RF PA is not

connected yet to the DC/DC converter and is replaced by a 5.6 Ω resistance on the test

board (Fig. 6.23). All measurements are carried out with a switching frequency of 200 MHz.


The steady-state characteristics such as the DC consumption (3.2 mA at Vbat=3.6 V)of

the analog and low power blocs and the internal supply voltage of the power stage are in

agreement with the simulation. In particular the internal decoupling is eective as the supply

voltage of the power stage does not exhibit any over/undershoot when the SMPS is operating

(Fig. 6.24).

In closed-loop condition, the SMPS does not suer from instability with the full output

voltage range, though the pulse-skipping happens at the lower and upper limits of the output

voltage range. The experimental gain between the reference voltage and the output voltage

is β=2, like in the simulation.

Among the LDOs designed to supply the internal blocs from the battery voltage, only

the output voltage of the one used for analog and low power circuits (Fig. 6.15) is measured

on the PCB. The value measured is 2.5 V as specied during the design.


The features added to this test-chip, namely the dynamic sizing of the power transistors

and digital adaptive dead-time control, have been tested in variable output voltage condition.

The signal EN that controls the size of the power transistors is plotted in Fig. 6.25

with the output voltage varying at 100 kHz. The actual threshold voltage is 1 V instead of

1.5 V because of the miscalculation of the voltage divider. Nevertheless the dynamic sizing

control adjusts very well the size of the power transistors according to the output voltage;

the hysteresis threshold is also correct.

The duration of the conduction of the body-diode of the synchronous switch is kept

very small compared to the switching period (Ts=5 ns) thanks to the adaptive dead-time



(a) Layout

Dec

. LD

O s

ync

LDO

ctrl

(b) Floor plan

Fig. 6.22. Layout and oor plan of the test-chip (the SMPS with a RF PA)



(a) PCB

(b) Microphotograph of the test chip

Fig. 6.23. Test board and chip microphotograph

Fig. 6.24. LX node voltage for Vbat=3.6 V (200 MHz)



Fig. 6.25. Dynamic sizing of the size of the power stage: control signal vs. the outputvoltage at 100 kHz

Fig. 6.26. Adaptive dead-time: dead-time selection signals vs. output voltage

controller. As shown in Fig. 6.26 the dead-time selection signals (SEL0 and SEL1 ) vary

according to the output voltage of the SMPS and enable the appropriate dead-times as the

output voltage varies. The duration of dead-time td2 across the power range is kept below

400 ps i.e. less than 10% of Ts and in agreement with simulation (Fig. 6.27a, b and c). A

constant duration of about 400 ps is measured for the dead-time td1, which is a bit higher

than the simulation value of about 300 ps but is still low enough (Fig. 6.27d). Therefore the

discretization of the dead-time control with 3 steps is sucient because the power loss due

to the body diode is acceptable (11 mW when the output power is 414 mW in Fig. 6.27c

condition).

6.7.3 Reference tracking

The DC/DC converter was tested in reference tracking with dierent input signal fre-

quencies (Fig. 6.28) and showed no signicant out-phasing within the large signal bandwidth

of the WCDMA signal (3.84 MHz). However the pulse-skipping occurs when the duty cycle

of the power stage becomes very low or very large, leading to more HF ripple on the output

voltage (Fig. 6.28a). Indeed it appeared that the experimental duty cycle range is smaller

than in the simulation.



(a) td2=350 ps at Vout=0.69 V and Iout=123mA

(b) td2=275 ps at Vout=0.95 V and Iout=169 mA

(c) td2=300 ps at Vout=1.5 V and Iout=272 mA (d) td1=400 ps at Vout=0.95 V and Iout=169mA

Fig. 6.27. Measured dead-times at dierent output voltage



(a) f=100 kHz, Vbat=4.5 V (b) f=2 MHz, Vbat=3.6 V

(c) f=4 MHz, Vbat=4.5 V

Fig. 6.28. Reference tracking at dierent input signal frequencies



(a) Eciency at Vbat=3.6 V (b) Input current from the battery atVbat=3.6 V

Fig. 6.29. Comparison of measured eciency and input current from the battery vs. sim-ulation

6.7.4 Experimental eciency

The experimental eciency shows a discrepancy with the simulation for identical condi-

tions (Fig. 6.29a). Many leads are currently being investigated to nd out the cause of the

increased power consumption from the battery. Indeed when we compare the input current

as a function of output power from both simulation and measurement, a signicant overhead

appears in the measurement (Fig. 6.29b).

Obviously the extra power consumption is not due to an interconnect resistance in series

with the power transistors because the experimental LX node voltage waveform does show

any dierence with the simulation waveform at the same node. One possible explanation

is the discrepancy in the model of the parasitic capacitance and resistance of the insulating

substrate layer beneath the buried oxyde of the 0.13-µm CMOS SOI process, but this is still

to be conrmed by the process designers.

6.8 Conclusion

In this chapter we detailed the design of a HF DC/DC converter including new techniques

to improve the eciency at low output power. The simulated eciency curves show the

increase of the eciency thanks to the combination of the resonant gate drivers, the low

voltage operation of the drivers and the dynamic width sizing of the power transistors.

The internal power management is realized by 3 LDOs designed for the supply of low

voltage circuits, so this demonstrator can be directly connected to a battery without requiring

auxiliary voltage sources.

This demonstrator illustrates also the need of high-density capacitors in power manage-

ment systems.

The experimental results presented in this chapter are in line with the simulation, except

for the power eciency which is being investigated. The dynamic features such as the


6.8 Conclusion

regulation bandwdith, the dynamic sizing of the power transistors and the digital adaptive

dead-time control are now validated by the measurement results from the demonstrator.


Conclusion

Synthesis of the work

Throughout this work we have shown the key issues of the design of high frequency

DC/DC converters for a dynamic supply of RF PAs. The formal methodology developed

during this thesis has been applied and validated on demonstrators designed in 0.25-µm

BiCMOS and 0.13-µm CMOS SOI technologies respectively. The goal of this methodology

is to give the designer the keys for a successful design by a detailed analysis of the main

functions. Since every power management design is a trade-o between the size, the velocity

and the power eciency, we intend to show the implications of the primary design choices.

This manuscript is not intended to be a cook book, yet practical equations are provided for

a quick design of a DC/DC converter from the basic specications of the application.

Throughout the CMOS design of the demonstrators, optimized schematics of common

analog blocks such as op-amps, comparator or active lters are presented. But emphasis is

put rather on the novel features that allow an optimal high frequency operation of a DC/DC

converter. These features include the adaptive dead-time control, the dynamic width sizing

of the power stage and the resonant gate driver. At least two optimal implementations of

each function are provided in the two technologies used throughout this work.

A DC/DC converter comprises multiple circuits that have dierent sensitivity to mis-

match, parasitic eects and mutual inuence. Therefore layout guidelines given with the

design procedure lead to a satisfying trade-o in block placement that does not impact (too

much) the power eciency and the functionnality. As an example the reduction of the rout-

ing resistance around the power stage is more critical than additional access resistance to

the low power circuits.

The main objective of this thesis is to decrease the size of passive devices and allow their

integration with the active part of the DC/DC converter. The increase of the switching

frequency was the lead followed to achieve that goal. A theoretical analysis showed the drop

of the eciency that results from the increase of the switching frequency, especially in light

load condition. Our subsequent works focus on design techniques to improve the eciency

and the resonant gate driver proved to be very interesting for that purpose. Thanks to the

recycling of the gate drive energy of the power transistors, a signicant reduction of the

switching losses was obtained which translates into an improvement of the overall eciency


Conclusion

of the converter by as much as 5%. The analysis, the design and the layout of this resonant

gate driver and its inductance took a key position in our work. An important theoretical

study was carried out to estimate the energy saving obtained with the resonant gate driver

compared to the conventional driver and the silicon area penalty. It appears that the wide

duty cycle range required by the EER operation is the main limiting factor of the potential

energy saving brought by the resonant gate driver. The on-chip integration of the driver and

its inductor was possible thanks to the high switching frequency (200 MHz).

In a variable load condition such as in EER, the adaptive dead-time control is necessary

to ensure both safety and power losses reduction when the switching frequency goes high.

An optimal implementation is provided in chapter 3 based on an analog approach and the

probing of LX node voltage proved the ability of the dead-time controller to reduce the

conduction time of the body-diode of the synchronous transistor. A second implementation

based on digital approach is used in the second demonstrator, which is as much eective as

the rst one and less complex.

A further improvement of the eciency at low output power was obtained by combining

the resonant gate driver with two other techniques that are the low supply voltage operation

of the drivers and the dynamic sizing of the width of the power transistors. By reducing

the switching losses, the combination of these three techniques enhances the eciency by as

much as 10% at low output power.

The combination of these design techniques results in a robust, stand-alone DC/DC

converter that can be directly connected to the battery thanks to the LDEMOS transistors

used in the power stage. This feature is essential for the autonomy of portable systems that

run on a Li-ion battery delivering a voltage as high as 5 V. It removes the necessity of a rst

voltage converter to lower the supply voltage as it is required with converters designed with

low voltage technologies.

Perspectives

Higher eciency at light load

With the evolution of the communication standards toward higher data rates, wideband

modulations will be more and more present on mobile platforms. An ecient supply of the

PA will still consist in EER or at least in ET for very wideband applications. High switching

frequency DC/DC converters are the best candidates to fulll the task of dynamic supply

of PAs in such condition. The practical RF output power distribution favors low power

transmissions and the eciency of the DC/DC converter must be improved at low output

power without sacricing the eciency at large output power.

The dynamic width sizing of the power transistors can be further improved in a multicell

and interleaved architecture where each power stage can be completely disconnected from

the rest of the SMPS. A great number of inductors is the main penalty of this architecture.


Conclusion

Besides the PID controller must be recongured each time a power stage is connected or

disconnected.

A shrink in the technology is another lead to improve the eciency while increasing the

switching frequency, but it is necessary to have high-voltage devices that can handle the

battery voltage.

Integration with passive devices in a SiP

Thanks to the relatively high switching frequency, the values of passive devices is low

enough to consider an integration with the techniques described in chapter 5. Two leads can

be considered to achieve that goal. A rst approach consists of assembling an active die,

that contains the active devices of the SMPS, with a die containing the passive components.

A SiP can then be designed by a wire bonding of the two chips or by ip-chiping. The latter

technique being more favorable in terms of area and parasitics.

The ultimate approach consists of designing an inductor with a magnetic core on top

of a die containing the active components of the SMPS and the high density capacitors.

The connection between the inductor and the active die can be done through vias in the

magnetic layer. Compared with the rst approach this is more complex because its supposes

a compatibility of high density capacitors design steps with a standard CMOS technology.

Moreover it requires a fair quality deposition of magnetic alloy on the silicon substrate. But

this approach allows a more compact design and is then more suitable when multiple DC/DC

converters are present on the chip.

EMI issues

The electromagnetic compatibility of a HF DC/DC converter with other systems in its

neighbourhood is a very important study that must be carried out. Such study would allow

to check the inuence of the switching activity of the power stage and the high frequency

ripple current of the lter inductor. In particular the impact of electromagnetic eld radiated

by the lter inductor and the inductors of the resonant gate drivers on the RF PA, which

also includes a balun made by on-chip air-core inductors.

The analysis of the EMI on the performance of the system is a complex work that

requires a combination of electrical and electromagnetic simulation tools. A large degree of

simplication of the models of the system is necessary for reasonable simulation duration.

Can this work serve in other applications than EER?

The design of power management system is a topic that concerns any eld of circuit

design. The features of our demonstrators are specically required in applications such

the Dynamic Voltage Scaling (DVS) of digital circuits. Indeed a large voltage regulation

bandwidth and a sucient dynamic range are the main requirements for the dynamic supply


Conclusion

of digital cores in a digital SoC. In that particular application the energy saving of the

resonant gate driver can be high because the output range required in the DVS is less than

in EER. In that purpose multiple voltage islands can be designed in the digital SoC with a

DC/DC converter dedicated to each voltage island.


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List of publications

M. Bathily, F. Hasbani and B. Allard, Analysis and optimization of HF DC/DC

converters for RF polar transmitters, IEEE PowerSoc'08, Cork, Ireland, Poster pre-

sentation

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HF, in Proc. Journée des Jeunes Chercheurs en Génie Electrique, Lyon, 2008.

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integrated DC/DC converters, in Energy Conversion Congress and Exposition, 2009.

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HF DC/DC converters by resonant gate drivers, IEEE PowerSoc'10, Cork, Ireland,

Poster presentation

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switching frequency and analog step-down converters, IEEE Transactions on Power

Electronics (submitted)

M. Bathily, B. Allard and F. Hasbani, Integrated resonant gate driver and high

switching-frequency DC-DC converters, IEEE Power Electronics Letters (accepted

for publication)

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Bandwidth Analog Integrated DC/DC Step-down Converters, Journal of Low Power

Electronics (Elsevier) (accepted for publication)


Abstract

Today's mobile communication devices include many features and deliver data with high rates. In order

to increase the life time of the battery, it is necessary to enhance each block eciency, i.e. to provide and

to design ecient power management system to deliver energy to the dierent parts of the device. The

RF power amplier (PA) that feeds the antenna is the main power consumer on a mobile platform. The

Envelope Elimination and Restoration (EER) technique constitutes an interesting approach to increase

the eciency of the RF PA when variable-envelope modulations such as WCDMA or WLAN are used. A

DC/DC converter with a large bandwidth is then required to supply the PA with the envelope of the RF

signal. This PhD work focuses on the design of high switching frequency DC/DC converters for WCDMA

EER. Besides the monolithic integration of the converter and the RF PA on a single chip requires an

increase of the switching frequency beyond the hundred of MHz in order to shrink the size of passive

devices. A formal design methodology is developed to specify the converter and the main building blocks

of the system. This methodology derives the specications of the converters from those of the RF standard

in terms of bandwidth and output power. New architectures are proposed to overcome the limitation of

the conventional architecture and to improve the eciency of the converter. The study focuses the light

output power range. A practical use of this methodology is given through the design of demonstrators in

0.25-µm BiCMOS and 0.13-µm CMOS SOI technologies and experimental results are provided to validate

the methodology and the simulation results.

Keywords: Analog circuits design, buck converter, BiCMOS, CMOS, DC/DC conversion, EER,

PWM, WCDMA, SMPS

Résumé

Les appareils de communication mobile actuels intègrent de plus en plus de fonctionnalités et transmettent

des données à des débits toujours plus élevés. Pour étendre la durée de vie de la batterie, il est nécessaire de

concevoir une bonne stratégie de gestion d'énergie et d'alimentation des diérents circuits. L'amplicateur

de puissance (PA) radio est le principal consommateur d'énergie. La technique de reconstruction d'enveloppe

permet d'augmenter le rendement énergétique de l'amplicateur de puissance lorsque les modulations à

amplitude variable comme le WCDMA ou le WLAN sont utilisées. Dans cette architecture un convertisseur

DC/DC est utilisé pour alimenter l'amplicateur radio avec l'enveloppe du signal RF. Ce travail de thèse

décrit la conception des convertisseurs à découpage DC/DC à haute fréquence pour alimenter un PA dans

le cadre de la reconstruction d'enveloppe pour le standard WCDMA. De plus l'intégration monolithique

du convertisseur et du PA impose d'augmenter la fréquence de découpage du convertisseur pour réduire

la taille des composants passifs. Une méthodologie formelle est développée pour spécier le convertisseur

et ses principaux circuits. Cette méthodologie déduit les spécications du convertisseur à partir de celles

du standard RF, notamment en terme de bande passante et de puissance. De nouvelles architectures sont

proposées pour dépasser les limitations de l'architecture classique et améliorer le rendement du convertisseur.

L'application pratique de cette méthodologie est eectuée à l'aide de démonstrateurs réalisés dans les

technologies BiCMOS 0.25 µm et CMOS 0.13µm SOI. Les résultats expérimentaux obtenus permettent de

valider la méthodologie et conrment les résultats de simulation.

Mots-clés: Circuits intégrés analogiques, BiCMOS, CMOS, convertisseur DC/DC, PWM, WCDMA


FOLIO ADMINISTRATIF

THESE SOUTENUE DEVANT L'INSTITUT NATIONAL DES SCIENCES APPLIQUEES DE LYON

NOM : BATHILY DATE de SOUTENANCE : Décembre 2010 (avec précision du nom de jeune fille, le cas échéant)

Prénoms : Malal

TITRE : Design of DC/DC converters for RF Systems-on-Chip

NATURE : Doctorat Numéro d'ordre : 2010-ISAL-0112

Ecole doctorale : EEA

Spécialité : Génie Electrique

Cote B.I.U. - Lyon : T 50/210/19 / et bis CLASSE :

RESUME : Les appareils de communication mobile actuels intègrent de plus en plus de fonctionnalités et transmettent des données à des débits toujours plus élevés. Pour étendre la durée de vie de la batterie, il est nécessaire de concevoir une bonne stratégie de gestion d'énergie et d'alimentation des différents circuits. L'amplificateur de puissance (PA) radio est le principal consommateur d'énergie. La technique de reconstruction d'enveloppe (Envelope Elimination and Restoration) permet d'augmenter le rendement énergétique de l'amplificateur de puissance lorsque les modulations à amplitude variable comme le WCDMA ou le WLAN sont utilisées. Dans cette architecture un convertisseur DC/DC est utilisé pour alimenter l'amplificateur radio avec l'enveloppe du signal RF. Ce travail de thèse décrit la conception des convertisseurs à découpage DC/DC à haute fréquence pour alimenter un PA dans le cadre de la reconstruction d'enveloppe pour le standard WCDMA. De plus l'intégration monolithique du convertisseur et du PA impose d'augmenter la fréquence de découpage du convertisseur pour réduire la taille des composants passifs. Une méthodologie formelle est développée pour spécifier le convertisseur et ses principaux circuits. Cette méthodologie déduit les spécifications du convertisseur à partir de celles du standard RF, notamment en termes de bande passante et de puissance. De nouvelles architectures sont proposées pour dépasser les limitations de l'architecture classique et améliorer le rendement du convertisseur. L'application pratique de cette méthodologie est effectuée à l'aide de démonstrateurs réalisés dans les technologies BiCMOS 0.25 um et CMOS 0.13 um SOI. Les résultats expérimentaux obtenus permettent de valider la méthodologie et confirment les résultats de simulation.

MOTS-CLES : Circuits intégrés analogiques, BiCMOS, CMOS, convertisseur DC/DC, EER, PWM, WCDMA

Laboratoire (s) de recherche : Université de Lyon, Ampère, INSA Lyon, CNRS UMR 5005

Directeur de thèse: Professeur Bruno ALLARD

Président de jury : Corinne ALONSO, Pr.

Composition du jury : Corinne ALONSO, Pr. Yves LEMBEYE, Pr. José Antonio COBOS, Pr. Frédéric HASBANI, Bruno ALLARD, Pr.


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