For Peer Review

SHE Based Multipulse operation of Single Phase Cascaded

H-Bridge Multilevel Microinverter for Rooftop PV Systemwith Isolated Loads

Journal: European Transactions on Electrical Power

Manuscript ID: ETEP-14-0951

Wiley - Manuscript type: Research Article

Date Submitted by the Author: 24-Nov-2014

Complete List of Authors: Verma, Vishal; Delhi Technological University, Electrical Engineering

Sayal, Aseem; Delhi Technological University, Electrical Engineering Kumar, Amritesh; Delhi Technological University, Electrical Engineering

Keywords: Symmetric Polynomials, Cascaded H-bridge multilevel inverter, Maximum Power Point Tracking

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1

Selective Harmonic Elimination Based operation of

Single Phase Cascaded H-Bridge Multilevel Micro-

Inverter for Isolated Rooftop PV System

Aseem Sayal, Amritesh Kumar, Vishal Verma

Delhi Technological University, Delhi, INDIA

Abstract

With the advent of the era of distributed generation (DG), the rush for efficiency improvement of rooftop PV system has

emerged as a grey area for research. The paper presents an efficient topology of Single Phase cascaded H-Bridge multilevel

Inverter (CHBMLI) for rooftop PV system. The proposed inverter reduces the size of output filter and provides transformerless

operation by transferring the requisite power to different DC buses of CHBMLI, thus eases the way out for highly effective

low-cost power processing systems that support the rooftop photovoltaic (PV) installations for residential applications. The

first stage of the two stage conversion system deals with a MPPT controller for maximum power point tracking, while the

second stage employs CHBMLI which maintains the requisite voltage at the DC buses of cascaded 7level CHBMLI from a

single DC MPPT tracked PV source. The new concept of multipulse switching of the cascaded bridges ensures elimination of

low order harmonics, thus enhancing the overall efficiency of the proposed inverter. The irradiance variation analysis of

switching vectors by proposed hypothesis for the CHBMLI to implement microinverter and its operation amidst is also

presented. The performance of the proposed system is validated through simulation results in MATLAB Simulink

environment. The simulation results demonstrate the effectiveness of the proposed controller under irradiance variations while

regulating the inverter output voltage.

Index Terms—Cascaded H-bridge multilevel inverter (CHBMLI), Fourier Transform, Incremental Conductance, Maximum

Power Point Tracking (MPPT), Symmetric Polynomials.

1. Introduction

The reserves of fossil fuels are depleting fast and their prices are on the rise. In order to meet the future energy demands,

renewable sources of energy like Solar and Wind have shown promising future [1]. The rooftop application involving single

phase wiring can easily be fed from PV source for the household use, thereby reducing the burden on the power grid. A double

stage PV single phase grid connected system with high frequency transformer has been reported in literature [4]. The popular

single H-bridge inverter used in house hold requires bulky L-C filter to improve the waveform profile, making it unsuitable for

grid connection, which is requisite for rooftop PV systems [2]. In recent times Multilevel Inverter (MLI) has gained great

interest due to their high conversion efficiency and less bulky filter [3].Amongst efficient topologies, Cascaded H-Bridge

based MLI has emerged as most popular due to modularity in structure and ease in increasing the levels of MLI for lower THD

with improved power factor, low switching frequency and high voltage, power applications [5]-[7].

The nearness of PV farms cannot be ascertained in the vicinity of load centers due to space constraints. It is therefore roof top

PV which is envisaged as potential contender for the distributed generation (DG) concept. Microinverters, which are generally

used for rooftop PV system where either single large PV panel or couple of PV panels are connected with one inverter to feed

the load is obvious point of attraction [8]. These PV systems are either configured in centralized or multistring format [9].

Centralized configuration has added advantage of single DC link with centralized MPPT controller and control, which is also

simpler as compare to multistring configuration which has multi MPPT controllers, operating with multiple DC sources, buses

[10]. The household two level bridge inverters are popularly connected with the different configurations for PV system and are

reported to suffer from problems of high value filter requirements [11].

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Conventional CHBMLI requires n number of different DC sources for n number of H-bridges to get the 2n+1 levels of inverter

output using symmetrical sources. Such proposition incurs huge costs due to the use of battery as load leveler if PV

panel/string is considered connected across the DC bus of each H-Bridge or connection of separate DC sources to get the

benefit of modularity of CHBMLI. The avoidance of multiple DC sources has been reported by use of n-1 number of

capacitors to emulate as DC sources [12]-[14]. Such configurations are suitable for 3 phase applications and have been detailed

in literature along with the analysis of their switching angles [15]-[17].

In PV system, the evacuation of full generated power from the panels is the main point of concern, and hence MPPT controller

is of high importance. Incremental Conductance being stable and oscillation free algorithm for MPPT, offers a good solution

[18]-[20]. In addition the transient response of the MPPT controller may be improved by incorporating temperature loop and

isolation loop [21]. In the proposed system, Incremental Conductance based MPPT controller is advocated in its first stage and

a cascaded 7 level inverter using only a single DC power source at first stage and one capacitor imitating other DC source in its

second stage with modified control scheme in standalone mode is proposed. The analysis of scheme for computing switching

angles to obtain output 7 level waveform using symmetric polynomials solving approach is also presented. The scheme

presents centralized controller for single DC link voltage control. The scheme is capable of adding more number of levels by

adding more number of H-bridges with capacitors as virtual DC source. Increasing the levels would better shape the voltage

output more close to sinusoid and the current nearly sinusoidal, thereby reducing the THD in current. The light weight, small

size, lower switching losses with small LC filter at the output of inverters increases the efficiency tremendously. The results of

the proposed new PWM control strategy for computation of desired switching angles feeding resistive loads with load

perturbation is presented under MATLAB environment under varying insolation conditions. The transient response for

dynamically perturbed loads with THD analysis is also demonstrated to validate its effectiveness in meeting the requisite

standards.

2. System Configuration

This section describes the configuration of PV panel, DC-DC converter with DC link connected battery source along with DC

link tank capacitor in stage 1 and multilevel cascaded H-Bridge inverter in its stage 2. The proposed system configuration is

shown in Fig. 1. The considered loading at inverter terminals is resistive loading.

Fig. 1.Proposed configuration of system.

CHB Controller MLI Gating

A

N

MPPT

PV

I V

DC

DC

v H2

v H1

+

+

-

- Duty

B

A

T

T

E

R

Y

S 11

S 12

S 13

S 14

1 1 ’ V

H2

H1

S 21

S 22

S 23

S 24

2 2 ’

V/2

R

Load

Gating Signals Stage 2 Stage 1

Page 2 of 11

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The modeling and specifications of PV system and MPPT controller is referred from prior publication [22]-[23].The Kyocera

based PV panels are considered for realizing a PV array of 0.8 kW in two strings format with 2 numbers of such panels in

series for each string as shown in Fig.2. The parameters of the panel are shown in Table I.

Table 1.Parameters of the Kyocera based commercial solar array at nominal operating conditions (T=25oC, S=1000W/m2)

The inverter is operated using PV array as a single DC source for first H-bridge and capacitors as the DC sources for the rest of

the bridges. The topology does not utilize transformer whilst meeting the total harmonic distortion and power factor

requirements.

3. Realization of Multilevel Output

The DC bus for the first H-bridge (H1) is powered by MPP tracked PV fed power with an output voltage of V, while the virtual

DC source for the second H-bridge(H2) is a capacitor which is maintained at a nominal voltage of V/2. The output voltage of

the first H-bridge is denoted by vH1and the output of the second H-bridge is denoted by vH2so that the output of this two DC

source cascaded multilevel inverter is vout=vH1+vH2[24].

By closing the switches S1 and S4 of H1, the output voltage vH1can be made equal to V, closing the switches S2 and S3 of H

1

made the output voltage vH1 equal to-V, while the output voltage of H1can be made equal to 0 when switch S1 is closed for i>0

Ipmax 7.61A

Vpmax 26.3V

Pmax 200.13

Isc 8.21A

Voc 32.9V

Kv -0.1230 V/K

KI 0.0032 A/k

Ns 54

t

Fig. 3.Output voltage waveform of a 7-level cascade multilevel inverter.

Fig. 2. PV panels arranged in two strings configuration for 0.8 kW PV array.

Blocking Diodes

Bypass Diodes

String

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and switch S3 is closed for i<0. Similarly, the output voltage of H2

can be made equal to,-V/2, or V/2 by opening and closing its

switches appropriately. Therefore, the output voltage of the inverter (vout) can have the values-3V/2,-V , -V/2, 0,V/2 , V and

3V/2 , which constitute seven levels. The output waveform of a 7 level cascaded H-Bridge inverter is shown in Fig. 3. Table II

shows the generation of output voltage waveform using the topology depicted in Fig.1.

t vH1 vH2 vout=vH1+vH2

0 ≤ t ≤ t1 0 0 0

t1 ≤ t ≤ t2 0 V/2 V/2

t1 ≤ t ≤ t2 V -V/2 V/2

t2 ≤ t ≤ t3 V 0 V

t3 ≤ t ≤ T/4 V V/2 3V/2

Table II. Output Voltages for a 7-Level Inverter Table III. Capacitor Voltage Regulating Scheme

Depending upon the magnitude of capacitor voltage vc and the direction of inverter current I, the output voltage level V/2 can

be achieved in two different ways either for capacitor charging or discharging. Table III summarizes all the cases to charge and

discharge capacitor when output voltage is maintained at V/2. The capacitor charging cycle is kept greater than the capacitor

discharge cycle to regulate the capacitor voltage. Fig. 4 (a) shows the gating signals generated of H-bridges H1 and H2 for

capacitor charging to a level vout=V/2. Fig. 4 (b) shows the gating signals generated when capacitor is discharged for vout=V/2.

Here tI1=T/2-t1,t

I2=T/2-t2andt

I3=T/2-t3.

4. Control Scheme

This section deals with the control scheme of CHBMLI and battery controller in subsection 4.1 and 4.2 respectively.

4.1 Control Scheme of CHBMLI

The main objective of control scheme of CHBMLI is to switch the levels of voltage at appropriate times so that output voltage

shapes to near sinusoidal ac voltage. The control scheme is based on selective harmonic elimination and 3rd

, 5th

and 7th

harmonics are eliminated. The previous reported literature deals with 3 phase system and accordingly only two lower order

harmonics, 5th

and 7th

have been considered for elimination [20]. The proposed scheme for single phase system using

symmetric polynomials [25]-[28] has been modified to eliminate 3rd

harmonic entirely and minimizing 5th

and 7th

harmonics.

The output voltage of CHBMLI is 7 level staircase ac waveform which is passed through small LC filter to produce desired

System Sate vH1

vH2

vout=vH1+vH2

vc<V/2, i>0

V -V/2 V/2

vc<V/2, i<0

0 V/2 V/2

vc>V/2, i>0

0 V/2 V/2

vc>V/2, i<0

V -V/2 V/2

0

1

S11

0

1

S12

0

1

S13

0

1

S14

0

1

S21

0

1

S22

0

1

S23

0

1

S24

0

1

S11

0

1

S12

0

1

S13

0

1

S14

0

1

S21

0

1

S22

0

1

S23

0

1

S24

0

1

S11

0

1

S12

0

1

S13

0

1

S14

0

1

S21

0

1

S22

0

1

S23

0

1

S24

0

1S

11

0

1

S12

0

1

S13

0

1

S14

0

1

S21

0

1

S22

0

1

S23

0

1

S24

(a) (b) Fig. 4. Gating signals of H1 and H2 when (a)capacitor is charged at vout=V/2and (b) capacitor is discharged at vout=V/2.

.

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sinusoidal voltage. The fourier series expansion of the output 7 level staircase ac voltage waveform is given by (1), considering

the nominal capacitor voltage is held at V/2.

1 2 3

4 1( ) cos cos cos sin

1,3,5....2

VV wt nwt nwt nwt nwt

n n

wheret1, t2 and t3 are the switching times. If the desired fundamental voltage isV1, switching times t1, t2 and t3 are determined

since (1) becomes V(wt)=V1sin(wt). For single-phase systems, the main objective of the proposed scheme is to cancel the

3rd

harmonic and to minimize 5th

and 7th

order harmonics as they tend to dominate the THD. The mathematical statement of

these conditions is given in eqns. (2)-(4).

1 2 3 1

4cos cos cos

2

Vwt wt wt V

31 2cos 3 cos 3 cos 3 0wt wt wt

1 2 3 1 2 3cos 5 cos 5 cos 5 cos 7 cos 7 cos 7wt wt wt wt wt wt

(4)

The above set of equations form three transcendental equations with three unknown’st1,t2 andt3. These equations are solved

using Symmetric polynomials approach. Assuming , and , (2)-(4) can be

expressed by (5)-(7).

11 1 2 3 0,

4

2

Vz k k

V

(5)

3

3

31

4 3 0i ii

z

(6)

3

3 5

51

5 20 16 0i i ii

z

The polynomials , and as given in (5)-(7) are symmetric polynomials. Their elementary symmetric

polynomials , and are given by (8)-(10).

3

1 1 2 31

ii

(8)

3 3

2 1 2 1 3 2 311

i jii

i j

(9)

3

3 1 2 31

ii

(10)

With function in terms of , the polynomials (5)-(7) may be described as:

1 1z k

(11)

3

3 1 1 1 2 33 4 12 12z

(12)

is minimum

(7)

(1)

(2)

(3)

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3 5 3 2 2 3 5

5,7 1 1 1 1 2 1 2 1 2 3 1 3 2 3 1 1 1

7 3 5 2 3 2 3 2 4

1 1 2 1 2 1 2 1 2 1 2 1 2 3 1 3 1 3

2 2

2 3 1 2 3 2 3

5 20 16 60 80 80 60 80 80 7 56 112

64 168 560 448 560 896 448 168 560 448

560 1344 448 448

z

2

1 3 1

(13)

Using 1 1 0z k to eliminate 1 so that

3

3 2 3 3 2 3 2 3, 3 12 12 12, ,y z k k k k

(14)

2, 3

3 5 3 2 2

5,7 5,7 2 3 2 2 2 3, , 5 20 16 60 80 80 60 80 803 2 3

3 5 7 3 5 2 3 2 37 56 112 64 168 560 448 560 896 448 168

2 2 2 2 2 2 3

2 4 2 2 2560 448 560 1344 448 448

3 3 2 3 2 3 2 3 3

y z k k k k k k k k

k k k k k k k k k k

k k k k

1

(15)

Eliminating 2 , the resultant polynomial is given by

3 5 23 33, 5 3 3 2 3 5 2 3 2

3 5 7 2 2 4 2

3 3 3 3 3

1Re , , 45 60 16 240 180, , 9

1189 504 336 64 4032 4032 4032 2268 3024 1

27

y yq s y y k k k k

k k k k k k k

(16)

Which is only second degree in . For each value of k, is solved to obtain the roots . These roots are

then used to solve for the root resulting in the one set of 2 sets of values of as the only possible

solutions to (14)-(16). For each solution triplet the corresponding values of are calculated using

resultant method to obtain the switching times.

1 1 2 3 1 1 2 3, , 0r

(17)

2 1 2 3 2 1 2 1 3 2 3, , 0r

(18)

3 1 2 3 3 1 2 3, , 0r

(19)

That is, (20)-(22) is computed.

2 2

1 2 3 1 1 2 3 2 1 2 3 1 2 1 2 2 1 3 2 3 3, Re , , , , , ,s s r r

(20)

2 2

2 2 3 1 1 2 3 2 1 2 3 1 3 1 2 3 2 3 2 3, Re , , , , , ,s s r r

(21)

2

2 3

3 1 2 3 2 2 3 2 3 2 3 3 3Re , , , ,1

s s s s

(22)

The solutions of (14)-(16) are substituted into (20)-(22) and the roots are obtained. For each , is solved

for the roots . Finally, is solved for to obtain the triplets as the only possible solutions for eqns. (5)-

(7). This finite set of possible solutions satisfying condition formsthe solutions of eqns. (5)-(7).

4.2 Control Scheme of Battery Charge Controller

Working in standalone mode of operation often requires some storage elements for load leveling. To maintain DC link

capacitor voltage, a battery storage system is connected through buck-boost converter as shown in Fig. 5. The constant DC link

PV

Pane

l

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voltage ensures proper balance between load demand and supply. The excess generation charges the battery and deficiency is

met from the battery when operated in boost mode. The controller for battery is shown in Fig. 6.

5. MATLAB Based Simulation

A single-phase 50 Hz rooftop PV system consisting of 7 level cascaded H-Bridge inverter, PV array regulated at output

voltage of 230 V through DC-DC boost converter and battery is simulated in MATLAB environment. The considered PV array

of 800W is realized by connecting 2 panels in series and 2 in parallel. The PV panel consists of 54 cells connected in series.

The open circuit voltage of panel is 32.9V and short circuit current of panel is 8.21A. The boost converter utilizes 5mH

inductor, MOSFET switch and fast switching diode. The DC link capacitor of 1000uF is used at DC link which is regulated at

voltage of 230V. The virtual DC source i.e. capacitor of 6000µF regulated at a voltage level of 130V and is used in the other

H-Bridge of inverter to realize different levels in the output voltage. The LC filter with inductance of 3mH and capacitance of

1µF is used to smooth out the 7 level output voltage in order to obtain sinusoidal output voltage and current. The MATLAB

simulation block diagram of the topology is shown by Fig. 7.

Small Battery

System

2

1

L -Ib

Battery

Gating Pulse

Controller

Vdc

+

-

PI PI Comparator

g Vdc

Vdc*

IPV

-1

+

-

Ib

+

- +

-

Discrete,Ts = 5e-005 s.

powergui

v+-

v+-

Voltage

g

A

B

+

-

g

A

B

+

-

LPF

LPF

cap_vol fundamental_voltage

current

gate_upperbridge

gate_upperbridge FourierMag

Phase

i+

-

c 12

(a)

Fig. 5.The Battery system.

Fig. 6.The gating pulse control for battery system.

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Fig. 7. (a) Model of cascade multilevel inverter, (b) DC Link power management with MPPT controller, (c)Angle Generation Subsystem, (d) Gating

Generation subsystem for case 1 when capacitor is charged for vout=V/2, (e) Gating Generation subsystem for case 2 when capacitor is discharged for vout=V/2,

(f) Capacitor voltage controller subsystem.

The equations to calculate switching times in order to eliminate harmonics are written in MATLAB editor and are integrated

with the main system model using Interpreted MATLAB Function. The gate signals are generated using variable time delay

2

-n

1

+p

v+-

vpv1

v+-

vpv

i+

-

i+

-

i+

-

ipv

+

-

SOLAR PANEL

g DS

g DS

g DS

Param

MPPT

Parameters

V

I

Gate

Power

MPPT

Controller

i+

-

I1

V_PV1

I_PV1

v out

In2

Out1

Out2

Battery

Controller

+

_

m

Battery

ibl

ipval

V_PV1

I_PV1

Vc

Nominal Fundamental Voltage

Vc

Nominal Capacitor Voltagetheta_2

theta_1

theta_3

cap_vol

fundamental_voltage

PI

PIIn1

In2

Angle Generation

gate_lowerbridge_case1

gate_upperbridge_case1In1

In2

In3

Out1

Out2

Gate Signals Case 1

theta_2

theta_3

theta_1

gate_lowerbridge_case2

gate_upperbridge_case2In1

In2

In3

Out1

Out2

Gate Signals Case 2

theta_2

theta_3

theta_1

gate_upperbridge

gate_lowerbridge

gate_lowerbridge_case1

gate_lowerbridge_case2

gate_upperbridge_case2

gate_upperbridge_case1 In1

In2

In3

In4

Out1

Out2

Capacitor Voltage Controller

(d) (e)

D

C/

A

C

C

on

ve

rte

r

(f)

(c)

(b)

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block. The PV array along with battery is shown in Fig. 7(b). Fig. 7 (c) shows the subsystem of angle generation. Fig. 7 (d) and

(e) describes the subsystem generating gating signals for two cases in order to regulate capacitor voltage. Fig. 7(f) implements

the capacitor voltage controller and selects the gating signals to be given to bridges based on magnitude of capacitor voltage

and direction of current.

6. Performance Evaluation

The proposed system configuration is simulated under MATLAB Simulink environment and various waveforms obtained for

inverter, load voltage, load current and capacitor voltage are shown in Fig. 8. From fig. 8(a) it can be noticed that second level

in the output voltage waveform is maintained at constant level of 230V whereas there are small fluctuations observed in the

first level and the third level, since both incorporate the fluctuating capacitor voltage. The voltage spikes occur at multiples of

(1/f) seconds because both the sources (PV source and capacitor) are being switched in or out simultaneously. This occurs due

to the differences in dead time of the H-bridge switches as well as the timing of turning the switches on and off not being

exactly the same between the two H-bridges. The output voltage and current waveforms are shown respectively in Fig. 8(b)

and Fig.8(c). The resistive load is decreased by 13.77%, i.e. from 791.2W to 682.2W at time t=0.2s. It can be clearly seen

through Fig. 8(b) and (c) that output ac voltage is maintained at its nominal RMS value of 230V while the current is decreased

by 13.42%, i.e. from RMS value of 3.43A to 2.97A due to decreased load demand. The capacitor voltage which is regulated at

its nominal voltage of 130V is shown in Fig. 8(d). It can be seen that the fluctuations in the voltage is in the range of ±1%. Fig.

9 shows the zoomed version of Fig. 8(d) for the time period of 0.3s-0.4s. It can be noticed that capacitor voltage dips by 1%

when it is discharged (in case when vout = V/2 or vout = 3V/2) and rises by 1% when it is charged (in case vout = V/2).

The power flow exchange between PV array, battery and resistive load is descripted in Fig. 10. Fig. 10(a) shows the output

power from PV array. The maximum output power obtained from PV array is 802W when the insolation is 1000 W/m2 for the

time period 0-0.3s. At time t=0.3s, insolation is reduced to half of its initial value, i.e. to 500W/m2 and output power obtained

from PV array is reduced to 392W. The decrease in PV generation leads to discharging operation of batteries to meet the load

demand. This resulted in increase of battery average power from -380W to 64W. Fig. 10(b) shows the instantaneous and

average battery power and DC Link power. The average value of DC link power is 574W for the time period 0-0.2s while it

reduces to 456W for the time period 0.2-0.4s. It can be seen that batteries are charged during the time period 0-0.3s, since the

demanded power from DC Link is less than power obtained from PV array, and the batteries are shown discharged during time

period 0.3-0.4s, when the power obtained from PV array is less than required DC Link power.

Fig. 8. (a) 7 level staircase output voltage waveform, (b) Output voltage waveform, (c) Output current waveform, (d) Capacitor Voltage waveform.

Fig. 9.Zoomed steady-state Capacitor Voltage waveform.

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The FFT analysis of output voltage and current is performed and shown in Fig. 11 and Fig. 12 respectively. The total harmonic

distortion in voltage is 1.59% with third, fifth and seventh harmonics being 0.86%, 1.13% and 0.59% respectively whereas the

total harmonic distortion in output current is 1.36% with third, fifth and seventh harmonics being 0.71%, 0.98% and 0.58%

respectively. It can be observed that third harmonics are not completely eliminated in output voltage and current waveforms.

This is due to the delay in computation of switching times in MATLAB. The charging/discharging of capacitors depends on

switching times, therefore there is a slight deviation of capacitors voltages from their nominal value, resulting in THD in 3rd

harmonics.

7. Conclusion

The performance of single phase rooftop PV system comprising of PV array, DC-DC boost converter, battery and cascaded

H-bridge multilevel inverter topology has been successfully demonstrated under load perturbation and irradiance variations.

The MPP tracking is satisfactorily done by Incremental Conductance algorithm to obtain maximum power from the PV

array. The cascaded multilevel inverter topology required connection at only one level and capacitors acted as voltage source

for the other H-bridges. The switching times are computed using symmetric polynomials approach for elimination of 3rd

and

5th

harmonics and reduction of 7th

harmonic. The simulation results verify the feasibility and suitability of algorithm for the

proposed topology. The voltage level of the capacitors is regulated while at the same time the switching angles are

accurately calculated to eliminate 3rd

, 5th

and reduce 7th

harmonics in the output waveform, thus minimizing the filter

requirements. The proposed switching strategy is capable of supplying majority light load applications fed from PV arrays.

References

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Fig. 11.FFT of output voltage.

Fig. 10. (a) PV Array output power and (b) Instantaneous and Average Battery power and DC Link power.

Fig. 12.FFT of output current.

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