floorplanning of pipelined array (fopa) modules using sequence pairs
DESCRIPTION
Floorplanning of Pipelined Array (FoPA) Modules using Sequence Pairs. Matt Moe Herman Schmit. Outline. Pipelined Arrays Previous Sequence Pair work Sequence Pair additions Results. Cryptography. Control. Signal Processing. Microprocessor. Memory. System of the Future. - PowerPoint PPT PresentationTRANSCRIPT
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Floorplanning of
Pipelined Array (FoPA) Modules using
Sequence Pairs
Matt Moe
Herman Schmit
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Outline
• Pipelined Arrays
• Previous Sequence Pair work
• Sequence Pair additions
• Results
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System of the Future
• Soft IP cores– hardware accelerators– pipelined arrays
Microprocessor
Control
Memory
Cryptography
Signal Processing
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Pipelined Arrays
• Systolic architecture
• Easy to compile to
• Fast throughput aftersynthesis
• Structure lost duringphysical design
Logic
Logic
Logic
Logic
Logic
Logic
pipeline stage
array adjacent pipelinestages
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Physical Design of Pipelined Arrays
• Maintain structure
• One pipeline stage =one floorplan module
• Use floorplanning tools to create placement constraints
Logic
Logic
Logic
array adjacent modules
floorplan module
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How do you maintain the structure?
• If modules were the same size - trivial solutions
23456789
1
5
9
3
82
1
6
7
4
1
2
8
7
9
6
3 4 5
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More interesting problem…
• Modules vary in size
• Wire Congestion– Created by
non-adjacencyof modules
– Forces extra areausage
2
1
0
3
6
9
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8
4
5
11
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Classic Simulated Annealing of Sequence Pairs
• Sequence Pair– Floorplan representation that describes
directional constraints between every possible pair of blocks
– Large design space
• H. Murata, et.al., “VLSI Module Placement Based on Rectangle Packing by the Sequence Pair,” IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 15, no. 12, pp. 1518-1524, December 1996.
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Classic Swap Move
D
AC
B
A B C D
D A
C
B
D
A
C
B
A D C B
D A
C
B
D
A
C B
D
A
C B
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ABCD DACB
A B C D
D
A
C
B
D
A
C
B
Oblique Constraint Graph
A B C D
D
A
C
B
D
A
C
B
Oblique Connnectivity Graph
D
AC
B
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FoPA Delete / Insert Move
D
AC
B
A B C D
D A
C
B
D
A
C
B
A B C D
D B
A
C
D
A
C
B
D
AC
B
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D
AC
B
A B C D
D A
C
B
D
A
C
B
A C B D
D A
C
B
D
A C B
D
A C B
Restricted Delete / Insert Move
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This looks better…
• All logically array adjacent elements are adjacent in thefloorplan
• Reduced wirecongestion
9 8 7
10 11 6
3
2
4 5
01
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Floorplanning Results
• Block sizes created from fastest synthesized designs
• Each point represents the best score from 10 annealing runs
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Floorplan Utilization
97.0%
97.5%
98.0%
98.5%
99.0%
99.5%
100.0%
1-D DCT IDEA(short) IDEA(long) 2-D DCT LDPC
ClassicFoPA
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Longest Wire Length
0
2
4
6
8
10
12
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1-D DCT IDEA(short) IDEA(long) 2-D DCT LDPC
Classic
FoPA
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Results afterPlacement and Routing
• Floorplans used as constraints in Monterey Design System’s Dolphin
• Iteratively expand floorplans by 1% until routable
• Delay reported by Dolphin
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Added Area
0.00%
10.00%
20.00%
30.00%
40.00%
50.00%
60.00%
70.00%
80.00%
1-D DCT IDEA(short) IDEA(long) 2-D DCT
Unfloorplanned
Classic
FoPA
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Added Delay
0.00%
5.00%
10.00%
15.00%
20.00%
25.00%
30.00%
1-D DCT IDEA(short) IDEA(long) 2-D DCT
Unfloorplanned
Classic
FoPA
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Average Placed and Routed Results
Added Area Added Delay
Unfloorplanned 19.95% 12.60%
Classic 41.84% 16.96%
Classic+LSP 37.96% 15.51%
FoPA 15.00% 8.50%
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Conclusions
• New restricted move set– Creates better placement of modules
during floorplanning synthesis– Creates smaller and faster designs after
placement and routing
• In paper– New wire length model– Cost Metric