floating point arithmetic with vhdl

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Francis O'Malley

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1 month ago

floating point arithmetic with vhdlCan anyone help me floting point arithmetic on fpga. I am using vhdl for coding. There is afloating point library that I am using. But I can not use exactly. I want to make this operation:

x := 3.1415;y := 32.232434;z := x * y;

how can I make this operations in " www.eda.org/fphdl " this library?

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1 month ago • Like

Sanjay Kumar Basappa Miragi • hiu need an library or an code which will perform this operation in xilinx or altera?


Emre Kirkaya • I am allready using library. And I can make a operation with thisnumbers.

a = 01000010110001010110011001100110b = 01000010101010110110011001100110

but I want to use a number like 3.1415.

1 month ago • Like 2

Francis O'Malley • Hi Emre:

Using the floating point arithmetic library you specifically mentioned (atwww.eda.org/fphdl), have you downloaded "fixed_float_types_c.vhdl", "fixed_pkg_c.vhdl"and "float_pkg_c.vhdl" and analysed (compiled) them into a library called“ieee_proposed”?

Then you can simply write:

library ieee_proposed;use ieee.float_pkg.all;…variable x, y, z : float32;beginx := to_float (3.1415, x); -- Uses “x” for the sizing onlyy := to_float (32.232434, y);z := x * y;………

This is explained in the user's guide at http://www.eda.org/fphdl/Float_ug.pdf

Emre Kirkaya • Hi Francis O'Malley ,

Actually I tried to use your code but I could not synthesize. XST did not allow. How can Iuse the code. My code is;

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1 of 5 12/12/2012 7:21 PM

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library ieee_proposed;use ieee_proposed.float_pkg.all;

entity to_float isend to_float;

architecture Behavioral of to_float isvariable xf,yf,zf : float32;beginxf := to_float(input1,32);yf := to_float(input2,32);zf := xf * yf;end Behavioral;

And XST gave me these erors;

ERROR:HDLCompiler:806 - "C:/Users/Kk/CDwVHDL/tofloat/to_float.vhd" Line 17:Syntax error near ":=".ERROR:HDLCompiler:806 - "C:/Users/Kk/CDwVHDL/tofloat/to_float.vhd" Line 18:Syntax error near ":=".ERROR:HDLCompiler:806 - "C:/Users/Kk/CDwVHDL/tofloat/to_float.vhd" Line 19:Syntax error near ":=".

How can I fix it?


Emre Kirkaya • actually input1 is 3.1415 and input2 is 2.


Francis O'Malley • Hi Emre,

With the "to_float" floating-point conversion function, you need to size the result based onthe range of an argument, such as by passing the arrays represented by variables x andy, as follows:

x := to_float (3.1415, x);y := to_float (2.0, y);

or by passing the indices, as follows:

x := to_float (3.1415, 8, -32);y := to_float (2.0, 8, -32);

Hope this helps!

Emre Kirkaya • Hello. I can using the floating point librarry now. But i have a problemagain. the problem is:

library ieee_proposed;use ieee_proposed.fixed_float_types.all;use ieee_proposed.float_pkg.all;use ieee_proposed.math_utility_pkg.all;

entity deneme isPort ( a : in STD_LOGIC;b : in STD_LOGIC_VECTOR (2 downto 0);z : out STD_LOGIC_VECTOR (7 downto 0));end deneme;

architecture Behavioral of deneme is

beginprocess(a)variable bf,cf,zf : float32;variable d,e : std_logic_vector(31 downto 0);begind := "00000000000000000000000000000" & b;

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2 of 5 12/12/2012 7:21 PM

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e := to_slv(zf);z <= e(7 downto 0);end process;end Behavioral;

I wrote this code for getting 3 bit std_logic_vector. And Iwant to convert floating point.and make "b*2.2" operation. But the result rounding. For example 2 * 2.2 should be 4.4but result is 4.Another problem is:library IEEE;use IEEE.STD_LOGIC_1164.ALL;

library ieee_proposed;use ieee_proposed.fixed_float_types.all;use ieee_proposed.float_pkg.all;use ieee_proposed.math_utility_pkg.all;

entity deneme isPort ( a : in std_logic_vector(31 downto 0);z1 : out float32);end deneme;

architecture Behavioral of deneme issignal z1f,z2f : float32;begin

z1f <= to_float(a,z1f);

z1 <= z1f;

end Behavioral;

I think this code should be make converting float32 from std_logic_vector. But it doesnt. Iam givinga = 00000000000000000000000000000010 (=2 in std _logic format)I think it should be "01000000000000000000000000000000" (=2 in float32) but result is;z1 = 00000000000000000000000000000010 (=2 in std _logic format)Where is the problem.Actually I wantto make converting std_logic_vector(31 downto 0) to float32, withoutrounding. How can I do this. Thanks.

4 days ago • Like

Francis O'Malley • Hi Emre:

I think the problem you're observing with "4.4" seemingly being rounded down to "4" isbecause of the following two lines: they really don't do what I think you intend them to do!

e := to_slv(zf);z <= e(7 downto 0);

Don't forget that float32 consists of a sign bit (+ or–), a normalized exponent, and afraction. And so when you assign to "z" the lowest 8 bits of "e" (the second line), you'veeffectively thrown away the sign bit, the 8 exponent bits, and the 15 most-significant bitsof the 23 fraction bits!

I suggest you rethink how you're going to use "e" (or "zf"), the result of the multiplication.Only you know about the requirements of the problem you're trying to solve, and theprecision you want to retain in the computation.

Also, in your first piece of code "b" should be in the process's sensitivity list: it shouldread "process(a,b)".

The problems with your second piece of code also stem from not correctly interpretingthe representation of floating point numbers. The floating point format is explained inDavid Bishop's "Floating point Package User’s Guide" at http://www.eda.org/fphdl/Float_ug.pdf

I have a feeling that what you're trying to do might benefit from using fixed-pointarithmetic throughout, or at least a conversion to fixed point first of all. Then you caneasily peel-off the top 8 bits (say) from the result.

As David Bishop says on page 1 of that document, "There are many concepts in floatingpoint that make it different from our common signed and unsigned number notations."

Hope this helps!


3 of 5 12/12/2012 7:21 PM

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4 days ago • Like 1

BTW, there's a handy calculator online for IEEE-754 Floating Point: http://www.h-schmidt.net/FloatConverter/IEEE754.html

And Peter Ashenden's excellent book, "Digital Design: An Embedded Systems ApproachUsing VHDL" (2008) has useful information in Chapter 3 about floating pointrepresentation using VHDL.

3 days ago • Like 1

David Bishop • I'm the guy who wrote these pages. Just found out about this discussionform Mr. O'Malley. A few notes:

XST can synthesize these packages, if you stick to the restricted subset. One thing itcan't do is to convert real numbers into float (even for constants). So, you will have to do:constant PI : float32 := "01000000010010010000111111011010";

Next, remove the "math_utility_library" unless you are using Xilinx 9.0. Everything else isdebugged with the "fixed_float_lib" for the types.

in this line:z1f <= to_float(a,z1f);where "a" is a std_logic_vector and z1f is a float, this will be a type conversion. This willnot do the signed conversion you want it to do. Do it this way:b : signed (4 downto 0);b <= "00010";z1f <= to_float(b, z1f'high, -z1f'low);(need to do the conversion this way because of Xilinx).

3 days ago • Like

Emre Kirkaya • I wrote a program as I understand from your comments.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;USE ieee.std_logic_arith.all;

library ieee_proposed;use ieee_proposed.fixed_float_types.all;use ieee_proposed.float_pkg.all;

entity deneme isPort ( b : in signed(3 downto 0);z2 : out float32);end deneme;

architecture Behavioral of deneme issignal z1f : float32;constant PI : float32 := "01000000010010010000111111011010";beginz1f <= to_float(b, z1f'high, -z1f'low);z2 <= PI * z1f;end Behavioral;

And XST gave me this error:

ERROR:HDLParsers:808 - "C:/Users/Kk/CDwVHDL/fppppppp/deneme.vhd" Line 37.to_float can not have such operands in this context.

I have to get the b data from outside(like switches).

3 days ago • Like

David Bishop • First, some basic problems with this code.* Remove "std_logic_arith" and replace with "numeric_std". Std_logic_arith is not astandardized package. It should never be used.

* be sure that you follow the directions for Xilinx at:

http://www.vhdl.org/fphdl/xilinx_11.htmlSounds like you never included the library into XST.The newest version of Xilinx uses a different interface, but there must still be a way toinclude the library.


4 of 5 12/12/2012 7:21 PM

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5 of 5 12/12/2012 7:21 PM

floating point arithmetic with vhdl

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