Flexible interface based on the peripheral interface structure

Instead of interfacing a microcomputer at the processor bus level, a PIA port can be used as the basis of a flexible interface structure. Malcolm Taylor shows how

A technique whereby a single port of a peripheral interface adaptor (PIA) is used as the basis of a flexible interface structure is described. In this way, all peripheral interfacing may be accomplished through the single PIA porL The technique finds application in the connection of interface units to desk-top microcomputers where it may not be appropriate to interface at the processor bus level Interface modules designed in this way will be compatible with any microcomputer offering a single PIA port.

microsystems interfacing peripheral interface adaptor

Development of interface modules can be accomplished at either the microcomputer bus level 1 or at the equip- ment level, utilizing standards such as the Sl00 bus and IEEE 488 respectively. The peripheral interface adaptor (PIA) or programmable peripheral interface (PPI) may also be applied as the standard interface at the equipment level. PIAs and PPIs offer two or three 8-bit bidirectional data ports and associated control signals depending on

2 3 the particular manufacturer, eg MOS 6520 or Inte18255 . For the MOS 6520 PIA, two 8-bit ports, A and B, are available. Port A has bidirectional data lines described as PA0-7 and two control lines CA1 and CA2. Port B is described in a similar way.

The basic application of PIA ports is for the connection of byte-oriented action/status devices, such as printers. More flexible structures, facilitating the connection of many interface modules to a single PIA port, can be developed with the addition of a small amount of external logic.

BCD INTERFACE UNIT

To consider the flexibility of applying a single PIA port to interface design, a binary coded decimal (BCD) interface will be considered as an example.

Simple output unit

Consider the requirement to connect 16 BCD output registers via a single PIA port. Figure 1 illustrates how this may be accomplished. The 8-bit data port is partitioned

Department of Computer Science, University of Liverpool, PO Box 147, Liverpool, L69 3BX, UK

into two output blocks, PA0-3 and PA4-7, to provide data (D0-3) and address (A0-3) highways respectively. Data is loaded into a particular 4-bit register by routing the strobe pulse generated on the CA2 control line through a 1 -of-16 line decoder to the clock terminal (CLK) of the addressed register. The reset (RES) signal clears the register array on system power up.

Simple input unit

Figure 2 illustrates the method required to connect 16 BCD inputs. In this case the 8-bit data port is partitioned into an input section, PA0-3, and an output section, PA4-7, to provide the data and address highways respectively. Four 16-line input multiplexers are required to select a particular BCD character on the input data highway. This is effected when an enabling pulse is generated on the CA2 control line.

General input/output unit

In a realistic system it may be necessary to have a mix of several input and output modules. A simple solution

PIA rt Buffer [

~ D 0 - 3

PA4~ ~ AO~

CAt

CA2

RES

Register 0 (eg 74175)

i ii

i [ Register 15

] L _ ~]_~Bc, . . . . . / L ~ d a t

:~t T~EB 00 °°,

Figure I. 16 channel BCD output unit

0141-9331/86/04222-04 $03.00 © 1986 Butterworth & Co. (Publishers) Ltd

222 microprocessors and microsystems

PIA port

AO*3

r (e9 74126)

I 50 I15

IlS

_ _ _ _ ~ 410

Figure 2. 16 channel BCD input unit

Bus transceiver PIA port (eg 74243)

i ~ ~-~ Bi4irectional / z data highway j - -

, Direction A0-3~/Address in module /

q I 4-bit register (eg 741"75) ~ Composite ]1 CAt Buffer / [----~.[ '-- '~---~. /aed .... ' 1 " '°q 74 26' Mo,o'e add . . . . J J CA2 ~ CEock

pulse ator _ ~ . ~ ~_. .~ R/W = (Read/writecontrol)

_ r ~ (Synchronize transaction =.on bi-directional data

highway)

Figure 3. System block diagram of general unit

would be to connect each individual unit to its own PIA port. A more flexible solution is illustrated in Figure 3 and connects up to eight input and eight output modules to a single PIA port.

The 8-bit data port is again partitioned into two equal sections: PA0-3 acts as a bidirectional highway (D0-3), and PA4-7 acts as a multiplexed address highway (A0-3). A 4-bit register is attached to the address highway; three bits provide the module address (A4-6) and the fourth bit acts as a read/write (R/W) control line to define the direction of the transaction on the data highway (logic 0 specifying output from the PIA port) and switch the bus transceiver accordingly. A composite 7-bit address is then defined by A0-3 and A4-6.

Pulses generated on the CA2 control line drive a clock pulse generator which produces the register strobe pulse and the data highway transaction synchronizing pulse O. Figure 4a defines the state diagram of this logic. In state SO, CA2 is routed to C; in state $1, CA2 is routed to ~. The corresponding logic diagram is shown in Figure 4b.

The system timing diagrams for this arrangement are illustrated in Figure 5. The sequence of operations is first to load the module address and state of the R/W line into the 4-bit register with CA2 pulse 0, and then effect the data highway transaction with CA2 pulse 1. The relative operations and their timing are deft ned by assembler code running on the microcomputer to which the PIA port is attached.

The simple input and output modules described previously require some minor modifications to be compatible with this more flexible bus arrangement. In the case of the output module (Figure 1) the 1-of-16 line decoder would be enabled by Aw.-1~Z--w, where Aw is the module or base address derived from A4-6. In a similar way, the input unit (Figure 2) would require the 16-line input multiplexers to be enabled by Aw.R/W. 0. The outputs of the multiplexers would also require isolating

a

SO S1

2 C=0 = + R E S q~ = CA2

Load module Effect bidirectional data address register highway transaction

CA2

RES

b Figure 4. for the diagram

1!teL ~-c

a State diagram of clock pulse generation logic general unit, b clock pulse generation logic

IM I - q m c - - J - - - [

0 ] - - - [ _ _ Input data ~ vaJid

PA0.3

PA4 7 ~ AddrEss in module

A46 ~ M°du~e address

R/W .j/ Read

r a M _ _

m F q _ _ ~ C Outputdata mu~ be

valid

Figure 5. System timing diagrams for read and write operations in the general unit

vol 10 n o 4 m a y 1986 223

Low byte register (eg 74273)

PIA port Bus transceiver ^...~£J I

~ ' ] / (eg 74245l [ ~PAO-? ~_~ 4igh byte register l

II ,i CA1 ¢ ~

U CA2 =,

Ct

RES

Address highway \ I I

\ Bidirectional

DO-7 / /data highway

IRQ

~ Q = R/W

Fliptlop

RES

Figure 6. System block diagram of flexible interface structure

by tristate drivers since the data highway is bidirectional, and they would also be enabled by Aw.R/W. O.

FLEXIBLE INTERFACE STRUCTURE

The basis of the structure is a 16-bit address highway, an 8-bit bidirectional data highway and two control signals: R/W and e. Figure 6 illustrates the system block diagram that achieves this. The 8-bit data port provides the basis of the bidirectional data highway (D0-7). Two 8-bit registers are also attached to this highway to latch the multiplexed low and high order address bytes. The outputs of the two registers then form the address highway (A0-A15). A R/W flip-flop, also loaded from the data highway, defines the direction of the transaction on the data highway when e is high.

A clock pulse generator provides the necessary clock pulses to load the two registers (CO and Cl), load the R/W flip-flop (C2) and effect the transaction on the data highway (~). Figure 7 gives the state diagram of this logic. A 2-bit counter and a 2-to-4 line decoder form the basis of the generator.

The bus transceiver is normally set in its output mode (data from the PIA port to the data highway) and is only able to respond to the state of the R/W line (logic 0 defining a write transaction) when 0 is active.

Figure 8 illustrates the system timing diagrams for the read and write transactions. The sequence of operations is

• load the low byte of the address with CA2 pulse 0 • load the high byte of the address with CA2 pulse 1 • load the R/W flip-flop with CA2 pulse 2 • effect the data highway read or write transaction with

CA2 pulse 3

The structure of the software driving routine on the microcomputer to effect a write transaction is as follows (port A is already set to the output mode)

• load low byte of address:

• load high byte of address:

• load R/W flip-flop:

• write data byte to addressed location:

write low address byte ~:c p)rt A ;~i: CA2 high ~e~ CA2 low

write high address byte to port A se, ~ CA2 high ~et CA2 low

write logic 0 to PA0 set CA2 high set CA2 low

~rite data byte to port A

~et CA2 high ~et CA2 low

The read transaction is similar in that the first two operations are concerned with the loading of the 2 byte address. The final two operations are

• load R/W flip-flop: write logic 1 to PAO ~.et CA2 high set (A2 low

• read data byte from set port A to input mode addressed location:

set CA2 high read data byte from portA set CA2 low set port A to output mode

In the case of the MOS 6520 PIA, the CA1 control line may be configured into an input mode such that on placingthe line low a corresponding pin on the processor bus side of the PIA is also placed low to assert an interrupt request to the processor. This interrupt request is also maskable, under software control, within the PIA. It is therefore possible to provide a maskable interrupt request facility

Load low byte of address SO

CO = CA2 C1 =0 C2 = 0

=0

t

I J C1 = 0

C2 = 0 [-

1 = CA2

$3

C A 2

load high byte of address S~

f. C0 --~ 0 C! = CA2 C2 ~ 0

[ ,;, 0 L

I _j~CA2

CO = 0 C1 ~0 c2 = CA2

~ 0

$2 Ef fec t b i - d i r ec t i ona l Load r e a d / w r i t e f l i p f l o p da ta h i g h w a y t ransac t i on

Figure 7. State diagram of clock pulse generation logic for the flexible interface

224 microprocessors and microsystems

CA2

CO

C1

C2

¢

PA0-7_X

A0-7

A8-15

R/W

Figure 8.

71 l-q I [

I I

1[ ] [

Low byte X High byte x R/Wstate ")C ~ Input datavalk

~ Low byte of address

High byte of address

J Read

System timing diagram for read and write operations in the flexible interface

Fq

I1 OUtput data

ust be valid

Write

(IRQ) by way of the CA1 control line. If more than one interrupt source is to be connected then an interrupt sorting module 1 will be required to generate the single interrupt IRQ. In this case it is necessary first to identiff/the source of the interrupting device by reading the status (address) contained in the sorting module and then use this information to activate the corresponding service routine.

The interface structure derived is similar to that available at the processor bus level, although the speed of transactions is reduced due to the multiplexed nature of the bidirectional data highway. Interface modules may be readily designed to conform to this interface specification.

CONCLUSION

A technique has been described whereby a single PIA port is used as the basis of a flexible interface structure. The technique may be applied in the connection of interface modules to desk-top microcomputers where a PIA port is the only available interfacing facility because it is not appropriate to interface at the processor bus level. Interface modules designed in this way are compatible with any microcomputer offering a single PIA port.

REFERENCES

1 Zissos, D System design with microprocessors Academic Press, New York, USA (1978)

2 MCS 6500 microcomputer family hardware manual MOS Technology (1976)

3 Intel component data catalog Intel Corp (1984)

Malcolm Taylor is a lecturer in the Department of Computer Science at Liverpool University, UK. He was previously employed as a hardware specialist (1976- 1978) and then as a lecturer (1978-1982), both in the Computer Laboratory at Liverpool University. His research interests include microprocessor applications,

medical computing and hardware design techniques. He holds a BSc in electrical engineering from Salford University, UK, as well as an MSc and PhD in digital electronics from Manchester University, UK.

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