first results from the drs4 waveform digitizing chip

First results from the DRS4 waveform digitizing chip

Stefan RittPaul Scherrer Institute, Switzerland

3 ps Timing with the DRS series ASICs

Stefan RittPaul Scherrer Institute, Switzerland

Oct. 15th, 2008 Picosecond Workshop, Lyon 3

Requirements

High Sampling Speed

High Sampling Speed

SNR > 12 bitSNR > 12 bit

Deep SamplingDepth

Deep SamplingDepth Many ChannelsMany Channels

ps Timing Jitterps Timing Jitter

High TemperatureStability

High TemperatureStability


A bit of history…

DRS2DRS2

DRS3DRS3

DRS1DRS1MEG Experiment searchingfor e down to 10-13

MEG Experiment searchingfor e down to 10-13

DRS4DRS42008

2006

2004

2001

3000 Channels withGHz sampling

3000 Channels withGHz sampling

Design Principles

How to fulfill all these needs?


The Domino Principle

Shift RegisterClock

IN

Out

“Time stretcher” GHz MHz“Time stretcher” GHz MHz

Waveform stored

Inverter “Domino” ring chain0.2-2 ns

FADC 33 MHz

Keep Domino wave running in a circular fashion and stop by trigger Domino Ring Sampler (DRS)

Keep Domino wave running in a circular fashion and stop by trigger Domino Ring Sampler (DRS)


Origin of Jitter

VDD/GND noise causes timing jitter!VDD/GND noise causes timing jitter!

VDDR

VDD/2

tt’

VDDVDD’

Golden Rules:

• Make R small Power Planes• Design for steep edges

Golden Rules:

• Make R small Power Planes• Design for steep edges

R GND


Example: Bus drivers

R

C

• Sheet resistance M5: 0.036 /sq., 4000m x 0.4 m 360 • Area capacitance M5-M4: 0.037 fF/m2+0.036fF/m 0.35 pF


Bus driver simulation


Simulation Result 1

100 mV


Modified Bus Driver


Simulaiton Result 2

100 mV


More elaborate evaluation

A. Strak, H. Tenhunen, http://www.strak.se/Adam_Strak_DCAS_2006.pdf

Timing-Jitter induced by power supply noiseTiming-Jitter induced by power supply noise

http://www.strak.se/Adam_Strak_DCAS_2006.pdf


Rules for high precision timing

• Keep local power supply stable

• Low resistive power rails (planes)

• Separate power supply for inverter chain + PLL from rest

• Add on-chip decoupling capacitors

• Try to keep number of simultaneously switching gates minimal

• Design for fast transitions

• Identify high load lines, driver them with enough power

• Follow 1x 3x 10x 30x rule

• Use differential signalling for critical lines

• Inverter chain

• Reference clock input

• Do not use minimal transistors for critical paths

X DRS4


“Residual charge” problem

R

“Ghost pulse”2% @ 2 GHz

“Ghost pulse”2% @ 2 GHz

After sampling a pulse, some residual charge remains in the capacitors on the next turn and can mimic wrong pulses

After sampling a pulse, some residual charge remains in the capacitors on the next turn and can mimic wrong pulsesSolution: Clear before write

write clear


ROI readout mode

readout shift register

Triggerstop

normal trigger stop after latency

Delay

delayed trigger stop

Patent pending!

33 MHz

e.g. 100 samples @ 33 MHz 3 us dead time

(3.8 ns / sample @ 8 channels)

e.g. 100 samples @ 33 MHz 3 us dead time

(3.8 ns / sample @ 8 channels)


Simultaneous Write/Read

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

Channel 6

Channel 7

0

FPGA

0

0

0

0

0

0

0

1 Channel 0

Channel 11

Channel 0 readout

8-foldanalog multi-event

buffer

Channel 21

Channel 10

Expected crosstalk ~few mVExpected crosstalk ~few mV


Interleaved samplingdela

ys

(167p

s/8 =

21ps)

G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007)G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007)

6 GSPS * 8 = 48 GSPS

Possible with DRS4 if delay is implemented on PCBPossible with DRS4 if delay is implemented on PCB


New generation of FADCs

• 8 simultaneous flash ADCs on one chip

• Requiredifferentialinput

• DRS4 has beenredesigned withdifferentialoutput


Trigger an DAQ on same board

• Using a multiplexer in DRS4, input signals can simultaneously digitized at 65 MHz and sampled in the DRS

• FPGA can make local trigger(or global one) and stop DRSupon a trigger

• DRS readout (5 GHz samples)though same 8-channel FADCs

an

alo

g fro

nt e

nd

DRSFADC12 bit

65 MHzM

UX FPGA

trigger

LVDS

SRAM

DRS4

glo

bal tr

igger

bu

s

“Free” local trigger capability without additional hardware

“Free” local trigger capability without additional hardware


Decisions

• Usage of external ADC

• Analog Devices has better engineers

• Get information faster off-chip (1 sample in 30 ns, 12 bits would need 400 MHz clock)

• Possibility for continuous sampling ( triggering)

• Use passive input

• Hard to design 1 GHz buffer in 0.25 m technology, needed for 1V linear range

• Lower power consumption

• Problem: Bond wire Cparasitic limits bandwidth, high input current 0.8 mA

• Use Gate-All-Around (GAA) transistors

• Radiation hardness

• Good W/L vs. chip area bigger gates reduced mismatch

• On-chip PLL for sampling frequency stabilization

• Flexible channel configuration

DRS4

Have we achieved the requirements?


DRS4

• Fabricated in 0.25 m 1P5M MMC process(UMC), 5 x 5 mm2, radiation hard

• 8+1 ch. each 1024 bins,4 ch. 2048, …, 1 ch. 8192

• Differential inputs/outputs

• Sampling speed 500 MHz … 6 GHz

• On-chip PLL stabilization

• Readout speed 30 MHz, multiplexedor in parallel

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

STOP SHIFT REGISTER

READ SHIFT REGISTER

WSROUT

CONFIG REGISTER

RSRLOAD

DENABLE

WSRIN

DWRITE

DSPEED PLLOUT

DOMINO WAVE CIRCUIT

PLL

AGND

DGND

AVDD

DVDD

DTAPREFCLKPLLLCK A0 A1 A2 A3

EN

AB

LE

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8/MUXOUT

BIASO-OFS

ROFSSROUT

RESETSRCLK

SRIN

F U N C T IO N A L B L O C K D IA G R A M

MUX

WR

ITE

SH

IFT

RE

GIS

TE

R

WR

ITE

CO

NF

IG R

EG

IST

ER

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

CHANNEL 8

MUX

LVDS


DRS4 packaging

6 4 -L ea d L Q F P

6 4 -L ea d Q F N

17

64

18

63

19

62

20

61

21

60

22

59

23

58

24

57

25

56

26

55

27

54

28

53

29

52

30

51

31

50

32

49

3316

3415

3514

3613

3712

3811

3910

409

418

427

436

445

454

463

472

481

DRS3TOP VIEW

(N ot to Scale)

PIN 1

DR S3TO P VIEW

(Not to Scale)

PIN 1

P IN C O N F IG U R AT IO N

A 0

A 0

IN8+

IN 8+

A 1

A 1

IN8-

IN 8-A 2

A 2

IN7+

IN 7+A 3A 3

IN7-IN 7-OU T11 OU T 11IN6+IN 6+

OU T10 OU T 1 0IN6- IN 6-

OU T9OU T 9

IN5+IN 5+

OU T8OU T 8

IN5-IN 5-

OU T7

OU T 7

IN4+

IN 4+

OU T6

OU T 6

IN4-

IN 4-

OU T5

OU T 5

IN3+

IN 3+

OU T4

OU T 4

IN3-

IN 3-

OU T3

OU T 3

IN2+

IN 2+

OU T2

OU T 2

IN2-

IN 2-

OU T1

OU T 1

IN1+

IN 1+

IN1-

IN 1-

DG

ND

DV

DD

DTA

P

DS

PE

ED

DW

RIT

E

DE

NA

BL

E

DM

OD

E

RO

FS

IN11

+

IN11

-

IN1

0+

IN1

0-

IN9

+

IN9

-

DV

DD

DG

ND

DG

ND

DV

DD

DTA

PD

SP

EE

DD

WR

ITE

DE

NA

BL

ED

MO

DE

RO

FS

IN11

+IN

11-

IN10

+IN

10-

IN9+

IN9-

DV

DD

DG

ND

M UXOUT/OU T0

MU X O UT/OU T 0

AG

ND

AG

ND

AV

DD

AV

DD

BIA

S

BIA

S

SR

IN

SR

IN

RS

RL

OA

D

RS

RL

OA

D

RS

RC

LK

RS

RC

LK

RS

RO

UT

RS

RO

UT

RS

RR

ST

RS

RR

ST

SS

RL

OA

D

SS

RLO

AD

SS

RO

UT

SS

RO

UT

WS

RC

LK

WS

RC

LK

WS

RO

UT

WS

RO

UT

IN0-

IN0-

IN0+

IN0+

AV

DD

AV

DD

AG

ND

AG

ND

DRS3 DRS4

9 mm

18 mm

4.2 mm

DRS4flip-chip PIN 1

O U T 0 +5 7A G N DO U T 0 -5 6A G N D 2

1

O U T 1 -5 5IN 0+ 3O U T 1 +D G N D

D G N D

D G N D

5 4IN 0- 4

O U T 2 +5 3IN 1+ 5

O U T 2 -5 2IN 1- 6

O U T 3 -5 1IN 2+ 7

IN 2- 8

O U T 4 +4 9IN 3+ 9

O U T 4 -4 8IN 3- 1 0

O U T 5 -4 7IN 4+ 11

O U T 5 +4 6IN 4- 1 2

O U T 6 +

4 5IN 5+ 1 3

O U T 6 -

4 4IN 5- 1 4

O U T 7 -

4 3IN 6+ 1 5IN 6-IN 7+IN 7-D G N D

1 61 71 81 9

AG

ND

AG

ND

AV

DD

A2

A3

BIA

S

DT

AP

RE

FC

LK

+R

EF

CL

K-

PL

LLC

K

PL

LOU

TD

SP

EE

D

DW

RIT

ED

EN

AB

LE

WS

RIN

AV

DD

AV

DD

AG

ND

AG

ND

76

75

63

64

65

66

67

68

69

70

71

72

73

74

62

61

60

59

58

O U T 7 +

4 24 14 03 9

OU

T8

-

35 36 37 38O

UT

8+

34

O-O

FS

33D

VD

DD

VD

DR

ES

ET

32

A1

31A

030

RO

FS

29R

SR

LO

AD

28S

RC

LK27

SR

IN26

SR

OU

T25

DV

DD

DV

DD

23D

GN

D2

2IN

8-

21IN

8+

20


On-chip PLL

ReferenceClock

fclk = fsamp / 2048

Vspeed

• PLL jitter « 100 ps (Spartan-3 jitter 150 ps)• “Dead Band” free• Does not lock on higher harmonics

• PLL jitter « 100 ps (Spartan-3 jitter 150 ps)• “Dead Band” free• Does not lock on higher harmonics

loop

filt

er

DRS4

Simulation

Measurement

Phase detector

up

down


Linear Range (DRS3)

Excellent linearity from 0.1V … 1.1V @ 33 MHz readout

NO

NL

INE

AR

ITY

[m

V]

ANALOG OUTPUT [V]

0 0.2 0.4 0.6 0.8 1 1.2-2

-1

0

1

2

ROFS = 0.95 VBIAS = 0.70 V

NO

NL

INE

AR

ITY

[m

V]

ANALOG OUTPUT [V]

0 0.2 0.4 0.6 0.8 1 1.2-2

-1

0

1

2

ROFS = 0.95 VBIAS = 0.70 V

0.5 mV max.


Bandwidth

Bandwidth is determined by bond wire and internalbus resistance/capacitance:

850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip)

finalbus width

Simulation

850 MHz (-3dB)

QFP package

Measurement


Signal-to-noise ratio (DRS3!)

“Fixed pattern” offset error of 5 mV RMScan be reduced to 0.35 mV by offsetcorrection in FPGA

SNR:

1 V linear range / 0.35 mV = 69 dB (11.5 bits)

“Fixed pattern” offset error of 5 mV RMScan be reduced to 0.35 mV by offsetcorrection in FPGA

SNR:

1 V linear range / 0.35 mV = 69 dB (11.5 bits)

AN

AL

OG

OU

TP

UT

[V

]

BIN NUMBER0 200 400 600 800 1000

0.48

0.49

0.5

0.51

0.52

Crosstalk from trigger signal

OC

CU

RE

NC

E

OUTPUT VOLTAGE [V]0.48 0.49 0.5 0.51 0.520

20

40

60

80

100

120

140

160

180

200

OC

CU

RE

NC

E

OUTPUT VOLTAGE [V]0.48 0.49 0.5 0.51 0.520

20

40

60

80

100

120

140

160

180

200

OffsetCorrection


Timing jitter

t1 t2 t3 t4 t5

• Inverter chain has transistor variations ti between samples differ “Fixed pattern jitter”

• “Differential temporal nonlinearity” TDi= ti – tnominal

• “Integral temporal nonlinearity”TIi = ti – itnominal

• “Random jitter” = variation of ti between measurements

• Inverter chain has transistor variations ti between samples differ “Fixed pattern jitter”

• “Differential temporal nonlinearity” TDi= ti – tnominal

• “Integral temporal nonlinearity”TIi = ti – itnominal

• “Random jitter” = variation of ti between measurements

TD1 TI5


Fixed jitter calibration

• Fixed jitter is constant over time, can be measured and corrected for

• Several methods are commonly used

• Most use sine wave with random phase and correct for TDi on a statistical basis

• Fixed jitter is constant over time, can be measured and corrected for

• Several methods are commonly used

• Most use sine wave with random phase and correct for TDi on a statistical basis


Sine Curve Fit Method

S. Lehner, B. Keil, PSI

i

j

500

1

1024

1

22 min)))2

sin(((j i

jijj

jji of

iay

yji : i-th sample of measurement jaj fj j oj : sine wave parametersi : phase error fixed jitter

“Iterative global fit”:

•Determine rough sine wave parameters for each measurement by fit

•Determine i using all measurements where sample “i” is near zero crossing

•Make several iterations

“Iterative global fit”:

•Determine rough sine wave parameters for each measurement by fit

•Determine i using all measurements where sample “i” is near zero crossing

•Make several iterations


Fixed Pattern Jitter Results

• TDi typically ~50 ps RMS @ 5 GHz

• TIi goes up to ~600 ps

• Inter-channel variation on same chip is very small since all channels are driven by the same domino wave

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

STOP SHIFT REGISTER

READ SHIFT REGISTER

WSROUT

CONFIG REGISTER

RSRLOAD

DENABLE

WSRIN

DWRITE

DSPEED PLLOUT

DOMINO WAVE CIRCUIT

PLL

AGND

DGND

AVDD

DVDD

DTAPREFCLKPLLLCK A0 A1 A2 A3

EN

AB

LE

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8/MUXOUT

BIASO-OFS

ROFSSROUT

RESETSRCLK

SRIN

F U N C T IO N A L B L O C K D IA G R A M

MUX

WR

ITE

SH

IFT

RE

GIS

TE

R

WR

ITE

CO

NF

IG R

EG

IST

ER

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

CHANNEL 8

MUX

LVDS


Random Jitter Results

• Sine curve frequency fitted for each measurement (PLL jitter compensation)

• Encouraging result for DRS3:2.7 ps RMS (best channel)3.9 ps RMS (worst channel)phase error in fitting sine wave

• Differential measurement t1 – t2 adds a 2, needs to be verified by measurement

• Measurement of n points on a rising edge of a signal improves by n

• Sine curve frequency fitted for each measurement (PLL jitter compensation)

• Encouraging result for DRS3:2.7 ps RMS (best channel)3.9 ps RMS (worst channel)phase error in fitting sine wave

• Differential measurement t1 – t2 adds a 2, needs to be verified by measurement

• Measurement of n points on a rising edge of a signal improves by n

Measurements for DRS4 currently going on, expected to be slightly better

Measurements for DRS4 currently going on, expected to be slightly better


Inter-Chip Synchronization

Trigger

ReferenceClock

PLL Jitter?

Chip 1

Chip 2

t1

t2


• Synchronize chips with a global low jitter reference clock

• Determine timing of a hit in respect to global clock (beginning of sampling window)

• PLL timing jitter < desired accuracy you’re done

• PLL timing jitter > desired accuracy use clock channel with sine

Rules for Synchronization

8 inputs

Shift register

Domino + PLLReference Clock

Global Sine Wave

~100 ps jitter few ps accuracy

~100 ps jitter few ps accuracy


Chip Comparison

G. Varner Delagnes/Breton S.RittHawaii Saclay/Orsay PSIBlab1 Lab 2 Lab 3 Planned Blab2Hamac Matacq Sam Planned DRS3 DRS4

Sampling frequency 100 MHz-6 GHz 20 MHz-3.7 GHz1-10 GHz 40 MHz 0.7-2.5 GHz 0.7-2.5 GHz 10 GHz 10 MHz-5 GHz6 GHzAnalog bandwidth (3db) 300 MHz 900 MHz 850 MHz 50 MHz 200-300 MHz 300 MHz 650 MHz 450 MHz 950 MHzNumber of Channels 1 8 9 16 12 1 2 12/6/2/1 8/4/2/1Triggered mode Yes Common StopChannel trigger on analog sumsCommon StopCommon StopCommon Stop Common stopResolution 10 bit 9-10 bit 10 bit 13.3 bit 13.4 bit 11.6 bit 11.6 bitSamples 128 rows of 512 256 256 4/8 rows of 512 144 2520 256 2048 1024-12288 1024-8192Clock 33 MHz 33 MHz 40 MHz 100 MHz 66 MHz 20 MHz fsamp/2048Max latency 560 us 2.2ms 50us 30 usInput Buffers Yes TIA (5kOhm gain) Yes Yes Yes No No NoDifferential inputs No No No Pseudo-diff Yes Yes Yes Yes YesInput impedance 50 Ohms 50 Ohms 50 Ohms Ext 30-70Ohms adjustable10 MOhm/3pF> 10 MOhm > 10 MOhm 1 kOhmReadout clock 500 MHz 1 GHz Wilkinson5 MHz 5 MHz 16 MHz 33 MHzReadout time 10ms (12-b) 150s 512s 3 s 650 s < 2s 30ns * n_samplesLocked delays Ext DAC Ext DAC Ext DAC Ext DLL External ctrl Int DLL Int DLL Ext PLL Int PLLOn-chip ADC Ext 1 GHz FPGA TDCYes Yes 1 GHz WilkinsonNo No No No NoR/W simultaneous Yes Yes Yes No No No YesPower/ch 15mW/sample 1.6W/read 50mW 20mW/sample 200mW/read36 mW 250-500 mW 150 mW 1-13mW 14-45 mWDynamic range 1mV/1.6V 1mV/1V 0.26mV/2.75V175 uV-2V 0.65mV-2V 0.35mV/1.1VXtalk Inter-rows 0.1%< 10% Signal freq dept, average <<10%< 0.1% 0.30% <0.5%Sampling jitter TBD 45ps 15ps 40ps 200ps (Ext PLL)6ps+PLLPower supplies 2.5V 2.5V 2.5V 2.5V -1.7/3.3V -3.3/+3.3V 0-3.3V 2.5V 2.5VProcess TSMC 0.25 TSMC 0.25 TSMC 0.25 TSMC 0.25 HP/DMILL 0.8AMS 0.8 AMS 0.35 AMS 0.18 UMC 0.25 UMC 0.25Chip area 5.25 mm2 10 mm2 2.5 mm2 12 mm2 19.8 mm2 30 mm2 10 mm2 25mm2 18mm2Reset No No No No No YesTemp coeff 0.2%/?C 0.2%/?C 0.005%/?C 0.005%/?C 0.005%/?CCost/channel 500$/40 10$/2k 500$/40 10$/2k3.14$/50k 15.7$ 15.7$/12k 10$/1 2$/10k


Experiments using DRS chip

MAGIC-II 400 channels DRS2MAGIC-II 400 channels DRS2MEG 3000 channels DRS2MEG 3000 channels DRS2

BPM for XFEL@PSI1000 channels DRS4 (planned)

MACE (India) 400 channels DRS4 (planned)MACE (India) 400 channels DRS4 (planned)


Availability

• DRS4 will become available in larger quantities in November 2008

• Chip can be obtained from PSI on a “non-profit” basis

• Delivery “as-is”

• Reference design (schematics) from PSI

• Costs ~ 10-15$/channel

• Costs decrease if we find sell more…

• VME boards from industry in 2009

32-channel 65 MHz/12bit digitizer

“boosted” by DRS4 chip to 5 GHz

32-channel 65 MHz/12bit digitizer

“boosted” by DRS4 chip to 5 GHz

Input

USB 2.0

ext. Trigger

DRS4


Datasheet


Conclusions

• Fast waveform digitizing is in my opinion the best choiceto achieve ps timing

• Phase noise of a single cell using a 500 MHz sine wave has been measured to be 3-4 ps in the DRS chip

• More characterization is needed from community (Single pulse response, 48 GHz mode, …)DRS4 has prospects to come

quite a step closer to our goal

DRS4 has prospects to come quite a step

closer to our goal

http://midas.psi.ch/drs


Simple inverter chain

1 0 0 0 0 0

0 0 0 0 00

1 0

0 0 0 0 00

1

0

10 0 0

1 1 1 1

1 1 1 1 1

1 1 1 1 1

1 1 1 1 1 1

11

1 0 0 0 0 0

0 0 0 0 00

0

0 0 0 0 00

0

0 0 0

1

1

1

0 0 00

0 0 0 0

0 0 0 0

00

0 0 0 0 00

00


Design of Inverter Chain

PMOS > NMOS

PMOS < NMOS


“Tail Biting”

enable

1 2 3 4

1

2

3

4

speed


Stopping

enable

1 2 3 4

1

2

3

4

speed

time

enable


Stop Schematics

D Q D Q D Q

WE

RES RES RES

1 2 3

1

2

3

WE


Complete Domino Cells

DQ

RES

DQ

RES

DQ

RES

Sampling Cell 1 Sampling Cell 2 Sampling Cell 3

VspeedEnable

Write

Start

Domino Cell 1 Domino Cell 2 Domino Cell 3


On-line waveform display

click

templatefit

pedestalhisto

848PMTs

“virtual oscilloscope”“virtual oscilloscope”


Lat

ch

Lat

ch

Lat

ch

Lat

ch

Constant Fraction Discr.

Lat

ch

12 bit

Clock

+

+

MULT

Lat

ch

0

&<0

Delayedsignal

Invertedsignal

Sum

first results from the drs4 waveform digitizing chip

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