FinFETs: From Circuit to Architecture

Niraj K. JhaDept. of Electrical Engineering

Princeton University

Joint work with: Anish Muttreja, Prateek Mishra, Chun-Yi Lee, Ajay Bhoj and Wei Zhang

Talk Outline

• Background

• Low Power FinFET Circuits– Unusual Logic Styles

– Unusual Dual-Vdd/Dual-Vth Circuits

• Architectural Impact

• Other Ongoing Work

• Conclusions

Why Double-gate Transistors ?

Non-Si nano devicesBulk CMOS

Feature size 32 nm 10 nm

DG-FETsGap

• DG-FETs can be used to fill this gap• DG-FETs are extensions of CMOS

– Manufacturing processes similar to CMOS

• Key limitations of CMOS scaling addressed through– Better control of channel from transistor gates– Reduced short-channel effects– Better Ion/Ioff– Improved sub-threshold slope– No discrete dopant fluctuations

What are FinFETs?

• Fin-type DG-FET– A FinFET is like a FET, but the channel has been “turned on its edge”

and made to stand up

Si Fin

Independent-gate FinFETs

• Both the gates of a FET can be independently controlled• Independent control

– Requires an extra process step– Leads to a number of interesting analog and digital circuit

structures

Back GateOxide insulation

FinFET Width Quantization

• Electrical width of a FinFET with n fins: W = 2*n*h

• Channel width in a FinFET is quantized

• Width quantization is a design challenge if fine control of transistor drive strength is needed

–E.g., in ensuring stability of memory cells

FinFET structure Ananthan, ISQED’05

Talk Outline

• Background

• Low Power FinFET Circuits– Unusual Logic Styles

– Unusual Dual-Vdd/Dual-Vth Circuits

• Architectural Impact

• Other Ongoing Work

• Conclusions

Motivation: Power Consumption

• Traditional view of CMOS power consumption– Active mode: Dynamic power (switching +

short circuit + glitching)– Standby mode: Leakage power

• Problem: rising active leakage– 40% of total active mode power consumption

(70nm bulk CMOS) †

†J. Kao, S. Narendra and A. Chandrakasan, “Subthreshold leakage modeling and reduction techniques,” in Proc. ICCAD, 2002.

Logic Styles: NAND Gates

SG-mode NAND IG-mode NAND

LP-mode NAND IG/LP-mode NAND

pull up bias voltage

pull down bias voltage

IG-mode pull up

LP-modepull down

Comparing Logic Styles

Design Mode Advantages Disadvantages

SG Fastest under all load conditions

High leakage† (1μA)

LP Very low leakage (85nA), low switched capacitance

Slowest, especially under load. Area overhead (routing)

IG Low area and switched capacitance

Unmatched pull-up and pull-down delays.

High leakage (772nA)

IG/LP Low leakage (337nA), area and switched capacitance

Almost as slow as LP mode

†Average leakage current for two-input NAND gate (Vdd = 1.0V)

FinFET Circuit Power Optimization• Construct FinFET-based

Synopsys technology libraries

• Extend linear programming based cell selection† for FinFETs

• Use optimized netlists to compare logic styles at a range of delay constraints

Benchmark

Minimum-delaysynthesis in

Design Compiler

SG-mode netlist

Power-optimized mixed-mode netlists

SG+IG/LP SG+IG

SG+LP Linear programmingbased cell selection

32 nm PTM FinFET models

Delay/power characterization in

SPICE

LPIG/LP

IG SG

Synopsys libraries

32 nm PTM inFET modelsFinFET models(UFDG, PTM)

Logic gatedesigns

Logic gatedesigns

†D. Chinnery and K. Keutzer, “Linear programming for sizing, Vdd and Vt assignment,” in Proc. ISLPED, 2005.

Power Consumption of Optimized Circuits

Leakage power savings

• 110% a.t. (68.5%)

• 120% a.t. (80.3%)

Total power savings

• 110% arrival time (a.t.) (34%)

• 120% a.t. ( 47.5%)

Estimated total power consumption for ISCAS’85 benchmarks

Vdd = 1.0V, α = 0.1, 32nm FinFETs

Available modes

Talk Outline

• Background

• Low Power FinFET Circuits– Unusual Logic Styles

– Unusual Dual-Vdd/Dual-Vth Circuits

• Architectural Impact

• Other Ongoing Work

• Conclusions

Dual-Vdd FinFET Circuits

• Conventional low- power principle:

– 1.0V Vdd for critical logic, 0.7V for off-critical paths

• Our proposal: overdriven gates– Overdriven FinFET gates

leak a lot less!

1.08V 1V

Leakage current

Reverse biasVgs=+0.08V

Overdriven inverter

Higher Vth

Vin

• Using only two Vdd’s saves leakage only in P-type FinFETs, but not in N-type FinFETs

• Solution– Use a negative ground voltage (VH

ss) to symmetrically save leakage in N-type FinFETs

– –

Vth Control with Multiple Vdd’s (TCMS)

VddH

VssH

Symmetricthreshold control

for P and N

VddL

VssL

VddH 1.08V

VddL 1.0V

VssH -0.08V

VssL 0.0V

TCMS buffer

Exploratory Buffer Design

• Size of high-Vdd inverters kept small to minimize leakage in them

• Wire capacitances not driven by high-Vdd inverters• Output inverter in each buffer overdriven and its size (and

switched capacitance) can be reduced

loptS1 S2

VHdd

VHss VL

ss

VLdd

S1 S2

VHdd

VHss VL

ss

VLdd

ii’

Power Savings

• Benchmarks are nets extracted from real layouts and scaled to 32nmhttp://dropzone.tamu.edu/~zhouli/GSRC/fast_buffer_insertion.html

Power component

Savings

Dynamic power

-29.8%

Leakage power

57.9%

Total power 50.4%

Fin-count Savings

• Transistor area is measured as the total number of fins required by all buffers

• TCMS can save 9% in transistor area

TCMS Extension

Delay-minimized netlistPower : 283.6uWArea: 538 fins

Power-optimized netlistPower : 149.9uWArea: 216 fins

b

b

d

d

c

a

e

X8

X8

X8

X8

X16

X16

X16

X16

X4 X4

X1

X2

X2

X2

Level: 1 2 3 4

b

b

d

d

c

a

e

X2

X4

X2

X2

X2

X8

X8

X8

X2 X1

X1

X1

X1

X1

nor10011

nor11011

nor01100

nand01001

nor00111

nor10011 nand00110

nor01100

inv101

inv101

inv101

inv101

inv101

inv101

Level : 1 2 3 4

Power Reduction (ISCAS’85 Benchmarks)

% reduction in power

0

10

20

30

40

50

60

70

80

90

110% 130% 150% 170% 190%

ATCs

% r

edu

ctio

n i

n p

ow

er

TCMS TCMS (Single-Vth

Dual-Vdd

% reduction in dynamic power 53.3 49.8 51.4

% reduction in leakage power 95.8 95.7 95.8

% reduction in

total power 67.6 65.3 66.3

% reduction in

Fin-count 65.2 59.5 61.6

Power-minimized vs Delay-minimized Netlists at 130% ATC

Talk Outline

• Background

• Low Power FinFET Circuits– Unusual Logic Styles

– Unusual Dual-Vdd/Dual-Vth Circuits

• Architectural Impact

• Other Ongoing Work

• Conclusions

Orion-FinFET

• Extends ORION for FinFET-based power simulation for interconnection networks

• FinFET power libraries for various temperatures and technologies nodes

• Power breakdown of interconnection networks for different FinFET modes

• Power comparison for different FinFET modes under different traffic patterns

Router Microarchitecture & Pipeline Stages

Crossbar

Switch allocation arbiters

From source

From north

From south

From east

From west

Input buffers

Req Grant

To sink

To north

To south

To east

To west

……

.

……

.

……

.

……

.

……

.

VC allocation arbiters

RC

RC

RC

RC

RC

Route calculation

VC allocation

Switch allocation

Switch traversal

Link traversal

Power Simulation Flow

FinFET model card

FinFET logic gate characteristics

Run UFDG SPICE simulation

FinFET power library

Capacitance & leakage extraction

Router power model

Logic-level router circuits

Fin count specification for logic gates

Router power profile

Router dynamic & leakage power calculation

Network configuration

Clock tree & link power calculation

Clock & link power profile

Router traffic profile

Number of tiles in the network

Network power

Clock/link power model

Power Breakdown for SG/LP Modes

• 4X4 mesh network: 5 ports/router, 48-flit buffer/port• Flit width = 128 bits• Clock frequency = 1GHz

0

0.005

0.01

0.015

0.02

0.025

0.03

SG LP 1.2/-0.2 LP1.4/-0.4

Wat

t

Buffer Crossbar Arbiter Clock Leakage

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

SG LP 1.2/-0.2 LP1.4/-0.4

Wat

t

Router Link Clk dist Driver leak

Router power breakdown Network power breakdown

Bulk CMOS vs. LP-mode FinFETs

• Bulk CMOS simulation: 32nm predictive technology model

• Leakage power of bulk CMOS network 2.68X as compared to an LP-mode FinFET network

0

0.5

1

1.5

2

2.5

3

3.5

4

Bulk CMOS LP mode (1.2/-0.2)

Wat

ts

Router Dynamic Link Clk dist Leakage

Router Leakage Power vs. Temp.

• Leakage power of SG-mode router grows much faster with temp. than for LP-mode

• Leakage power ratio at 105oC: 7:1

0

0.002

0.004

0.006

0.008

0.01

0.012

0.014

25 35 45 55 65 75 85 95 105Temperature

Leak

age

pow

er (

Wat

t)

SGLP 1.2/-0.2

Talk Outline

• Background

• Low Power FinFET Circuits– Unusual Logic Styles

– Unusual Dual-Vdd/Dual-Vth Circuits

• Architectural Impact

• Other ongoing work

• Conclusions

FinFET SRAM and Embedded DRAM Design

• FinE: Two-tier FinFET simulation framework for FinFET circuit design space exploration: – Sentaurus TCAD+UFDG SPICE model– Quasi Monte-Carlo simulation for process variation

analysis– Thermal analysis using ThermalScope– Yield estimation

• Variation-tolerant ultra low-leakage FinFET SRAMs at lower technology nodes

• Gated-diode FinFET embedded DRAMs

Extension of CACTI for FinFETs

• Selection of any of the FinFET SRAM and embedded DRAM cells

• Use of any of the FinFET operating modes

• Scaling of FinFET designs from 32nm to 22nm, 16nm and 10nm technology nodes

• Accurately modeling the behavior of a wide range of cache configurations

NATURE

CMOS fabricationcompatible

CMOS fabricationcompatible

Nano RAMon-chip storage

Nano RAMon-chip storage

Run-timereconfiguration

Run-timereconfiguration

Temporallogic folding

Temporallogic folding

Designflexibility

Designflexibility

Logicdensity

Logicdensity

FPGA vs. ASICsFPGA vs. ASICs

• Distributed non-volatile nano RAMs: main storage for reconfiguration bits

• Fine-grain reconfiguration (even cycle-by-cycle) and logic folding More than an order of magnitude

increase in logic density and area-delay product

Competitive performance and moderate power consumption

Non-volatility: useful in low power & secure processing

• NanoMap to map application to NATURE Significant area-delay trade-off flexibility

Conclusions

• FinFETs a necessary semiconductor evolution step because of bulk CMOS scaling problems beyond 32nm

• Use of the FinFET back gate leads to very interesting design opportunities

• Rich diversity of design styles, made possible by independent control of FinFET gates, can be used effectively to reduce total active power consumption

• TCMS able to reduce both delay and subthreshold leakage current in a logic circuit simultaneously

• Time has arrived to start exploring the architectural trade-offs made possible by switch to FinFETs