Study and Comparison of On-Chip LC Oscillators for Energy Recovery Clocking

Master thesis performed in Electronic Devices by

Junaid Aslam

LiTH-ISY-EX-3597-2005

Study and Comparison of On-Chip LC Oscillators for Energy Recovery Clocking

Master thesis performed in

Electronic Devices, Dept. of Electrical Engineering,

at Linköping University by

Junaid Aslam LiTH-ISY-EX-3597-2005

Supervisor: Professor Atila Alvandpour

Examiner: Professor Atila Alvandpour

Linköping 2005-02-16

Avdelning, Institution Division, Department Institutionen för systemteknik 581 83 LINKÖPING

Datum Date 2005-02-16

Språk Language

Rapporttyp Report category

ISBN

Svenska/Swedish X Engelska/English

Licentiatavhandling X Examensarbete

ISRN LITH-ISY-EX-3597-2005

C-uppsats D-uppsats

Serietitel och serienummer Title of series, numbering

ISSN

Övrig rapport ____

URL för elektronisk version http://www.ep.liu.se/exjobb/isy/2005/3597/

Titel Title

Study and Comparison of On-Chip LC Oscillators for Energy Recovery Clocking

Författare Author

Junaid Aslam

Sammanfattning Abstract This thesis deals with the study and comparison of on-chip LC Oscillators, used in energy recovery clocking, in terms of Power, Area of Inductor and change in load capacitance. Simulations show how the frequency of the two oscillators varies when the load capacitance is changed from 5pF to 105pF for a given network resistance. A conventional driver is used as a reference for comparisons of power consumptions of the two oscillators. It has been shown that the efficiency of the two oscillators can exceed that of a conventional driver provided the distribution network resistance is low and the on-chip inductor has a high enough Q value. Conclusions drawn from the simulations, using network resistances varying from 0Ω to 4Ω, show that the selection of the oscillator would depend on the network resistance and the amount of area available for the inductors.

Nyckelord Keyword On-chip oscillators, LC oscillators, energy recovery clocking, on-chip inductor

- 1 -

ABSTRACT

This thesis deals with the study and comparison of on-chip LC Oscillators, used in

energy recovery clocking, in terms of Power, Area of Inductor and change in load

capacitance. Simulations show how the frequency of the two oscillators varies

when the load capacitance is changed from 5pF to 105pF for a given network

resistance. A conventional driver is used as a reference for comparisons of power

consumptions of the two oscillators. It has been shown that the efficiency of the

two oscillators can exceed that of a conventional driver provided the distribution

network resistance is low and the on-chip inductor has a high enough Q value.

Conclusions drawn from the simulations, using network resistances varying from

0Ω to 4Ω, show that the selection of the oscillator would depend on the network

resistance and the amount of area available for the inductors.

- 2 -

- 3 -

ACKNOWLEDGEMENTS

I would like this opportunity to thank my advisor Prof. Atila Alvandpour for all of

his help and useful advice and for providing the resources to work on this Thesis. I

would also like to thank Behzad Mesgarzadeh for helping me during my work on

Dual Phase LC Oscillators, Peter Caputa and Martin Hansson for helping with

interconnect parasitics and Rebecca Källsten for commenting on the report. I

would also like to thank my parents Mr. and Mrs. Aslam for their support

throughout this crucial period and Janina Eidam for the inspiration. Last but not

least I would like to thank God for giving me the will to work.

- 4 -

- 5 -

TABLE OF CONTENTS

ABSTRACT....................................................................................................................- 1 - ACKNOWLEDGEMENTS............................................................................................- 3 - TABLE OF CONTENTS................................................................................................- 5 - 1. INTRODUCTION ..................................................................................................- 7 - SECTION1: INTRODCUTION TO AND SELECTION OF OSCILLATORS ............- 8 - 2. INTRODUCTION TO OSCILLATORS................................................................- 9 -

2.1. Oscillator Types ..........................................................................................- 9 - 2.2. Focus on LC On-Chip Oscillators.............................................................- 11 - 2.3. Resonance of RLC Circuits ......................................................................- 12 - 2.3.1. Parallel LC Resonance..........................................................................- 13 - 2.3.2. Series LC Resonance ............................................................................- 14 - 2.3.3. Quality Factor – Q ................................................................................- 14 - 2.4. Basic Oscillator Model .............................................................................- 16 - 2.5. Negative Resistance ..................................................................................- 18 - 2.6. LC Oscillators ...........................................................................................- 20 - 2.7. Integration of LC Oscillators ....................................................................- 21 - 2.8. Energy Recovery Clocking .......................................................................- 21 - 2.9. Oscillator Selection...................................................................................- 23 - 2.9.1. Hartley Oscillator..................................................................................- 26 - 2.9.2. Colpitts Oscillator .................................................................................- 27 - 2.9.3. Tuned-input Tuned-output Oscillator ...................................................- 29 - 2.9.4. Cross-coupled Inverter Pair Oscillator..................................................- 30 - 2.9.5. 2 Inductor Differential Oscillator..........................................................- 31 - 2.10. Frequency of Operation ........................................................................- 32 -

SECTION2: ON-CHIP INDUCTORS – SCHEMATIC MODEL AND QUALITY FACTOR.......................................................................................................................- 33 - 3. ON-CHIP SPIRAL INDUCTORS........................................................................- 34 -

3.1. Square Spiral Inductor ..............................................................................- 34 - 3.2. Schematic Model ......................................................................................- 35 - 3.3. Q................................................................................................................- 38 - 3.3.1. Effect of width on Q .............................................................................- 39 - 3.3.2. Effect of frequency on Q.......................................................................- 41 - 3.3.3. Combined effect of width and frequency..............................................- 42 - 3.4. Conclusion ................................................................................................- 43 -

SECTION3: SIMULATIONS OF SELECTED OSCILLATORS AND RESULTS ...- 44 - 4. SIMULATION OF DUAL PHASE LC OSCILLATORS IN ENERGY RECOVERY CLOCKING ...........................................................................................- 45 -

4.1. Introduction...............................................................................................- 45 - 4.2. Simulation Setup.......................................................................................- 45 - 4.3. Current Mirror...........................................................................................- 47 - 4.4. Cross-Coupled Inverter Pair Dual Phase Oscillator..................................- 49 -

- 6 -

4.4.1. Effect of Transistor Size on Voltage Swing .........................................- 51 - 4.4.2. Effect of Network Resistance on Transistor Sizes................................- 53 - 4.4.3. Effect of change in load capacitance and network resistance on the frequency of oscillation.........................................................................................- 54 - 4.4.4. Area of the inductor verses Q of Inductor ............................................- 55 - 4.4.5. Power Consumption vs Q of the inductor and Network Resistance.....- 57 - 4.5. 2 Inductor Oscillator .................................................................................- 61 - 4.5.1. Effect of Transistor size on Voltage Swing ..........................................- 62 - 4.5.2. Effect of Network resistance on Transistor Sizes .................................- 63 - 4.5.3. Effect of change in load capacitance and network resistance on the frequency of oscillation.........................................................................................- 64 - 4.5.4. Area of the inductor verses Q of Inductor ............................................- 66 - 4.5.5. Power Consumption vs Q of the inductor.............................................- 67 - 4.6. Comparison ...............................................................................................- 70 -

5. CONCLUSIONS...................................................................................................- 79 - REFERENCES .............................................................................................................- 80 -

- 7 -

1. INTRODUCTION Oscillators are used in digital systems to derive the timing clock. There are

many different oscillators in use today. The focus of the thesis was to do a survey

of oscillators and select ones that can be used on-chip in an energy recovery

clocking scheme and do some comparison simulations on the oscillators. The

break-up of the report is done as follows:-

• Section 1 gives some background on oscillators and deals with the study of

oscillator configurations and discusses the reasons behind the selection or

rejection of oscillators for on-chip integration in an energy-recovery

clocking scheme.

• Section 2 deals with on-chip inductors. The definition of quality factor and

the factors that affect the quality factor of the inductor.

• Section 3 deals with the simulations and results of the two oscillators that

were selected. It shows comparison in terms of change in frequency vs

change in load capacitance, area requirement for inductance and power

consumption.

- 8 -

SECTION1: INTRODCUTION TO AND SELECTION OF OSCILLATORS

- 9 -

2. INTRODUCTION TO OSCILLATORS

Oscillators play an essential role in analog and digital systems. They are used

for mixers and modulators in RF electronics and as clocks in digital electronics.

Design of an oscillator is a non-trivial task and requires a lot of skill and

experience. Difficulty arises because of the fact that we use an inherently non-

linear behavior that cannot be completely described with linear system tools.

Furthermore, oscillators might have to provide power to many circuits (e.g. as a

clock in a digital system). This can make their oscillation frequency dependent on

output load. In the high-frequency area, 1GHz and above, parasitic components

highly impact the performance of the oscillator.

2.1. Oscillator Types

There are basically two types of oscillators widely in use:-

2.1.1. Sinusoidal Oscillators e.g.

• RC Based

• Switched Capacitor Based

• LC Based

• Crystal Oscillator

2.1.2. Square wave Oscillators e.g.

• Ring Oscillator

- 10 -

Figure 2-1: Oscillator classification. This thesis focuses on LC Oscillators

In digital CMOS technology, oscillators are used to generate clocks for the digital

circuitry and can be classified as follows:-

• Off-chip: if the oscillator circuit is fabricated separately and the

signal is brought to the chip via the external contacts. The oscillator

might be made in a different technology.

• On-chip: if the oscillator circuit is on the same chip as the rest of the

circuit and uses the same technology.

Oscillators

Square Wave Sinusoidal

Ring Oscillator

Switched Cap RC LC Crystal

- 11 -

2.2. Focus on LC On-Chip Oscillators

Since there are many different applications of oscillators, their selection

depends on the application in which they are used. It is therefore essential to

narrow down the oscillators based on the application.

This thesis focuses on LC based on-chip Oscillators in CMOS Technology.

The motivations for using such a configuration are:-

• Study of an LC based oscillator requires study of LC tank circuits and

their implementation in CMOS Technology. LC tank circuits have

various applications of interest in digital CMOS technologies most

importantly in clock distribution networks [2] [3].

• LC oscillators can be modified to work in an Energy Recovery Clocking

scheme [4]. Such a scheme is used to reduce the power consumption

due to clocking.

• Though on-chip Oscillators are difficult to design they are preferred

over Off-chip Oscillators because when a clock signal is sent through

the external pins, the signal sees a lot of bond-wire inductance. This

adversely affects the clock signal.

- 12 -

2.3. Resonance of RLC Circuits

Resonance is a term used to describe the property whereby a network

presents maximum or minimum impedance at a particular frequency, for example,

an open circuit or a short circuit. One important resonator is the lumped element

RLC circuit. This is also called a tank circuit. An LC resonator can store energy in

the form of a sinusoid. It works like a pendulum, converting Electrical energy into

Magnetic Energy and vice versa.

The resonance of a RLC circuit occurs when the inductive and capacitive

reactances are equal in magnitude but cancel each other because they are 180

degrees apart in phase. When the circuit is at its resonant frequency, the combined

imaginary component of the admittance is zero, and only the resistive component

is observed. The sharpness of the minimum depends on the value of R and is

characterized by the Q or Quality of the circuit.

The reactance of a capacitor with capacitance C farads is given as

fCX c π2

1= at frequency f. The reactance of an inductor with inductance L Henry is

given as fLX L π2= at frequency f.

As can be seen from these two equations at lower frequencies the inductor

acts as a short circuit while at higher frequencies the capacitor acts as a short

circuit. At the resonance frequency the reactances are equal to each other which

gives us the following equation

fCfL

XX CL

ππ

212 =

= (Eq 2.1)

- 13 -

Solving for f we get the equation for the resonance frequency as

LCf

π21

= (Eq 2.2)

2.3.1. Parallel LC Resonance

Resonance for a parallel RLC circuit is the frequency at which the

impedance is maximum. With values of 1 nH and 1 pF, the resonance frequency

will be approx 5 GHz. Here the circuit behaves like a perfect open circuit. At

frequencies higher or less than 5GHz, the ideal parallel LC presents a short circuit.

Figure 2-2: Parallel LC Tank Circuit with Resistance

Using equation. 2.2 the resonance frequency can be calculated.

- 14 -

2.3.2. Series LC Resonance

Resonance for a series RLC circuit is the frequency at which the impedance

is minimum. With values of 1 nH and 1 pF, the resonant frequency is around 5

GHz. Here the circuit behaves like a perfect short circuit. At frequencies higher or

less than 5GHz, the ideal parallel LC presents an open circuit.

Figure 2-3: Series LC Tank Circuit with Resistance

2.3.3. Quality Factor – Q

Q can be defined as follows [5]

patedpowerdissiavgedenergystorQ

.ω= (Eq 2.3)

For the parallel LC tank circuit, the peak energy stored in either the capacitor

or the inductor is the total energy that is resonating back and forth between the

inductor and the capacitor. The peak capacitor voltage at resonance is Vpk = IpkR

where Ipk is the peak current and the R is the resistance of the network in ohms as

- 15 -

shown in Figure 2-2. Therefore the total energy stored in the tank circuit can be

written as [5]

2)(21 RICE pk= (Eq 2.4)

At resonance the circuit in Figure 2-1 degenerates to a simple resistance.

The avg. power dissipated can therefore be written as [5]

RIP pkavg2

21

= (Eq 2.5)

Using equation 2.4 and 2.5 and substituting in equation 2.3 we get the Q for

a parallel LC tank as [5]

CLRQ = (Eq 2.6)

or

fRCfL

RQ ππ

22

== (Eq 2.7)

The quality factor of a series LC Network can also be derived similarly and

is given as follows

RC

LQ = (Eq 2.8)

or

fRCRfLQ

ππ

212

== (Eq 2.9)

- 16 -

2.4. Basic Oscillator Model

The most important part of an oscillator is a positive feedback loop circuit.

Figure 2-4 shows the generic loop representation of such a circuit [1].

Figure 2-4: Basic Oscillator Configuration

HA(ω) is the transfer function of the amplification stage. HF(ω) is the

transfer function of a feedback stage. The closed-loop transfer function [1] of the

configuration shown in Figure 2-4 is:

( )( ) ( )ωωω

FA

A

HHH

VinVout

−=

1 (Eq 2.10)

Since there is no input to an oscillator [1] Vin = 0, this would require a non-

zero output voltage, Vout. This brings us to the Barkhausen Criterion which states

that for Vin = 0, the following relationship should hold for stable oscillations:-

( ) ( ) 1=ωω AF HH (Eq 2.11)

The amplifier transfer function has a real valued gain i.e. HA(ω) = HA0(ω).

Further dividing HF(ω) into real and imaginary parts HFr(ω) and HFi(ω)

HA(ω)

HF(ω)

+Vin

Vf

Vout

- 17 -

respectively the following initial condition should hold for an oscillator circuit to

start oscillating [1]

1)()( >ωω AFr HH (Eq. 2.12)

Under stable operation the following condition should hold [1]

0)(1)()(

==

ωωω

Fi

AFr

HHH

(Eq. 2.13)

- 18 -

2.5. Negative Resistance

The idea of negative resistance can be explained from the circuit [1] shown

in Figure 2-5. The circuit consists of a series resonance circuit consisting of

resistance R, inductance L, and capacitance C. The figure also shows a current-

controlled voltage source. This voltage can represent the output of a CMOS

device. The equation of the circuit in terms of current can be written as [1]

]

dtidvti

CdttdiR

dttidL )()(1)()(

2

2

−=++ (Eq 2.14)

When the oscillator reaches steady-state and the voltage amplitude is stable, the

right hand side of equation 2.14 can be set to zero. The provides us with the

following solution to the equation [1]

)()( 21tjtjt eIeIeti ωω −∂ += (Eq 2.15)

where L

R2

−=∂

and 2

21

⎟⎠⎞

⎜⎝⎛−=

LR

LCω

Figure 2-5: Series resonance circuit

R L Cv(i)

- 19 -

Since ∂ is a negative quantity, as time progresses the harmonic response of the

circuit will reduce to zero because of the ohmic losses in the resistance. If the

value of R reaches zero, the sinusoid that is obtained is undamped and there are no

ohmic losses, such that the energy resonates between the inductor and the

capacitor.

The goal of a CMOS device in an oscillator is to generate a source response

that compensates for this resistance. This is achieved by providing a negative

resistance [1]. If the device that we include in the oscillator has a voltage current

response that is described by the following equation [1]

2

210)( iRiRviv ++= (Eq 2.16)

The terms can be adjusted to compensate for the resistance in the circuit. If

the first to terms of equation 2.16 are substituted into equation 2.14 we obtain the

following equation [1]

dttdiR

dtidvti

CdttdiR

dttidL )()()(1)()(

12

2

−=−=++ (Eq 2.17)

If the terms of the first derivative are combined then we will see that

R1 + R = 0 (Eq 2.18)

Equation 2.18 is the requirement to have an undamped sinusoid response

from the oscillator. Therefore the negative resistance that the device or devices

attached to the LC tank circuits will be

R1 = -R (Eq 2.19)

- 20 -

2.6. LC Oscillators

LC oscillators such as the one shown in Figure 4-5 can be modeled as

shown in Figure 2-6 [10]. The right side block represents a differential input

transconductor. The tank losses are lumped together in a resistor R. The tank

losses can be measured in terms of Q factor of the tank as well. The losses are

compensated by the differential transconductor connected in a positive feedback

which acts as negative resistance [10]. The circuit oscillation is defined by the

value of inductance L and capacitance C used in the circuit.

The output amplitude of the oscillator depends upon the current that passes

through the active devices used in the oscillator. In our case the devices used to

produce negative resistance are CMOS devices. The width of these CMOS devices

dictates the current passing through them and consequently the output amplitude.

For high enough amplitudes differential pairs such as the one showed in Figure 2-

10 switch almost ideally. Using a PMOS differential pair allows more efficient use

of the bias current.

Figure 2-6: LC Oscillator Model

transconductor

I tank

RtankCL

Sinusoid Output

- 21 -

2.7. Integration of LC Oscillators

On-chip LC resonant circuits in CMOS technologies are made using square

spiral inductors such as the one shown in Figure 3-1. As will be described later

when we describe energy recovery clocking, the capacitance is the parasitic

capacitance of the load. This is generally in the pF range. The draw-back of a fully

integrated approach of making LC Oscillators is the low quality factor of the

inductor especially due to series resistance and the parasitic capacitances present

in the inductor and also due to the resistance present in the distribution network.

This increases the power dissipation required to achieve the desirable amplitude

seen at the load. Since the capacitance comes from the load, there is no knowledge

of the quality factor of the capacitance. However, the quality factor of the inductor

is available and also there is some idea into how much network resistance is

present. Therefore, on-chip inductors and their quality factors have been discussed

in Chapter 3. In chapter 4 simulations of two oscillator circuits have been done

using network resistance and an on-chip inductor model.

2.8. Energy Recovery Clocking

Energy recovery clocking has been introduced in [2], [3] and [4].

Depending on the type of oscillator used LC resonance circuit is formed with the

inductor that has been fabricated on-chip and the parasitic load capacitance. The

frequency depends upon the values of the on-chip inductance and the amount of

parasitic load capacitance that is present. If the oscillator shown in Figure 4-5 is

used then energy recovery clocking is achieved as shown in Figure 2-7.

- 22 -

Logic

Logic

Logic

Logic

Logic

Logic

Logic

Logic

Figure 2-7:- Energy recovery clocking using cross coupled inverter pair oscillator

Cload is the parasitic capacitance of the load and is used as part of the LC tank

circuit. Rnw is the resistance of the distribution network. This resistance has to be

kept as small as possible because a large amount of energy is lost is due to this

resistance. L is the on-chip inductor. If the oscillator shown in Figure 4-14 is used

then energy recovery clocking is achieved as shown in Figure 2-8.

VDD

L

Cload

Cload

Rnw

Rnw

Clk

Clk bar

- 23 -

Logic

Logic

Logic

Logic

Logic

Logic

Logic

Logic

Figure 2-8:- Energy recovery clocking using 2inductor oscillator

Using energy recovery clocking scheme, power savings of up to 30% have been

reported [3]. Therefore energy recovery clocking shows potential for low power

clocking. Two oscillators have been simulated and compared using a test-bench

and the results have been discussed in chapter 4.

2.9. Oscillator Selection

There are different types of oscillator configurations that are used. The

oscillators can be qualified upon what type of LC circuit is used and also on how

the negative resistance is created. The LC circuit can have different types of

topologies. These different topologies have been shown in Figure 2-9. Different

topologies have different names.

Cload

Rnw

L

VDD

Cload

Rnw

L

Clk

Clkbar

- 24 -

Figure 2-9: Different LC networks used in oscillators

There are also different types of differential negative resistances that can be

created. Figure 2-10 a) and b) show two different ways to create negative

resistance. If we look closely at Figure 2-10 a) we see that this is actually a cross-

coupled inverter structure. Using differential PMOS along with differential NMOS

gives the oscillator more gain but at the expense of more power consumption,

increase in number of devices and area.

a) Hartley b) Colpitts

c) Parallel LC d) Clapp

e) Series LC

L1 L2

C

C1 C2

L

L CC1 C2

C3 L

L

C

- 25 -

Figure 2-10: Negative resistance by using differential cross-coupled PMOS and NMOS devices

Selecting which type of oscillator would be suitable for on-chip integration

is based on the application that we are interested. As mentioned before the

application of interest is to integrate an LC Oscillator on chip in an energy

recovery clocking scheme. The selection therefore depends upon a number of

factors. The most important factor that was considered for selection was whether

or not the oscillator can be used in the energy recovery clocking scheme. To be

a) Differential PMOS and NMOS or Cross-Coupled Inverter Pair

b) Differential NMOS

- 26 -

usable in such a scheme, there should be at least one capacitance in the LC

network that has one port connected to the ground. This capacitance is then

replaced by the load capacitance. The other factors include capacitance

requirement and the effect of change in load capacitance on the functionality of

the oscillator. A number of oscillators were surveyed and based upon the above

mentioned criteria were selected or rejected. Some of these oscillators are shown

as follows:-

2.9.1. Hartley Oscillator

This oscillator is shown in Figure 2-11 [1]. The LC network has two

inductors and one capacitance. The NMOS amplifier is connected in a common

gate configuration. Looking at the figure it can be seen that this oscillator fails the

first and most important criteria. It cannot be used in energy recovery clocking.

The capacitance C3 has one port connected to L1 and the other port connected to

L2. There is no way to replace this capacitance with the load capacitance. This

oscillator was therefore rejected for simulations.

- 27 -

Figure 2-11: NMOS Hartley Oscillator

2.9.2. Colpitts Oscillator

This oscillator is shown in Figure 2-12 [5]. This oscillator has a capacitively

tapped resonator, with a positive feed-back provided by an active device. The

resistance R shown in Figure 2-12 represents loading due to finite Q. From the

figure it can be seen that capacitor C2 can be replaced by a load capacitance and

hence this oscillator can be used for our application. Investigating this oscillator

further we see that [5]

nVtVout = (Eq 2.20)

where ( )211CC

Cn+

= (Eq 2.21)

VDD

L1 L2

C3

- 28 -

From equation 2.20 we see that in order to increase the amplitude of Vout,

the amplitude of Vt has to be increased. The n factor is the ratio between Vt and

Vout. The n factor has to be made as close to one as possible to ensure that Vout

and Vt have similar amplitudes. The need to have similar amplitudes is expressed

by the following example. Suppose the n factor is 0.3. In order to have an

amplitude of 900mV on Vout, the amplitude of Vt has to be 2700mV. On the other

hand if the n factor is 0.95 then the amplitude of Vt has to be 947mV. Clearly if

the n factor is too low, there will be unnecessary power consumption due to the

high amplitude on Vt. From equation 2.21 it is seen that in order to have an n

factor as close to one as possible, C1 has to be much larger than C2. This would

mean that if we replace C2 with the load capacitance, then a capacitance much

larger than the load that is being driven has to be made with in the oscillator. A lot

of area is consumed to make this capacitance. Furthermore, the larger the

capacitance, the larger will be the power consumption of the oscillator. This makes

this oscillator unsuitable for use in our application. This oscillator was therefore

rejected.

Figure 2-12: Colpitts Oscillator

VDD

V Bias

L R

C1

C2

Vt

Vout

- 29 -

2.9.3. Tuned-input Tuned-output Oscillator

This oscillator is shown in Figure 2-13. It can be used in an energy

recovery scheme by replacing capacitance C3 by the load capacitance. This

oscillator has the same problems as discussed for the Colpitts oscillator. It requires

its own capacitance along with the capacitance of the load to work. An additional

strike against this oscillator is the need for careful tuning of the two tank circuits

for proper oscillation. From [3] we know that the load capacitance is not constant

and changes with the change in data activity. Since the load capacitance is

changing, the oscillator would require continuous tuning for proper operation. This

has a lot of performance overhead. Two inductors are being used just to generate a

single phase. As will be discussed in chapter 3, inductors consume a lot of area.

Therefore using this oscillator for our application is not feasible.

Figure 2-13: Tuned-input Tuned-output Oscillator

VDD

L1 C1

C2

L2 C3

- 30 -

2.9.4. Cross-coupled Inverter Pair Oscillator

This is a dual phase oscillator and is shown in Figure 2-14 [9], [10], [11]. It

uses a cross-coupled inverter structure to create negative resistance. This is the

same structure as the cross-coupled differential structure shown in Figure 2-10.

Looking at Figure 2-14 we see that it can be used in an energy recovery clocking

scheme by replacing capacitances C1 and C2 with the load. The oscillator

generates a sinusoid using one inductor whose both ends are connected to the

output of the two inverters. The capacitance is used entirely from the parasitic

capacitance of the load and it does not require any capacitance of its own to

operate. Furthermore it does not require careful tuning like the Tuned-Input

Tuned-Output oscillator mentioned in 2.9.3. It has at least two devices operating at

the same time and therefore has a high gain. This means that the oscillator can

handle large amounts of load. This oscillator is highly suited to our application.

This oscillator was therefore used for simulations, for energy recovery clocking.

Figure 2-14: Cross-coupled Inverter Pair Dual Phase Oscillator

VDD

C1 C2

L

- 31 -

2.9.5. 2 Inductor Differential Oscillator

This is also a dual phase oscillator and is shown in Figure 2-15 [3], [12],

[13],[14]. It uses a cross-coupled NMOS structure to create negative resistance.

This is the same as the cross-coupled NMOS structure shown in Figure 2-10.

Looking at Figure 2-15 we see that it can also be used in an energy recovery

clocking scheme by replacing capacitances C1 and C2 with the load. The

oscillator generates a sinusoid using two inductors, one for each phase. The

capacitance is used entirely from the parasitic capacitance of the load and it does

not require any capacitance of its own to operate. It also does not require careful

tuning. As compared to the cross-coupled inverter oscillator in 7.4, this oscillator

has lesser amount of gain and therefore comparatively can take lesser amount of

load at the output. It is also suited for our application. It was therefore used for

simulations, for energy recovery clocking.

Figure 2-15: 2 Inductor Dual Phase Oscillator with differential NMOS structure

VDD

L1 L2

C1 C2

- 32 -

2.10. Frequency of Operation

Though simulations have been performed at various frequencies, the frequency

of interest is 1GHz. This frequency is feasible for sinusoidal clocking of Logic

Blocks. Furthermore, parasitics such as Resistance of the Inductor and the

Resistance of the distribution network hinder the use of higher frequencies.

- 33 -

SECTION2: ON-CHIP INDUCTORS – SCHEMATIC MODEL AND QUALITY FACTOR

- 34 -

3. ON-CHIP SPIRAL INDUCTORS

3.1. Square Spiral Inductor

The most widely used on-chip inductor design is the square spiral inductor

as shown in Figure 3-1 [9]. Although a circular spiral has been known to

provide more inductance, the square version has been chosen because it is

supported by most CMOS technologies. It is best to make the inductor in the

top-most layer of the process since most of the logic is in lower layers and that

higher layers have lesser sheet resistance. Calculation of L (inductance in H) of

on-chip inductors is based on the value of width, the number of turns, the outer

and inner diameters etc.

Figure 3-1: On-chip Spiral Inductor in MET6. To bring the inner contact out, a separate metal layer (MET5) is needed (Figure 3-1, Port2).

Port 1 Port 2

IL

Port 2

OL

D

W

Met6 Met5

- 35 -

The different labels in Figure 3-1 can be explained as follows:-

Port 1 and Port 2 are the places where the inductor is connected.

W is the width of the interconnects. Using greater width means lesser resistance

and hence less losses. The width greatly affects the quality factor of the inductor

as will be shown when Q is discussed

D is the spacing between the interconnects

IL is the inner dimension of the inductor

OL is the outer dimension of the inductor

3.2. Schematic Model In general terms the spiral inductor is a distributed structure. There is

capacitive and inductive coupling between the metal strips and the substrate.

Series resistance is distributed over the entire circuit. The best and the fastest way

to simulate an on-chip inductor at the frequency of interest is to use a lumped

schematic model [7],[8],[15],[16] which accurately models the parasitics that are

present in the spiral inductor. The schematic is shown in Figure 3-2.

Figure 3-2: Lumped Schematic Model of on-chip Inductor

- 36 -

L(ls in the Figure) is the inductance of the coil and can be calculated by using

a Modified Wheeler Formula [6] :-

ρµ

2

2

01 1 KdN

KL avg

+= (Eq 3.1)

where N is the number of turns of the inductor while davg = 0.5(OL+IL). K1 and

K2 are dependent on the shape of the inductor [6]. ρ is the fill ratio and is

defined as ρ = (OL - IL)/(OL + IL). ρ represents how hollow the inductor is.

For a smaller value of ρ we have a more hollow inductor (value of OL is

comparable to IL). For larger values of ρ the inductor is fuller. Two inductors

with the same davg but different fill ratios will have different inductance values.

The full inductor has lesser inductance because its inner turns are closer to the

centre of the spiral and hence contribute with less positive mutual inductance

and more negative mutual inductance.

Cp is the lumped overlap capacitance between the metal 6 layer and the part of

the metal 5 layer that has been routed underneath Metal 6 to provide an output

port as shown in Figure3-2. Cp can be calculated by using equation 3.2.

56

2 **ox

oxp t

WNCε

= (Eq 3.2)

Where N is the no of turns. W is the width of the interconnect. oxε is the

permittivity of the oxide. 56oxt is the thickness of the oxide between Metal 6

and Metal 5.

Cox is the lumped capacitance between the Metal 6 layer and the substrate and

can be calculated using equation 3.3.

ox

oxox t

WlCε

***21

= (Eq 3.3)

- 37 -

Where l is the length of the inductor and oxt is the thickness of the oxide layer

between Met 6 and Substrate.

rs is the resistance of the interconnect and can be calculated by using the sheet

resistance of Met 6.

r1 is a parameter that models substrate losses. The ohmic loss in r1 signifies the

energy dissipation in the silicon substrate and can be calculated using equation

3.4 [15].

GSUBlWr

**2

1 = (Eq 3.4)

Where GSUB is substrate conductance per unit area

c1 is a parameter that models substrate capacitive effects and can be calculated

using equation 3.5.

2**

1CSUBlWc = (Eq 3.5)

CSUB is substrate capacitance per unit area.

The effect of inter-turn fringing capacitance is small because the adjacent turns

are almost equipotential and therefore ignored for this model. The overlap

capacitance Cp is more significant because a large potential difference exists

between the inductor and the underpass [15].

- 38 -

3.3. Q As can be seen from the schematic in Figure 3-2, an on-chip inductor is not

ideal. The series resistance rs in the inductor is the cause of ohmic losses which

have to be compensated. Compared to an ideal inductor, more Power is consumed

when sustaining oscillations in an LC tank circuit when an on-chip inductor is

used. The other parasitics shown in the schematic also contribute to losses. An

adequate way to evaluate the losses of an inductor is the Quality factor which is

defined in equation 3.6.

Q of the on-chip Inductor can be defined as follows [7]:-

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛++−

⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢

⎣

⎡

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛+⎟⎟

⎠

⎞⎜⎜⎝

⎛+

=L

rLCc

rLrr

rrLQ s

pp

ssp

p

s

22

2)(1

1

ωω

ω (Eq. 3.6)

where ( )2

211

122

1

ox

ox

oxp C

cCrrC

r+

+=ω

and ( )( ) 2

12

12

2111

2

11

rcCrccC

Ccox

oxoxp

++

++=

ωω

In equation 3.6 srLω corresponds the magnetic energy stored and the losses

in the series resistance in rs. The second factor in equation 3.6 represents the

substrate loss factor representing the energy dissipated in the semi conducting

silicon substrate. The last factor is the self-resonance factor describing the

reduction in Q due to the increase in the peak electric energy stored in the parasitic

capacitances of the inductor [15]. The only useful energy stored in the inductor is

the magnetic energy stored in the coil. The electric energy stored in the parasitic

capacitances is counterproductive.

- 39 -

At a frequency of 1GHz, most of the losses in an inductor are caused by the

series resistance rs. Resistance of a conductor is inversely proportional to its cross-

sectional area. Increasing the cross-sectional area will decrease the resistance

through the wire. This cross-sectional area is dependent on the thickness and the

width of the wire. In our particular situation the technology is fixed. This means

the thickness of the metal layers and the substrate capacitance and conductance per

unit area are fixed. Therefore the most significant factor that can affect Q is the

width of the wire. As can be seen from equation 3.2 to equation 3.5 the parasitics

are dependent on the dimensions of the inductor. Making an inductor wider

reduces the series resistance but on the other hand increases the parasitic

capacitances.

The higher the Q, the less losses will be encountered which translates to less

Power Consumption. Important factors that affect Q are:-

1. Width W of the inductor

2. Frequency at which the LC tank circuit is resonating

3.3.1. Effect of width on Q Making an inductor wider decreases the series resistance. Series resistance

is the most significant factor affecting Q. Therefore, making a wider inductor can

increase the Q factor at a particular frequency to a certain extent. The effect of W

at a frequency of 1GHz can be seen from Table 3-1, Figure 3-3 and 3-4. The

inductor value is 0.78nH. It has 2 turns and a spacing of 1µm. The outer diameter

OL of the inductor depends on how wide the inductor wire is. Table 3-1: Effect of Width on Q and outer dimension of the inductor

W µm

OL µm

Q

18 159 1.42 38 233 2.31 58 300 2.96 78 363 3.45 98 423 3.85

- 40 -

Effect of W on Q

00.5

11.5

22.5

33.5

44.5

18 38 58 78 98

W(µm)

Q

Figure 3-3:Effect of the width of the inductor on Q at 1GHz.

From Figure 3-3 we can see that at a frequency of 1GHz and a spacing of

1µm, making an inductor with a width of 98µm provides a higher Q value than the

narrower options. One big consequence of using wider inductors is that they cover

more area. Since area on a chip is limited we cannot make an inductor infinitely

wide. Figure 3-4 illustrates how the outer dimension increases as the width of the

inductor increases.

The greater the outer dimension, the more area the inductor covers.

- 41 -

Outer Dimension vs Width

050

100150200250300350400450

18 38 58 78 98

W (µm)

OL

(µm

)

Figure 3-4: Effect of the width on the outer dimension of the inductor OL.

3.3.2. Effect of frequency on Q Incase of ideal inductors the Q value increases with the increase in

frequency infinitely. This is however not the case for on-chip Inductors because

the parasitic capacitance and substrate losses show their significance at higher

frequencies. The effect of frequency on the Q value can be seen in Table 3-3. The

inductance is 0.78nH. Width of the inductor is 58µm.

Table 3-3: Frequency vs Q

F GHz

Q

0.2 0.61 0.5 1.52 1 2.93

1.5 4.01 2 4.35

2.5 3.36 3 0.25

- 42 -

Frequency vs Q

0

2

4

6

8

10

0.2 0.5 1 1.5 2 2.5 3

Frequency GHz

Q

Considering Cap and Res Considering Res only

Figure 3-5: Shows the effect of resonance frequency on Q From Figure 3-5 it can be see from the solid line that the Q value first

increases with frequency and then decreases. The second and third factor in

equation 3.6 begin to show their effects at higher frequencies and adversely affect

the Quality factor. For this particular situation, the highest Q is obtained at a

frequency of 2GHz. If we would ignore the second and third terms in equation 3.6

then the quality factor would be affected by frequency in the way shown by the

dotted line in Figure 3-5.

3.3.3. Combined effect of width and frequency

Figure 3-6 shows the combined effect of width and frequency on the Q

factor with a 3D Mesh. The conclusion that can be made from this figure is that

although increasing the width increases the Q factor, by decreasing the series

resistance, there is a limit on how wide an inductor can be made. This is because

the parasitic capacitances and substrate losses also begin to increase as the width is

increased. As the frequency increases we can see from Figure 3-6 that the effects

begin to be more obvious as the Q factor is decreasing with the increase of width.

- 43 -

Figure 3-6: 3D Mesh that shows the combined effect of width and frequency

3.4. Conclusion It can be seen from the simulations that inductors of many different Q

values can be made on-chip. Using wider inductors decreases the series resistance

and has a positive effect on Q. On the other hand if the inductor is too wide, the

inductor will cover a lot of area and the parasitic capacitance and substrate losses

will increase. Therefore, an inductor has to be made keeping in mind the required

Power Consumption, Available Area and Oscillation Frequency of interest.

Q

Width µm F GHz

- 44 -

SECTION3: SIMULATIONS OF SELECTED OSCILLATORS AND RESULTS

- 45 -

4. SIMULATION OF DUAL PHASE LC OSCILLATORS IN ENERGY RECOVERY CLOCKING

4.1. Introduction Energy recovery clocking schemes have been discussed in some research

papers [2], [3] and [4] and has been introduced in Ch-2. Such power-saving

clocking schemes show some potential and power consumption reduction of 35%

has been reported [3]. Comparison of two dual phase cross-coupled oscillator

structures that can be used for energy recovery clocking has been done. The two

oscillators have been compared in terms of power consumption, change in

frequency vs change in load capacitance and area requirements for the inductors

that each requires. All the oscillators need a start-up pulse in the beginning but

once started up the oscillations are self-sustaining and a clock is not required.

Before giving some introduction to the oscillators themselves, it is important to

give some understanding to what the application is and in which environment the

oscillators have been used and according to what standard the total power

consumption of the oscillators has been compared.

4.2. Simulation Setup An LC oscillator sees a lot of resistance when it is connected to the

distribution network. When the energy stored in the LC tank resonates back and

forth between the load capacitance and the inductance of the oscillator, a large

amount of energy is lost in the resistance of the distribution network. For these

simulations this resistance has been lumped together as one big resistance

connected between the output of the oscillator and the load capacitance. This

simulation setup has been shown in Figure 4-1.

- 46 -

Figure 4-1: Simulation Setup. The outputs of the two oscillators are connected to a resistance and a load Capacitance. The oscillators entirely use the load capacitance as part of the LC tank, just

as they would be used in an energy recovery clocking scheme. Since the logic sees

the sinusoid after going through the resistance of the network, the voltage swing

and frequency are measured after it has passed through the resistance. The power

is calculated by first measuring the average current that is being drawn from the

power supply and multiplying that with the voltage.

For comparison purposes a conventional driver such as the one shown in

Figure 4-2 is used. There is a chain of four inverters. A square wave clock is

generated and given as an input to the first inverter. The first two inverters are

sized such that they slightly reduce the edge rate because in reality when a

conventional driver receives a clock its edge rate is also not perfectly sharp. The

last two drivers are progressively sized, with the second last inverter being 1/5th of

the last inverter. The inverters are sized such that they give a bad edge rate which

is as close as possible to the sinusoid generated by the oscillators. There is no

resistance connected to the output of the conventional driver since it does not

significantly affect the power consumption of the conventional driver. The total

load capacitance that has been connected is 60pF because the total capacitance that

- 47 -

the LC oscillators see at both phases is also 60pF. The power consumption

measured for comparison is only that of the last two inverters.

Figure 4-2: Schematic of conventional driver

4.3. Current Mirror If the load capacitance and resistance is too high for the oscillators, a

current mirror circuit [10] [12] can be used to assist the oscillators and ease

transistor sizing. Instead of connecting the source of the NMOS transistors in the

oscillators to ground, it is connected to the drain of M5 in the mirror circuit which

is shown in Figure 4-3. The drain of transistor M4 is then connected to a separate

voltage supply. The current mirror circuit assists by providing more current to the

oscillators. This however comes at the expense of power consumption. The

amount of current can be adjusted by changing the width of the NMOS transistors.

Over-sizing the transistors will result in unnecessary power consumption. Figure

4-4 demonstrates how the current mirror circuit is connected to the cross-coupled

inverter pair oscillator described in section 4.

- 48 -

Figure 4-3: Current Mirror Circuit

Figure 4-4: Current mirror circuit connected to the cross coupled inverter pair oscillator

M5M4

- 49 -

4.4. Cross-Coupled Inverter Pair Dual Phase Oscillator This oscillator is shown in Figure 4-5 [9], [10], [11]. It has a cross coupled

inverter structure where the outputs of the two inverters are connected to each

others inputs. The oscillator therefore requires two PMOS transistors labeled M1

and M2 in Figure 4-5 and two NMOS transistors labeled M0 and M3 to operate.

The oscillator generates a sinusoid using one inductor whose both ends are

connected to the output of the two inverters. The capacitance used is entirely the

parasitic capacitance of the load.

During the instant when output vout is at its peak voltage and voutbar is at

its minimum, transistor M1 and M3 are turned on which then forms a parallel LC

Tank circuit with inductance L0 and the load capacitance shown in Figure 4-1

which is connected to Vout. When voutbar is at its maximum voltage then a tank

circuit is formed with inductance and the load Capacitance connected to voutbar.

- 50 -

Figure 4-5: Cross-Coupled Inverter Pair Dual Phase LC Oscillator

- 51 -

4.4.1. Effect of Transistor Size on Voltage Swing Increasing the size of the transistors increases the voltage swing. This

occurs because when the width of the transistors is increased, the resistance of the

transistors decreases, resulting in more current passing through the transistor

which consequently increases the voltage swing. This however comes at the

expense of increased power consumption. Hence a trade off has to be made of the

voltage swing verses the power consumption.

The size of the PMOS transistor dictates how high the voltage is in the

positive cycle and the size of the NMOS transistor dictates how low the voltage is

in the negative cycle. Using a PMOS to NMOS ratio of approx 2 makes the

sinusoid symmetric. The effect of transistor sizes on peak to peak voltage of the

sinusoid and power consumption of the oscillator is illustrated in Table 4-1. The

table shows how the peak to peak voltage and power increase with the increase in

transistor size when the oscillator is operating at a frequency of 1GHz and using

ideal inductors. The width of the PMOS and NMOS transistors is wp and wn

respectively. Figure 4-6 is the peak to peak voltage swing versus the normalized

widths of the PMOS and NMOS transistors. A normalized width of 1 is equal to

100µm for an NMOS and 200µm for a PMOS transistor. Similarly Figure 4-7

shows the power consumption of the oscillator vs the normalized width of the

NMOS transistors.

Table 4-1: Transistor sizes vs peak to peak voltage of the signal and power consumption of the oscillator using ideal inductors

wp µm

wn µm

Voltage Swing mV

Power mW

800 400 980.12 39.42 400 200 845.89 30.62 200 100 586.13 19.8

- 52 -

Peak to Peak Voltage vs Normalized Width

550600650700750800850900950

10001050

1 2 4

Normalized width of transistors

Pk to

Pk

Vol

tage

V

Figure 4-6: Peak to Peak voltage of the sinusoid as seen at the load vs the normalized transistor width. Normalized width of 1 stands for a width of 200µm for a PMOS transistor and 100µm for an NMOS transistor.

Power Consumption of the Oscillator vs Normalized Width

18

23

28

33

38

43

1 2 4

Normalized Width

Pow

er C

onsu

mpt

ion

mW

Figure 4-7: Power consumption of the oscillator vs normalized width of the transistor. Normalized width of 1 stands for a width of 200µm for a PMOS transistor and 100µm for an NMOS transistor.

- 53 -

4.4.2. Effect of Network Resistance on Transistor Sizes When the distribution network resistance increases, this decreases the

voltage swing that is seen at the load because of losses in the resistance. Therefore

in order to compensate for this loss in voltage swing the widths of the transistors

have to be increased. This is shown in Table 4-2 which shows how the transistor

size is affected when the network resistance is increased. Rnw is the resistance of

the network in ohms and the voltage swing is 700mV. Figure 4-8 shows the

normalized widths of the transistors vs the network resistance. A normalized width

of 1 stands for a width of 75µm for a PMOS transistor and 37.5µm for an NMOS

transistor. The figures give us an idea of how to compensate for the decrease in

voltage swing seen at the load due to increase of the network resistance by making

the transistors larger.

Table 4-2: Transistor sizes vs network resistance using ideal inductors wp µm

wn µm

Rnw Ω

75 37.5 0.5 150 75 1 200 100 1.5 300 150 2

- 54 -

Normalized Transistor width vs Network resistance

00.5

11.5

22.5

33.5

44.5

0.5 1 1.5 2

Network resistance Ω

Norm

aliz

ed tr

ansi

stor

wid

th

Figure 4-8: Effect of change in network resistance on transistor sizes for a fixed voltage swing and frequency. Normalized width of 1 stands for a PMOS width of 75µm and an NMOS width of 37.5µm

4.4.3. Effect of change in load capacitance and network resistance on the frequency of oscillation

To see the effects of change in load capacitance on the LC oscillator, the

load capacitance has been changed from 5pF to 135pF on both phases with an

inductance value of 1.2nH. How the change in load capacitance affects the

frequency when the network resistance is changed between 0.01Ω and 5Ω can be

seen in Figure 4-9. The figure shows the load capacitance versus frequency. Width

of PMOS is 500µm, width of NMOS is 250µm, the inductor has a value of 1.2nH

and has a resistance of 1.7Ω. The power supply voltage is 0.9V.

- 55 -

Frequency vs load Capacitance with a resistance of 0.01 to 5 Ohms

0.400

0.900

1.400

1.900

2.400

5 15 25 35 45 55 65 75 85 95 105

Cload pF

Freq

uenc

y

0.01 1 5 3

Figure 4-9: Effect of change in capacitance on the frequency of oscillation for different resistance values

For a resistance of 1Ω the same trend continues until a capacitance of

120pF and then the oscillator stops oscillating. With the resistance of 0.01Ω the

trend continues until a capacitance of 405pF. For resistance values of 3Ω the

frequency decreases with the increase in load capacitance until it reaches 45pF and

then increases until it reaches 65pF after which there are no sustainable

oscillations. At 5Ω the frequency decreases with the increase in load capacitance

until it reaches 25pF and then increases with the increase in load capacitance until

2nF. It can be seen from the figure that lesser the network resistance, the closer is

the frequency response of an oscillator to an LC Tank circuit.

4.4.4. Area of the inductor verses Q of Inductor As was discussed in chapter 3, the quality of an inductor can be increased

by increasing the width of the inductor wire. Increasing the width also increases

the dimensions of the inductor. Consequently, in order to increase the Q of an

inductor we need to cover more area. Also, the greater the number of inductors

Ω

- 56 -

used in the oscillator, the more area will be covered by the inductances for a given

Q value. Table 4-3 and Figure 4-10 show the total area covered by the inductor for

different Q values to attain a frequency of approx 1GHz when a load capacitance

of 30pF is present.

Table 4-3: Approximate area covered by the inductors for a given Q value of inductor

Approx Q Area µm2

2.5 90,0003.3 160,0004.2 360,0004.9 490,000

Inductor Area vs Inductor Q

0

100000

200000

300000

400000

500000

600000

2.8 3.5 4.2 4.9

Q

Are

a (s

quar

e µm

)

Figure 4-10: Approximate area covered by the inductors for a given Q value of inductor

- 57 -

4.4.5. Power Consumption vs Q of the inductor and Network Resistance

The power consumption for a fixed voltage swing and frequency depends

mainly on the network resistance, the amount of load capacitance and the quality

of the inductors. For a fixed load capacitance and network resistance, the power

consumption depends on the Q value of the inductor. Lower Q values mean

greater losses in the inductor and hence the power consumption of the oscillator is

increased. Network resistance has a big impact on the power consumption of the

oscillator as well. The network resistance should be properly estimated in order to

know how efficient the oscillator will be when it is placed in the application

environment. Table 4-4 illustrates how the power consumption is affected by the

change in Q value of the inductor and network resistance. The inductance value

lies between 1.2~1.4nH. Table 4-4: The power consumption of the oscillator vs the quality factor of the inductor for 0.01 to 4Ω network resisance

QL

Quality of

Inductor

Rnw Ω Network

Res.

wp(µm) width of

PMOS

wn (µm)

width of

NMOS

wbias (µm)

width of current mirror bias

Supply Voltage

V

Power Consumption

mW

1.6 0.01 1000 500 - 1 82.81 2.7 0.01 400 200 - 0.9 21.32

4 0.01 250 125 - 0.9 12.64 4.6 0.01 200 100 - 0.9 10.62 5.4 0.01 150 75 - 0.9 5.056 1.6 1 1000 500 - 1 85.21 2.7 1 600 310 - 1 47.21

4 1 360 180 - 1 28.89 4.6 1 320 160 - 1 26.27 5.4 1 270 135 - 1 22.23 1.6 2 1000 500 - 1 86.46 2.7 2 950 475 - 1 68.68

4 2 700 350 - 1 50.69 4.6 2 580 290 - 1 44.81 5.4 2 500 250 - 1 37.36 1.6 3 - - - 1 - 2.7 3 1200 800 400 1 120.41

4 3 1000 800 400 1 102.95

- 58 -

QL

Quality of

Inductor

Rnw Ω Network

Res.

wp(µm) width of

PMOS

wn (µm)

width of

NMOS

wbias (µm)

width of current mirror bias

Supply Voltage

V

Power Consumption

mW

4.6 3 1000 800 400 1 102.31 5.4 3 1000 800 350 1 91.44 1.6 4 - - - 1 - 2.7 4 1200 1000 500 1 147.8

4 4 1000 800 500 1 122.804 4.6 4 1000 800 500 1 122.138 5.4 4 1000 800 450 1 115.27

Figure 4-11: Power consumption LC oscillator vs network resistance and quality factor of the inductor. Rnw stands for network resistance while Q is the quality factor of the inductor For network resistances of 3Ω and 4Ω a current mirror circuit was used.

This had a big impact on the efficiency of the oscillator. For network resistance of

3 and 4 Ω and quality factor of 1.6, there were no oscillations and hence no data

taken. Figure 4-11 illustrates how the power consumption of the oscillator changes

P mW

Q Rnw Ω

- 59 -

for different Q values and network resistances. Clearly the efficiency of the

oscillator improves when the quality factor of the inductor is increased and the

network resistance is decreased. Figures 4-12 and 4-13 show the wave form output

of the conventional inverter driver and the cross-coupled inverter pair oscillator

for which the different readings were taken.

Figure 4-12: Output wave form of the conventional inverter driver at 1GHz

- 60 -

Figure 4-13: Output wave form of the Cross coupled Inverter Pair Oscillator 1GHz

- 61 -

4.5. 2 Inductor Oscillator This oscillator is shown in Figure 4-14 [3], [12], [13],[14]. This oscillator

has a cross-coupled NMOS structure as shown in the figure. It uses two inductors

L0 and L1 as labeled in the figure and parasitic capacitance from the load as part

of the LC circuit. When vout is at its maximum voltage and voutbar is at its

minimum voltage transistor M1 will be turned on and M0 will be turned of. A

series tank circuit is created between inductor L0 and the parasitic load

capacitance that is connected to output vout. The opposite is true when voutbar is

at its maximum and a tank circuit is made with inductor L1 and the parasitic load

capacitance that is connected to output voutbar.

Figure 4-14: 2 Inductor Dual Phase LC Oscillator

- 62 -

4.5.1. Effect of Transistor size on Voltage Swing As with the cross-coupled inverter pair oscillator discussed previously the

voltage swing increases when the transistors are made wider. The different peak to

peak voltages and corresponding power consumptions that occur with different

transistor sizes have been shown in table 4-5 when ideal inductors are used and

further graphically shown in Figure 4-15 and 4-16.

Table 4-5: Transistor sizes vs peak to peak voltage of the signal and power consumption of the Oscillator

wn µm

Voltage Swing mV

Power mW

500 1200 50.06 300 1000 44.03 200 800 36.00

Peak to Peak Voltage vs Normalized Width

750800850900950

100010501100115012001250

1 1.5 2.5

Normalized width of transistors

Pk

to P

k Vo

ltage

V

Figure 4-15: Peak to Peak voltage of the sinusoid as seen at the load vs the normalized transistor width. Normalized width of 1 stands for an NMOS width of 200µm

- 63 -

Power Consumption of the Oscillator vs Normalized Width

30

35

40

45

50

55

1 1.5 2.5

Normalized Width

Pow

er C

onsu

mpt

ion

mW

Figure 4-16: Power consumption of the oscillator vs normalized width of the transistor. Normalized width of 1 stands for a width of 200µm for the NMOS transistor.

4.5.2. Effect of Network resistance on Transistor Sizes As with the cross-coupled inverter pair oscillator, greater network

resistance translates to greater losses in the LC tank circuit. The sizes of the

NMOS transistors have to be increased to compensate for these losses. The

different transistor sizes vs the network resistance, when the voltage swing is fixed

to 1.2V and frequency is fixed to 1GHz, are shown in table 4-6 and Figure 4-17.

Table 4-6: Transistor sizes vs network resistance and power consumption of the oscillator

wn µm

Rnw Ω

Power mW

90 0.5 13.05 150 1 23.03 250 1.5 35.14 350 2 46.29

- 64 -

Normalized Transistor width vs Network resistance

0.000.501.001.502.002.503.003.504.004.50

0.5 1 1.5 2

Network resistance Ω

Norm

aliz

ed tr

ansi

stor

wid

th

Figure 4-17: Effect of change in network resistance on transistor sizes for a fixed voltage swing and frequency. Normalized width of 1 stands for an NMOS width of 90µm

4.5.3. Effect of change in load capacitance and network resistance on the frequency of oscillation

To see the effects of change in load capacitance on the LC oscillator, the

load capacitance has been changed from 5pF to135pF on both phases with an

inductance of 0.78nH. How this change in load capacitance affects the frequency

when the network resistance is changed between 0.01Ω and 3Ω can be seen in

Figure 4-18. The figure shows the normalized load capacitance verses normalized

frequency. The inductor has a value of 0.78nH and has a resistance of 0.41Ω. The

size of the NMOS transistors is 350µm. Voltage at the power supply is 0.5V.

- 65 -

Frequency vs load Capacitance with a resistance of 0.01 to 5 Ohms

0.400

0.900

1.400

1.900

2.400

5 15 25 35 45 55 65 75 85 95 105

Cload pF

Freq

uenc

y

0.01 1 5 3

Figure 4-18: Effect of change in capacitance on the frequency of oscillation with different network resistances

For resistances of 0.01 Ω and 1Ω, the frequency response of the oscillator

to increase in load capacitance is the same. With the resistance of 0.01Ω, the trend

continues until a capacitance of 325pF and with a resistance of 1Ω the trend

continues until a value of 105pF. For resistance value of 3Ω, the frequency

decreases until a maximum load capacitance of 45pF. With a resistance of 5Ω, the

frequency first reduces with the increase in load capacitance until a value of 15pF

and then increases until a capacitance of 45pF after which there are no sustained

oscillations.

Ω

- 66 -

4.5.4. Area of the inductor verses Q of Inductor Table 4-7 and Figure 4-19 show the total area covered by the inductor for

different Q values, for a frequency of approx 1GHz, when a load capacitance of

30pF is present.

Table 4-7: Approximate area covered by the inductors for a given Q value of inductor

Approx Q Area µm2

2.5 125,0003.3 245,0004.2 605,0004.9 720,000

Area vs Approx Q

0100000200000

300000400000500000600000

700000800000

2.8 3.5 4.2 4.9

Q

Are

a (s

quar

e µm

)

Figure 4-19: Approximate area covered by the inductors for a given Q value of inductor

- 67 -

4.5.5. Power Consumption vs Q of the inductor As discussed for the cross-coupled inverter oscillator, power consumption

for a fixed voltage swing and frequency depends mainly on the network resistance,

the amount of load capacitance and the quality of the inductors. For a fixed load

capacitance and network resistance, the power consumption depends on the Q

value of the inductors. Lower Q values mean more losses in the inductor and

hence the power consumption of the oscillator is increased. Table 4-8 illustrates

how the power consumption is affected by the change in Q for inductance and

network resistance. The inductance value varies between 0.7nH to 0.78nH. Table 4-8: The power consumption of the oscillator vs the Quality factor of the inductor

QL

Quality of

Inductor

Rnw Ω Network Res.

wn (µm) width of NMOS

Supply Voltage

V

Power Consumption

mW

2.03 0.01 900 0.6 75.71 2.93 0.01 200 0.6 30.99

3.9 0.01 170 0.5 14.86 4.7 0.01 140 0.5 11.82 5.4 0.01 90 0.5 7.93

2.03 1 1200 0.6 79.71 2.93 1 330 0.6 46.05

3.9 1 200 0.6 34.83 4.7 1 175 0.6 30.23 5.4 1 140 0.6 25.26

2.03 2 1500 0.6 82.38 2.93 2 600 0.6 63.18

3.9 2 310 0.6 51.97 4.7 2 280 0.6 44.47 5.4 2 230 0.6 39.31

2.03 3 - 0.6 - 2.93 3 900 0.6 79.14

3.9 3 530 0.6 65.52 4.7 3 470 0.6 62.88 5.4 3 410 0.6 58.17

2.03 4 - 0.6 - 2.93 4 1000 0.65 101.27

3.9 4 900 0.6 82.92 4.7 4 900 0.58 73.37 5.4 4 720 0.58 70.56

- 68 -

Figure 4-20: Power consumption LC oscillator vs quality factor of the inductor and network resistance. Rnw stands for network resistance while Q is the quality factor of the inductor Figure 4-20 illustrates how the power consumption of the oscillator changes

for different Q values and network resistances. The efficiency of the oscillator

improves when the quality factor of the inductor is increased and the network

resistance is decreased. Figure 4-21 shows the output wave form from the

2inductor oscillator for which the power readings have been taken.

P mW

Q

Rnw Ω

- 69 -

Figure 4-21: Output wave form of the 2Inductor Oscillator at 1GHz

- 70 -

4.6. Comparison The first comparison of the two oscillators indicates how the change in load

capacitance affects the two oscillators when network resistance is changed from

0.01 to 5Ω is present. The load capacitance is changed from 5pF to135pF. Figure

4-22, 4-23, 4-24, 4-25 show the results of the simulations.

Frequrncy vs load Capacitance with a resistance of 0.01 Ohms

0.4000.6000.8001.0001.2001.4001.6001.8002.000

5 15 25 35 45 55 65 75 85 95 105

Cload pF

Freq

uenc

y G

Hz

CCIP2L

Figure 4-22: Effect of change in capacitance on the frequency of oscillation with 0.01Ω resistance. CCIP stands for Cross-coupled inverter pair oscillator and 2L stands for 2 Inductor Oscillator

Frequrncy vs load Capacitance with a resistance of 1 Ohms

0.4000.6000.8001.0001.2001.4001.6001.8002.000

5 15 25 35 45 55 65 75 85 95 105

Cload pF

Freq

uenc

y G

Hz

CCIP2L

Figure 4-23: Effect of change in capacitance on the frequency of oscillation with 1Ω resistance. CCIP stands for Cross-coupled inverter pair oscillator and 2L stands for 2 Inductor Oscillator

- 71 -

Frequrncy vs load Capacitance with a resistance of 3 Ohms

1.100

1.300

1.500

1.700

1.900

2.100

5 15 25 35 45 55 65 75 85 95 105

Cload pF

Freq

uenc

y G

Hz

CCIP2L

Figure 4-24: Effect of change in capacitance on the frequency of oscillation with 3Ω resistance. CCIP stands for Cross-coupled inverter pair oscillator and 2L stands for 2 Inductor Oscillator

Frequrncy vs load Capacitance with a resistance of 5 Ohms

1.3501.4501.5501.6501.7501.8501.9502.0502.150

5 15 25 35 45 55 65 75 85 95 105

Cload pF

Freq

uenc

y G

Hz

CCIP2L

Figure 4-25: Effect of change in capacitance on the frequency of oscillation with 3Ω resistance. CCIP stands for Cross-coupled inverter pair oscillator and 2L stands for 2 Inductor Oscillator.

Figure 4-26 shows how the two oscillators compare in terms of inductor

area coverage vs quality of the inductor. The graph shows that the two inductor

oscillator requires more area for the inductor for the same value of Q as compared

to the cross-coupled inverter pair oscillator.

- 72 -

Inductor Area vs Inductor Q

0100000200000300000400000

500000600000700000800000

2.8 3.5 4.2 4.9

Q

Are

a (s

quar

e µm

)

CCIP2L

Figure 4-26: Approximate area covered by the inductors for a given Q value of inductor. CCIP stands for Cross-coupled inverter pair oscillator and 2L stands for 2 Inductor Oscillator Figures 4-27 to 4-31 show the ratio of the power consumption of the

conventional driver shown in Figure 4-2 to the power consumptions of both LC

oscillators under simulation vs the quality of the inductor for different values of

the network resistance. For network resistances of 3 and 4Ω, a current mirror

circuit such as the one shown in Figure 4-3 has been used for the cross-coupled

inverter pair oscillator to ease transistor sizing. This came at the expense of power

consumption and hence there is a big difference in power consumption of the

2inductor oscillator and the cross-coupled inverter pair oscillator for these

resistance values.

- 73 -

Power consumption of Oscillator vs Q of inductor with 0.01Ohm resistance

0123456789

2 3 4 5

Q

Pc/

Po CCIP2L

Figure 4-27: Ratio of Power consumption of conventional inverter driver to the power consumption of LC oscillator vs quality factor of the inductor when there is 0.01Ω network resistance. CCIP stands for Cross-coupled inverter pair oscillator and 2L stands for 2 Inductor Oscillator. Pc is the power consumption of the conventional driver while Po is for the LC oscillator

Power consumption of Oscillator vs Q of inductor with 1 Ohm resistance

0.4

0.9

1.4

1.9

2.4

2.9

2 3 4 5

Q

Pc/P

o CCIP2L

Figure 4-28: Ratio of Power consumption of conventional inverter driver to the power consumption of LC oscillator vs quality factor of the inductor when there is 1Ω network resistance. CCIP stands for Cross-coupled inverter pair oscillator and 2L stands for 2 Inductor Oscillator. Pc is the power consumption of the conventional driver while Po is for the LC oscillator

- 74 -

Power consumption of Oscillator vs Q of inductor with 2 Ohms resistance

0.4

0.6

0.8

1

1.2

1.4

1.6

2 3 4 5

Q

Pc/P

o CCIP2L

Figure 4-29: Ratio of Power consumption of conventional inverter driver to the power consumption of LC oscillator vs quality factor of the inductor when there is 2Ω network resistance. CCIP stands for Cross-coupled inverter pair oscillator and 2L stands for 2 Inductor Oscillator. Pc is the power consumption of the conventional driver while Po is for the LC oscillator

Power consumption of Oscillator vs Q of inductor with 3 Ohms resistance

0.4

0.5

0.6

0.7

0.8

0.9

1

2 3 4 5

Q

Pc/

Po CCIP

2L

Figure 4-30: Ratio of Power consumption of conventional inverter driver to the power consumption of LC oscillator vs quality factor of the inductor when there is 3Ω network resistance. CCIP stands for Cross-coupled inverter pair oscillator and 2L stands for 2 Inductor Oscillator. Pc is the power consumption of the conventional driver while Po is for the LC oscillator

- 75 -

Power consumption of Oscillator vs Q of inductor with 4 Ohms resistance

00.10.20.30.40.50.60.70.80.9

2 3 4 5

Q

Pc/

Po CCIP2L

Figure 4-31: Ratio of Power consumption of conventional inverter driver to the power consumption of LC oscillator vs quality factor of the inductor when there is 4Ω network resistance. CCIP stands for Cross-coupled inverter pair oscillator and 2L stands for 2 Inductor Oscillator. Pc is the power consumption of the conventional driver while Po is for the LC oscillator

Transistor Sizes vs Network Resistance

0

200

400

600

800

1000

1200

0.01 1 2 3

Network Resistance Ohm

Tran

sist

o W

idth

µm

wp-CCIPwn-CCIPwn-2L

Figure 4-32: Transistor Widths vs the Network Resistance for a Q factor of inductors of 4.6. Figures 4-22 to 4-32 show how the two oscillators compare with each other

in terms of change in load frequency, the inductor area requirements and power

consumption. Figure 4-22 and Figure 4-23 suggest that when the network

resistance is low (0 to 1Ω), the frequency response of both oscillators is similar to

- 76 -

an LC tank circuit. For a load capacitance of 5pF we see that the 2inductor

oscillator is operating at a higher frequency than the cross-coupled inverter

oscillator. This difference is due to the capacitive loading of the PMOS transistors

in the cross coupled inverter oscillator which causes this oscillator to see more

load capacitance than the 2inductor oscillator. This difference in frequency

continues until a load capacitance of 20pF after which the capacitive load of the

PMOS transistor is smaller compared to the load capacitance and hence there is no

significant difference in operation frequency between the two oscillators. Figure 4-

24 shows that for network resistance of 3Ω the operation frequency of the

2inductor oscillator decreases with the increase in load capacitance until a a value

of 45pF after which there are no sustainable oscillations. The operation frequency

of the cross-coupled inverter oscillator decreases with the increase in load

capacitance until a value of 45pF and then increases until a value of 65pF after

which there are no sustainable oscillations. The cross-coupled inverter oscillator

can operate with more load because of the additional gain provided by the PMOS

transistors. Figure 4-25 shows that at 5Ω in the 2inductor oscillator, the frequency

first decreases until a value of 20pF and then increases until a value of 45pF after

which there are no sustainable oscillations. For the cross-coupled inverter

oscillator the frequency decreases with the increase in load capacitance until a

value of 25pF and then increases with the increase in load capacitance until a

value of 2nF. We can also conclude from these figures that as the network

resistance increases there is a larger difference between the operation frequencies

of the oscillators. As the resistance increases the 2inductor oscillator requires more

inductance to match the frequency of the cross-coupled inverter oscillator or

conversely, the cross-coupled inverter oscillator requires lesser inductance to

match the frequency of the 2inductor oscillator.

Figure 4-28 shows that at a network resistance of 1Ω the power efficiency

of the cross-coupled inverter pair oscillator is greater compared to the 2indctor

oscillator. This is because from the AC point of view, the two inductors are in

- 77 -

series with each other and the capacitance. When two schematic π models of the

inductors are placed in series, the effective Q is reduced. This is not the case with

the cross-coupled inverter pair oscillator which has just one inductor and requires

lesser inductance to operate at the same frequency for the same load. At a

resistance of 2Ω in Figure 4-29 we see that the efficiencies of the two oscillators

are equal. The reason for this can be explained with the help of Figure 4-32 which

shows that the size of the transistors in the cross-coupled inverter oscillator at this

resistance value is much larger than the size of the transistors in the 2inductor

oscillator. Since the size of the transistors is much larger, its differential cross-

coupled structure consumes more power than the cross-coupled structure of the

2inductor oscillator. The power consumption of the cross-coupled inverter

oscillator therefore becomes comparable to the 2inductor oscillator. Figures 4-30

and 4-31 show that at higher network resistances there is a big difference between

the performance of the two oscillators because the sizes of the transistors used in

the cross-coupled inverter pair oscillator are much larger than the sizes of the

transistors used in the 2inductor oscillator and a current mirror circuit has to be

used in the cross-coupled inverter pair oscillator to keep the sizes of the PMOS

transistors in check. This however gives a large efficiency penalty as the current

mirror circuit draws a lot of current from the supply. Even with the use of the

current mirror circuit, the sizes of the transistors are quite large. At network

resistances between 3 and 4Ω, the 2inductor oscillator shows much better

performance.

Selection of one oscillator depends highly on the application. Suppose there

are a number of constraints. The area for the inductance is limited to 500,000µm2

(707µm X 707µm). The network resistance is 1Ω. With the given area the highest

Q value of the inductor that can be achieved when a 2Inductor oscillator is used is

approx 4, according to Figure 4-26. Since there are two inductors, they will share

the space that is provided. Compare this to the Q value of the inductor that can be

attained if a Cross-Coupled inverter pair oscillator is used. This is 4.9 according to

- 78 -

Figure 4-26. If we look at Figure 4-28 and at how much power the two oscillators

consume with these Q values we can see that the ratio for the 2 inductor oscillator

is 1.5 while for the cross-coupled inverter oscillator it is 2.3. With this given

situation the cross-coupled inverter oscillator uses 23% less power than the 2

inductor oscillator. Therefore, for these particular constraints the cross-coupled

inverter pair oscillator is more suitable for the application.

- 79 -

5. CONCLUSIONS In the second section a study of on-chip Inductors has been done. Inductors

of many different Q values can be made on-chip. Using wider inductor wires

decreases the series resistance and this has a positive effect on Q. On the other

hand if the inductor wire is too wide, parasitic capacitances begin to increase and

have an adverse effect on Q. Furthermore, if the inductor wire is wider it will

require more Area. Therefore, an inductor has to be made keeping in mind the

required Power Consumption, Available Area and the Oscillation Frequency of

interest. The third section shows a study and comparison of the two oscillators in

terms of effect of change in load capacitance on frequency, the power efficiency of

the two oscillators, the transistor sizes required and the approx area required for

the inductance. Simulation results suggest that for network resistances from 3 to

4Ω the two inductor oscillator is more efficient. Between resistances of 0 and 1Ω

the cross-coupled inverter oscillator is more effecient. We can also conclude that

in order to increase the efficiency of the oscillators compared to a conventional

driver the quality factor of the inductor needs to be maximized and the network

resistance needs to be minimized. Finally, we conclude that the selection of one

oscillator depends on the amount of network resistance and the area available for

the on-chip inductor. For a given area of 500,000µm2 and a fixed network

resistance of 1Ω the cross-coupled inverter pair oscillator is 23% more efficient

than the two inductor oscillator. However for the given inductance area and a

network resistance of 3 to 4Ω the 2 inductor oscillator is much more efficient.

- 80 -

REFERENCES [1] Reinhold Ludwig; Pavel Bretchko, “RF Circuit Design Theory and Applications”, Prentice Hall, 2000 [2] Chan, S.C.; Restle, P.J.; Shepard, K.L; James, N.K.; Franch, R.L.; “A 4.6GHz resonant global clock distribution network”, Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International , 15-19 Feb. 2004 Pages:342 - 343 Vol.1 [3] Drake, A.J.; Nowka, K.J.; Nguyen, T.Y.; Burns, J.L.; Brown, R.B.;” Resonant clocking using distributed parasitic capacitance”,Solid-State Circuits, IEEE Journal of ,Volume: 39 , Issue: 9 , Sept. 2004 Pages:1520 – 1528 [4] Cooke, M.; Mahmoodi-Meimand, H.; Roy, K.;”Energy recovery clocking scheme and flip-flops for ultra low-energy applications”, Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on , 25-27 Aug. 2003 Pages:54 – 59 [5] Thomas H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits”, Cambridge University Press, 1998. [6] Mohan, S.S.; del Mar Hershenson, M,; Boyd, S.P.; Lee, T.H;”Simple accurate expressions for planar spiral inductances”, Solid-State Circuits, IEEE Journal of ,Volume: 34 , Issue: 10 , Oct. 1999 Pages:1419 – 1424 [7] Wang Tao; Wang Yong; Cao Ming; Chen Kangsheng; “A novel technique fast optimizing the layout parameters of planar spiral inductor” ASIC, 2003. Proceedings. 5th International Conference on, Volume: 1 , 21-24 Oct. 2003 Pages:302 - 305 Vol.1 [8] Shwetabh Verma, Jose M. Cruz “On-Chip Inductors and Transformers”, SML Technical Report Series, Sun Microsystems, 1999.

- 81 -

[9] Mostafa, A.H.; El-Gamal, M.N.; Rafla, R.A.; “A Sub-1-V 4-GHz CMOS VCO and a 12.5-GHz oscillator for low-voltage and high-frequency applications” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on], Volume: 48 , Issue: 10 , Oct. 2001 Pages:919 – 926 [10] Samori, C.; Levantino, S.; Lacaita, A.L.;”Integrated LC oscillators for frequency synthesis in wireless applications”, Communications Magazine, IEEE, Volume: 40 , Issue: 5 , May 2002 Pages:166 – 171 [11] Levantino, S.; Samori, C.; Bonfanti, A.; Gierkink, S.L.J.; Lacaita, A.L.; Boccuzzi, V.;”Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion”, Solid-State Circuits, IEEE Journal of , Volume: 37 , Issue: 8 , Aug. 2002 Pages:1003 – 1011 [12] Tiebout, M.; Wohlmuth, H.-D.; Simburger, W.;”A 1 V 51GHz fully-integrated VCO in 0.12 µm CMOS”, Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International , Volume: 1 , 3-7 Feb. 2002 Pages:300 - 468 vol.1 [13] Gabara, T.; Fischer, B.; “Multi-GHz CMOS oscillators”, ASIC Conference and Exhibit, 1994. Proceedings., Seventh Annual IEEE International , 19-23 Sept. 1994 Pages:41 – 43 [14] Hsiao, C.C.; Kuo, C.W.; Chan, Y.J.;”6.8 GHz monolithic oscillator fabricated by 0.35 µm CMOS technologies”, Electronics Letters, Volume: 36, Issue: 23 , 9 Nov. 2000 Pages:1927 – 1928 [15] Yue, C.P.; Wong, S.S.;”On-chip spiral inductors with patterned ground shields for Si-based RF ICs”, Solid-State Circuits, IEEE Journal of, Volume: 33, Issue: 5, May 1998 Pages: 743 – 752 [16] Yue, C.P.; Ryu, C.; Lau, J.; Lee, T.H.; Wong, S.S.;”A physical model for planar spiral inductors on silicon”, Electron Devices Meeting, 1996., International, 8-11 Dec. 1996 Pages:155 - 158

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