final presentation: april 25 th, 2005 seri abd rauf fatima boujarwah juan chen liyana sharipp arti...

Final Presentation: April 25th, 2005

Seri Abd RaufFatima BoujarwahJuan ChenLiyana SharippArti Thumar

18-525: Integrated Circuit Design Project, Spring 2005

Project Manager: Bobby Colyer

Overall Design Goal: Implementing Noise Canceling Algorithm in Hardware


Got an iPod?

Can you hear the noise?

Want to know why?

Cell phone?

Car? PDA?

No?

http://www.palmone.com/us/products/handhelds/tungsten-e2/

•Most devices that we use throughout the day have a noise canceling component

–Audio

–Visual

–Motion


1.The BIG Picture2.Marketing Potential3.Behavioral/ Algorithm Description4.Design Process5.Floorplan Evolution6.Layout7.Verification8.Challenges9.Chip Specifications10.Finale


1.The BIG Picture2.Marketing Potential3.Behavioral/ Algorithm Description4.Design Process5.Floorplan Evolution6.Layouts7.Verification8.Challenges9.Chip Specifications10.Finale



• Also known as the Intelligent Microsurgical Instrument Project • A research done here at CMU, led by Prof Riviere and Dean Khosla

• Project Goal: To enhance accuracy in microsurgery

• Problem Definition:

• Physiological Tremor • Non-tremulous errors

• Method

• Weighted Fourier Linear Combiner (WFLC) for noise canceling purposes

• How does this help solve the problems?

WFLC

Revised Flow Chart Original Flow Chart


1.The BIG Picture

2.Marketing Potential3.Behavioral/ Algorithm Description4.Design Process5.Floorplan Evolution6.Layouts7.Verification8.Challenges9.Chip Specifications10.Finale



Microsurgical Instruments Human-Computer Interfaces

Vehicle ManeuveringHearing Aid

1.The BIG Picture2.Marketing Potential

3.Behavioral/ Algorithm Description4.Design Process5.Floorplan Evolution6.Layouts7.Verification8.Challenges9.Chip Specifications10.Finale


• Goal: To minimize noise• Algorithm: Based on adaptive filtering

depending on signal weights• Pseudo-code:

i) Take the input signal and model it using Fourier Transform

ii) For each sample, model it by approximating the weight constant and feeding it back to the next sample

iii) Each sample model is then subtracted from the original input signal to monitor the error

Output

w1

+

-

Sin(sumw0)

Integration Block

Integrator Block

Cos(sumw0) w2

Input

LMS

w0

Error

Generate Adaptive Weights to

Calculate Output

Take Fourier Transform of Input Signal using previous

Error

Sample Output Subtracted from Input Signal to Generate Current

Error

Repeat the Process for the next Sample Input

counter ROM

SineConverter

CosineConverter

0

1

0

1

FPMult1

FPMult2

0

1

0

1

0

1

FPAdd

FPAdd/Sub

Datum

Offset

w1

Out

FPSub e

AddOne

w2

mu

FPMult3


• The BIG Picture• Marketing Potential• Behavioral/ Algorithm Description

• Design Process• Floorplan Evolution• Layouts• Verification• Challenges• Chip Specifications• Finale


Floating Point Multipliers

• Array vs Wallace tree structures for power saving


• Wallace + Booth vs Wallace for better layout design

– saved 2K transistors – inserted smaller modules in top level to fill up the white space

• Buffered each bit of the output


Floating Point Adders• Ripple Carry Adder vs. Carry Look-ahead Adder

• Mirror Adder vs. Mux-based AdderMirror Adder Mux-based Adder

# of transistors 24 18

Area 11.52 x 5.4 15.16 x 5.62

Output signal Stable Unstable


• Changed the general FPAdd/Sub (with input signal ‘sub’) for all the three adders to:– FPAdd for the top adder– FPSub for the middle adder– FPAddSub for the bottom adder

• Barrel shifter vs. Logarithmic shifter– Barrel shifter is used during normalizing – consumes less

power– Log shifter is used during denormalizing – easier to extract

the sticky bits

• Changed Ripple Borrow Subtractor to Ripple Carry Adder with Carry In = 1

Eliminate ‘sub’ and minimize the logic for sign bit


MUX and Register• Designed MUXes based on where the inputs and

outputs are in the top level floorplan

• Designed registers based on their functionalities and inputs/outputs positions– Mu, Offset, Datum: Negative Edge Triggered DFF– w1, w2, Out, e : Clear-Alternate Enabled DFF


1.The BIG Picture2.Marketing Potential3.Behavioral/ Algorithm Description4.Design Process

5.Floorplan Evolution6.Layouts7.Verification8.Challenges9.Chip Specifications10.Finale



5 Floating Point Adders?


Need better routing channels

Need to redesign muxes to avoid congestions

Move this there…


And we thought this would be our final floorplan…


The multipliers turned out to be smaller!

1.The BIG Picture2.Marketing Potential3.Behavioral/ Algorithm Description4.Design Process5.Floorplan Evolution

6.Layouts7.Verification8.Challenges9.Chip Specifications10.Finale



Denormalizing

Normalizing

Output Logic

Add/Sub

Rounding Unit

Wallace Tree Multiplier

Alternator

Buffers


1.The BIG Picture2.Marketing Potential3.Behavioral/ Algorithm Description4.Design Process5.Floorplan Evolution6.Layouts

7.Verification8.Challenges9.Chip Specifications10.Finale


*Test Files are from Robot Assisted Needle Insertion Research Conducted by Professor Cameron Riviere

These inputs approximate to:

Constants:MU = 0.1OFFSET = 10

Inputs:DATUM =

10.34058900 10.42289600 10.49148600 10.59208400 10.67439200 10.72926400 10.77041800 10.78870800 10.78870800 10.74755400


Behavioral results Structural results

Output

Error

Similar Plots: Slight Differences due to 16-bit Floating Point Units.


**First three test vectors verify correctness of the layout

Output Bits 0-7: 01110111

Clean Output Signals: 1.8V


• The BIG Picture• Marketing Potential• Behavioral/ Algorithm Description• Design Process• Floorplan Evolution• Layouts• Verification

• Challenges• Chip Specifications• Finale



• Transistor Count– Solution: Reused hardware

• Hardware Sharing– Caused timing issue– Split the circuit into two cycles

• Sufficient Signal Strength– Improved Vdd and Gnd rail connections– Buffering techniques

• The BIG Picture• Marketing Potential• Behavioral/ Algorithm Description• Design Process• Floorplan Evolution• Layouts• Verification• Challenges

• Chip Specifications• Finale


Size of Design 364.275µm x 300.96µm

Aspect Ratio 1:1.21

Transistor Count 25385

Density 0.232 transistors/µ2

Clock Frequency 50KHz

Power 2.507mW

Pin Count 84 pins


Vdd!

Gnd!

In/Out

In/Out

Datum<15:0>

Mu<15:0>

Offset<15:0>

Clk

Reset

In

In

In

In

In

Out<15:0>

e<15:0>

Out

Out

Total # of Pins: 84


1.The BIG Picture2.Marketing Potential3.Behavioral/ Algorithm Description4.Design Process5.Floorplan Evolution6.Layouts7.Verification8.Challenges9.Chip Specifications

10.Finale



We will never be the same…

• Everyone must have a cell phone with a good noise canceling function

• Shopping is not a priority anymore. Metal 3 is not ‘in’ this season

• The early bird gets the worm…but can we get up? (hmmm, did we ever get to sleep?

• The Butterfly effect applies to EVERYTHING, including…floorplannig

• There are hundreds of applications for noise cancellation devices in our everyday lives

• Such algorithms are crucial in improving the quality of lives of many people


So, in conclusion, our chip:

Is universally effective and efficient in canceling noise

Can be used to cancel all types of noise

Will save lives

• http://www-2.cs.cmu.edu/~micron/index.htm• http://www-2.cs.cmu.edu/~camr/research.html• http://www.ri.cmu.edu/projects/project_32.html• http://www.eecs.berkeley.edu/~mounir/ee241/ee241.part2.pdf• http://www.ece.cmu.edu/~lowpower/cicc96.pdf• http://www.eecs.berkeley.edu/~mounir/ee241/

ee241_final_report.pdf• C. N. Riviere, “Predicting Respiratory Motion for Active

Canceling During Percutaneous Needle Insertion”, Oct. 2001• http://www.whynot.net/view_idea.php?id=1579• www.owlnet.rice.edu/~elec301/Projects00/site/design.html


final presentation: april 25 th, 2005 seri abd rauf fatima boujarwah juan chen liyana sharipp arti...

Documents

error slide

sample input slide

hardware slide

project manager

noise algorithm

dean khosla project

original input signal

sample iiieach sample