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ELECTRICALVALIDATION FOR

DDR IO INTERFACE

Presented byDipak Prakash Bankar

09VL07F

5/20/2011 1M. Tech. VLSI Design NITK Surathkal.

Prof. M. S. Bhat

NITK Surathkal

Under the Guidance

ofBhide Amruta A

Intel Technology India Pvt. Ltd.


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5/20/2011 2M. Tech. VLSI Design NITK Surathkal.

Agenda :

What is EV In general?

Importance.

What is DDR Interface?

Brief About DDR RAM.

Evolution Of DDR.

DDR3 Signals.

DDR3 protocol.

EV for DDR.

Flyby Topology.

Delay Locked Loop

Characterization of DLL.

References.


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5/20/2011 M. Tech. VLSI Design NITK Surathkal. 3

What is EV in general?

It comes under post silicon Validation. Done over Process, Voltage and

Temperature variations.

Done at Platform Level Component Level


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Importance.


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What is DDR interface?


Memory

Slots

PCIe/AG

P(Graphi

cs)

APM/

ACPI

PCI/

PCIe

Bus

AC97/HD

(AUDIO)

SATA/

USB/

LAN

PORTS

HDMIOther

Devices

DDRInterface


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DDR

Slots

PCIe/AG

P(Graphics)

APM/

ACPI

PCI/

PCIe

Bus

AC97/HD

(AUDIO)

SATA/

USB/

LAN

PORTS

HDMIOther

Devices

Two Dieone

package

DDRInterface


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DDR Slots

PCIe/AG

P(Graphics)

APM/

ACPI

PCI/

PCIe

Bus

SATA/

USB/

LAN

PORT

S

HDMI

Other

Devices

DDRInterface


VGA


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Evolution of DDR. DDR3 Signals.

DDR3 protocol.

READWRITE


Brief about DDR(RAM).


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Evolved from SDR


Evolution of DDR.


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DDR1.

Additional

Stubs andStub Lengths

Evolution of DDR.


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DDR2.

Additional

Stubs andStub Lengths

Evolution of DDR.


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DDR3.

Evolution of DDR.


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DDR3 Signals Groups.

Command group WE# :Write Enable RAS# : Row Address Select

CAS# : Column Address Select


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Clock CK/CK# :- Differential.

- Free running.

- all data, address, command and control signals are sampled on

the crossing of clock.


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Control group CKE : Clock Enable- Activate and deactivate internal clock signals and device input

buffers and output drivers.

- CKE LOW provides Pre-charge Power-Down and Self

Refresh operation.

CS : Chip Select

- CS provides for external

Rank selection on systems with multiple Ranks.

- All commands are masked when CS is registered HIGH.

ODT : On Die Termination- ODT (registered HIGH) enables termination resistance internal to

the DDR3 SDRAM.

- Allows the DRAM to turn on/off termination resistance for each DQ,

DQS, DQS#.


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Data group DQS/DQS# [7:0] : Data Strobe- Differential.

- Acts as clock for data.

- Starts from Tristate.

DQ[63:0]- Single ended Bi-directional.

- Center aligned w.r.t. DQS during write.

- Edge aligned w.r.t. DQS during read.

- 1 DQS is associated with each 8-bit data(DQ)

DM[7:0] :Write Data Mask

- 1 for each 8-bit data (DQ).


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DDR3 Protocol.

READ


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EV For DDR.

Platform Level - Signal IntegrityAddresses two concerns in the electrical design aspects

- the timing and

- the quality of the signal

The goal of signal integrity analysis is to ensure reliable high-speed datatransmission.


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EV For DDR.

Platform Level - Signal IntegrityMain issues of SI

Reflection Noise Due to impedance mismatch, stubs, vias and other interconnectdiscontinuities.

Crosstalk Noise Due to electromagnetic coupling between signal traces andvias.

Power/Ground Noise Due to paracitic of the power/ground delivery system duringdrivers simultaneous switching output (SSO). It is sometimes also

called Ground Bounce, Delta-I Noise or Simultaneous SwitchingNoise (SSN).


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EV for DDR.

Platform Level - Signal Integrity1. Clk to DQS Skew

2. Clk VIX

3. Clock Jitter characterization

4. Dq-Dqs timing

5. Clk-Control timing

6. Clk-Command timing


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EV for DDR.

Platform Level - Signal Integrity1. Clk to DQS Skew


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EV for DDR.

Platform Level - Signal Integrity2. Clk VIX


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EV for DDR.

Platform Level - Signal Integrity2. Clk VIX


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EV for DDR.

Platform Level - Signal Integrity4. Dq-Dqs timing


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EV for DDR.

Platform Level - Signal Integrity5. Clk-Control(CS#) timing


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EV for DDR.

Platform Level - Signal Integrity6. Clk-Command (WE#) timing


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EV for DDR.

Component Level Characterization Of AC timings

- Slew Rate

- Duty Cycle- Noise Margins

- Set up and Hold check


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EV For DDR.

Process Temperature

(C)

Voltage

(V)

Board Component (Processor)

LOW-Z Slow Low Low

High-Z Fast High High

Typical typical Typical Typical


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Flyby topology.


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Flyby topology.

Clock gets skewed

DQS should be skewed

accordingly

Uses programmable Delay

element known as Delay LockedLoop(DLL).


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Delay Locked Loop(DLL)

Phase

Detector Control

Delay Line

Fast/Slow

Clk in


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Characterization of DLL(My

Work). Code Vs Delay

0

100

200

300

400

500

600

700

800

0 10 20 30 40 50 60 70

Code vs Delay


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DNL

Characterization of DLL.

-15

-10

-5

0

5

10

15

0 10 20 30 40 50 60 70


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Characterization of DLL. INL

-30

-25

-20

-15

-10

-5

0

5

10

0 10 20 30 40 50 60 70


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ReferencesJEDEC

www.csee.umbc.edu/research/vlsi/reports/si_chapter.pdfClocking in Modern VLSI System by Thucydides Xanthopoulos, Spinger.

Intel Internal Reference Documents


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