figure 4–1 application of commutative law of...
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![Page 1: Figure 4–1 Application of commutative law of addition.epsem.upc.edu/~jesusv/cap_4_algebra_boole_B_2p.pdf · Title: Microsoft PowerPoint - algebra_boole_4_B.ppt Author: jesse Created](https://reader034.vdocuments.us/reader034/viewer/2022042022/5e7a5cc86d209472ee65e019/html5/thumbnails/1.jpg)
Figure 4–1 Application of commutative law of addition.
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 4–2 Application of commutative law of multiplication.
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 4–3 Application of associative law of addition. Open file F04-03 to verify.
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 4–4 Application of associative law of multiplication. Open file F04-04 to verify.
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 4–5 Application of distributive law. Open file F04-05 to verify.
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 4–6
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 4–7
Thomas L. Floyd
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Figure 4–8
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Figure 4–9
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Digital Fundamentals, 9e
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Figure 4–10
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 4–11
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Digital Fundamentals, 9e
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Figure 4–12
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 4–13
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Digital Fundamentals, 9e
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Figure 4–14
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Digital Fundamentals, 9e
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Figure 4–15 Gate equivalencies and the corresponding truth tables that illustrate DeMorgan’s theorems. Notice the equality of the two
output columns in each table. This shows that the equivalent gates perform the same logic function.
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Digital Fundamentals, 9e
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Figure 4–16 A logic circuit showing the development of the Boolean expression for the output.
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Figure 4–17 Gate circuits for Example 4–8. Open file F04-17 to verify equivalency.
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Digital Fundamentals, 9e
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Figure 4–18 Implementation of the SOP expression AB + BCD + AC.
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Digital Fundamentals, 9e
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Figure 4–19 This NAND/NAND implementation is equivalent to the AND/OR in Figure 4–18.
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Figure 4–20 Implementation of the POS expression (A + B)(B + C + D)(A + C).
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 4–21 A 3-variable Karnaugh map showing product terms.
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Digital Fundamentals, 9e
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Figure 4–22 A 4-variable Karnaugh map.
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 4–23 Adjacent cells on a Karnaugh map are those that differ by only one variable. Arrows point between adjacent cells.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
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Figure 4–24 Example of mapping a standard SOP expression.
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Digital Fundamentals, 9e
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Figure 4–25
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
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Figure 4–26
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Digital Fundamentals, 9e
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Figure 4–27
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
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Figure 4–28
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
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Figure 4–29
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
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Figure 4–30
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Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
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Figure 4–31
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
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Figure 4–32
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 4–33
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
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Figure 4–34
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Digital Fundamentals, 9e
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Figure 4–35 Example of mapping directly from a truth table to a Karnaugh map.
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Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
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Figure 4–36 Example of the use of “don’t care” conditions to simplify an expression.
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Figure 4–37 Example of mapping a standard POS expression.
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Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
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Figure 4–38
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Digital Fundamentals, 9e
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Figure 4–39
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Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
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Figure 4–40
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Digital Fundamentals, 9e
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Figure 4–41
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Digital Fundamentals, 9e
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Figure 4–42 A 5-variable Karnaugh map.
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Digital Fundamentals, 9e
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Figure 4–43 Illustration of groupings of 1s in adjacent cells of a 5-variable map.
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Figure 4–44
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Digital Fundamentals, 9e
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Figure 4–45 A VHDL program for a 2-input AND gate.
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Digital Fundamentals, 9e
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Figure 4–46
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Digital Fundamentals, 9e
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Figure 4–47 Seven-segment display format showing arrangement of segments.
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Digital Fundamentals, 9e
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Figure 4–48 Display of decimal digits with a 7-segment device.
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Digital Fundamentals, 9e
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Figure 4–49 Arrangements of 7-segment LED displays.
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 4–50 Block diagram of 7-segment logic and display.
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 4–51 Karnaugh map minimization of the segment-a logic expression.
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 4–52 The minimum logic implementation for segment a of the 7-segment display.
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Figure 4–53
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
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Figure 4–54
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 4–55
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Figure 4–56
Thomas L. Floyd
Digital Fundamentals, 9e
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Figure 4–57
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Figure 4–58
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Figure 4–59
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Figure 4–60
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Figure 4–61
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Figure 4–62
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Figure 4–63
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Figure 4–64
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Figure 4–65
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Figure 4–66
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