1 Fig. 1 Kuo et al.

p-Si substrate

Si buffer layer 50 nm

Si spacer 60 nm

Ge quantum dot

Ge wetting layer

100 nm Si cap

Pt or AlLPD oxide

(a) (b)

2

0 1 2 310-12

1x10-10

1x10-8

1x10-6

1x10-4

1x10-2

1x100

Al Ge QD

Pt P-Si

Pt Ge QD

Al P-Si

LPD-SiO2 25A

Cu

rren

t (A

)

Gate Voltage (V)Fig. 2 . Kuo et al.

3 Fig. 3 . Kuo et al.

Pt

4.7 eVAl3.15 eV

5.85 eV4.3 eV

3.2 eV

4.7 eV

EF

(a) (b)

3.2 eV

4.7 eV

Pt

4.7 eV

4.3 eV

EF

4

-8 -6 -4 -2 010-14

10-12

1x10-10

1x10-8

1x10-6

1x10-4

1x10-2 Pt gate

C

urr

ent

(A)

Gate Voltage (V)

Bulk pSi 300K Bulk pSi 40K SiGe QD 300K SiGe QD 40K

Fig. 4 . Kuo et al.

5

-80 -60 -40 -20 0 20 40 60 80 100 120

-4

-2

0

2

4

6

8 Pt gate

4.7 eV

3.2 eV

4.3 eV

4.7 eV

Efm

T=40KVg=-4V

En

erg

y

Position (nm)Fig. 5 . Kuo et al.

6

Schottky diode

7

TEM of epi Ge before PMA :

After PMA :

Pt Germanide

Ref :IEEE ELECTRON DEVICE LETTERS

JohnY. Spann, Student Member, IEEE, Robert A. Anderson, Student Member, IEEE, Trevor J. Thornton, Member, IEEE,Gari Harris, Member, IEEE, Shawn G. Thomas, Member, IEEE, and Clarence Tracy

32 Å

91 Å

79 Å125 Å

175Å

16 Å43 Å

29 Å

8

Pt SB w/ epi Ge/Si From MinHung

9

EFn

EFm N-type Si

EFnEFm

N-type Si

kT

qVwheneeTAeeTAJ kT

qVkTBnqkT

qVkTBnq 3

~]1[

Emission" Thermionic" From

)/(2*)/(2* ))(

ln(2*

sBn J

TSiorGeA

q

kT

10

kT

qVwheneeTAeeTAJ kT

qVkTBnqkT

qVkTBnq 3

~]1[

Emission" Thermionic" From

)/(2*)/(2* ))(

ln(2*

sBn J

TSiorGeA

q

kT

0.00 0.04 0.08 0.12 0.16 0.201E-8

1E-7

1E-6

1E-5

1E-4

1E-3

0.01

0.1

1

10

100

Bulk nSiepi nGe

Bulk nGe

6.95e-71.93e-6

0.00185

J

Vg (V)

nSi FBn 0.81 eV nGe FBn 0.59 eV N2679 FBn 0.77 eV

0.00 0.04 0.08 0.12 0.16 0.20

0

1

2

3

4

5

n-id

eality

11

0.00 -0.04 -0.08 -0.12 -0.16 -0.201E-8

1E-7

1E-6

1E-5

1E-4

1E-3

0.01

0.1

1

5.48373333e-7

2.770155e-6

0.00262312

J

Vg (Reverse bias)

Bulk nSi FBn 0.82 eV Bulk nGe FBn 0.58 eV epi nGe N2679 FBn 0.76 eV

Calculating ΦBn by Reverse current :

Sze : ref )kT

qexp(-TA

/3

Bn2*

qkTVforJJ RSR

12

I-V curves

-3 -2 -1 0 1 2 31E-8

1E-7

1E-6

1E-5

1E-4

1E-3

0.01

0.1

1

10

100

epi Ge

nGe

nSi

J (A

/cm

2 )

Vg (V)

nSi nGe epi Ge

Thermionic emission

V/cm104 4Thermionic-field emission (Tunneling)

thermionic emission

tunneling current

13

Thermionic emission Thermionic-field emission (Tunneling)

V/cm104 4

nSi E-field~ 2e4 V/cm Epi Ge E-field~ 3e6 V/cm

From Simulation :

14

C-V calibration :

C R

Cp

Rp

Rs

22222

2

222

222

1

1

1

1

1

)1(

pp

p

pp

pp

pp

s

pp

ppps

RCCC

RC

RC

C

RC

RpRR

C

jR

RC

RCjRR

2

4

C 1

22

2

p22

p

pp

p

RCC

RCCC由

-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0

0.0

1.0x10-7

2.0x10-7

3.0x10-7

4.0x10-7

5.0x10-7

6.0x10-7

C (

F/c

m2 )

Vg (volt)

C100K C500K

-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0

0.0

1.0x10-7

2.0x10-7

3.0x10-7

4.0x10-7

5.0x10-7

6.0x10-7

after calibration

2679N die1

So I just show the C-V before -2V for epi Ge with cap Pt SBD.

epi Ge with cap :

From I-V

15

-2.0 -1.5 -1.0 -0.5 0.00.00E+000

5.00E-008

1.00E-007

1.50E-007

2.00E-007

2.50E-007

3.00E-007

Pt SBD

C (

F/c

m2 )

Vg (volt) - reverse bias

NSi epi Ge with cap epi Ge w/o cap

SBD C-V :

Epi Ge with cap for SBD has higher C than Bulk nSi and epi Ge w/o cap.

EFn

EFm N-type Si

16

Floating gate Memory :

Flating gate

Control gate

Tunnel Oxide

Interpoly Dielectric

SourceDrain

p-substrate

Leakage path

Nano-crystals memory

(Freescale) :

Source Drain

Gate

Control Oxide

tunnel oxide

nano-crystals

Leakage path

Smaller dot size for scaling.Scaling (SiO2 gap between dots must exceed 5 nm)

Charge loss in full floating gate. Thick tunnel oxide.Trade-off between erase speed and tunnel oxide thickness – charge leaks off from the floating gate.The reliability issue when scaled down to deep submicron.

Disadvantage :

17

ConventionalSONOS(15Å~30 Å)

NROM(>40 Å)

Bit-per-cell 1 bit/cell 2 bits/cell

Program FN CHE

Erase FN BTBT

Trap Memory

18

Advantage : Trap size = atom for scaling

∆VT can be large if trap density is height

After annealing, Si implanted into the SiO2 separates from the oxide phase and form the Si-NCs.

Trap Memory :

Oxide

Substrate

Metal

defect

implantation

19

Schematic energy band diagram under program/erase

oo

Ev

Ev

Ec

Ec

Eraseprogram

JelectronJ

electron

Jhole

Jhole

Al2O

3SiO2

Al2O

3

p-Si SiO2 HfO

2 high-p-Si SiO

2 HfO

2 high-

SiO2

TaN

TaN

Program/erase performance is enhanced using high-k blocking oxide.

20

TEM characteristics

All high-k films are deposited by ALD.

After annealing treatment (1000oC, 10s) in N2 ambient, HfAlO

film shows partial crystalline, while HfO2 film shows fully

crystalline. The Al2O3 film shows also partial crystalline.

p-SiSiO2~3.6 nm

Al gate

Al2O3~10 nm

HfO2~5.2 nm

10 nm

Glue

Al2O3~10nm

SiO2~3nm

p-Si

HfAlO~10nm

21

C-V hysteresis memory window

-2 0 2 4 60

1

2

3

memory window ~5.7V

Cap

acit

ance

(fF

/m

2 )

Gate voltage (V)

sweeping voltage: 3V 12V

Structure:

SiO2(3nm)/HfO2(10nm)/Al2O3(10nm)

Al gate electrode

Frequency: 100kHz

Ramp rate: 0.1V/s

A good C-V hysteresis memory window of high-k charge trapping layers is observed with high gate voltage. The memory window is slightly lower (7-8V@Vg=15V) as compared with

reported data (~10V@Vg=12V) on TaN/AlLaO3(12nm)/AlGaN(10nm)/SiO2

(2.7nm)/p-Si [A. Chin et al., 2005 IEDM Tech. Dig. P. 165].