field programmable gate array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-sysarc2011... ·...
TRANSCRIPT
![Page 1: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/1.jpg)
12011/12/12
Field Programmable Gate Array
![Page 2: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/2.jpg)
22011/12/12
What is FPGA?
![Page 3: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/3.jpg)
XGP Simulator
2011/12/123
![Page 4: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/4.jpg)
42011/12/12
FPGAProgrammable (= reconfigurable) Digital SystemComponent
Basic componentsCombinational logicsFlip Flops
Macro componentsMultiplier ( large combinational logic)Random Access Memory (Large Density)Read Only memory (Large Density)CPU
Programmable InterconnectionProgrammable Input/Output circuitProgrammable Clock Generator
![Page 5: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/5.jpg)
52011/12/12
What is Combinational Logic?
CLABCD
f
g
A, B, C, D, f, g are all binary signal.
If output f, g are function of only inputs (A, B, C, D) then the circuit is combinational circuit.In another word, output signal is determined by only the combination of input signals.
f = func1(A, B, C, D)g = func2(A, B, C, D)
Combinational logic does NOT include memories such as Flip-Flops.Combinational logic can be constructed by just primitive gates such as NOT, NAND, NOR, etc. (But no feedback loop)
![Page 6: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/6.jpg)
62011/12/12
Combinational Logic realization - gates -
There is no signal loop in the circuit.In combinational logic, signal loop is prohibited since the loop makes states (Memory).Function is not configurable.
![Page 7: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/7.jpg)
72011/12/12
Combinational Logic realization - Table -
TRUTH TABLE
A B C f
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
A
B
C
0
0
0
0
0
0
1
1
f
Decoder
• Function is configurable by storing the TABLE values.
![Page 8: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/8.jpg)
82011/12/12
Clocked D LATCH
1 bit memory by NOR cross-loopWhen CLK=1, Q = D, /Q=not(D)When CLK=0, Q holds previous data.
D
CLK
Q
Q
Q
Q
When CLK=‘1’
D Q
Q
When CLK=‘0’
D Q
CLKCIRCUIT SYMBOL:
![Page 9: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/9.jpg)
92011/12/12
Master-Slave D Flip-Flop
2 LATCHES in seriesStill work as 1 bit memoryCLK edge Trigger OperationMost commonly used memory element in the state-of-the-art synchronous Digital Design.Q only changes CLK edge (once in one cycle).
D Q
D Q
CLK
D Q
CLK
CLK
D Q
CIRCUIT SYMBOL:
CLK
D
Q 1 1 0 1 0
![Page 10: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/10.jpg)
102011/12/12
Digital System is just FF + CLs
FPGA supports such digital circuit with configurability.FPGA’s basic element
CLD Q
D Q
D Q
D Q
CL
CLD Q
D QCL
![Page 11: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/11.jpg)
112011/12/12
Example of Circuit Synthesis
![Page 12: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/12.jpg)
122011/12/12
XILINX FPGA
Field Programmable Gate Array
![Page 13: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/13.jpg)
132011/12/12
XILINX XC3000 Family I/OElectronic Static Discharge ProtectionCMOS, TTL inputRegistered /Non Registered I/O
![Page 14: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/14.jpg)
142011/12/12
XILINX XC3000 Family CLBCLB: Configurable Logic BlockLook-up table for combinational logicD-Flip-FlopsLook-up Table = RAM
![Page 15: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/15.jpg)
152011/12/12
XILINX XC4000 Family CLBTwo Stage Look-up Table
![Page 16: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/16.jpg)
162011/12/12
XILINX VIRTEX FAMILY ARCHITECTURE
CLB: Configurable Logic BlockMany 4Kbit RAM BLOCK RAMDLL (Delay-Locked Loops) to provide controlled-delay clock networksMultiplier (18b x 18b) Macro also supported (not in figure)
![Page 17: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/17.jpg)
172011/12/12
XILINX VIRTEX FAMILY CLBCLB: Configurable Logic BlockMany 4Kbit RAM BLOCK RAMDLL (Delay-Locked Loops) to provide controlled-delay clock networks
![Page 18: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/18.jpg)
182011/12/12
XILINX VIRTEX FAMILY I/OElectronic Static Discharge ProtectionCMOS, TTL inputRegistered /Non Registered I/O
![Page 19: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/19.jpg)
192011/12/12
ALTERA CPLD
Complex Programmable Logic Devices
Altera uses less routing resource than XilinxAltera’s Logic Array Block (LAB) is more complex than Xilinx’s CLBs. Then fewer LABs in on chip than Xilinx’s CLBs.
![Page 20: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/20.jpg)
202011/12/12
ALTERA FLEX8000 ARCHITECUREEach LAB has eight LEs (Logic Elements) .
![Page 21: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/21.jpg)
212011/12/12
ALTERA FLEX8000 Logic Element (LE)
CARRY, CASCADE signals
![Page 22: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/22.jpg)
222011/12/12
ALTERA APEX 20K ARCHITECTURE
MANY RAMsLarge Number Input combinational logic such as MultiplierPhase Locked Loop for Advanced Clock generation
![Page 23: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/23.jpg)
232011/12/12
How to Design your Digital Systemusing Hard-Macro Blocks
Your Circuit
RAM
I/O circuit
ROM
Multiplier
CPU
RAM
ROM
White Blocks might be available (Hardware pre-designed Blocks)
SoftWarefor
CPU
![Page 24: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/24.jpg)
242011/12/12
Hardware Description Languages (HDLs)
HDL is a software programming language used to model the intended operation of a piece of hardware.Two level of modeling
Abstract behavior modelingHardware structure modeling: Input to Circuit Synthesis
Two kinds of LanguageVHDL: Very High Speed Integrated Circuit hardware description language
Similar to Pascal Programming languageVerilog HDL:
Similar to C Programming language
![Page 25: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/25.jpg)
252011/12/12
HALF_ADDER example
library IEEE;use IEEE.std_logic_1164.all;
entity HALF_ADDER isport ( A, B : in std_logic;
S, C : out std_logic );end HALF_ADDER;
architecture STRUCTURE of HALF_ADDER isbegin
S <= A xor B;C <= A and B;
end STRUCTURE;
module HALF_ADDER (A, B,S, C
);
input A, B;output S, C;
assign S = A ^ B;assign C = A & B;
endmodule
VHDL Verilog HDL
![Page 26: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/26.jpg)
262011/12/12
Moving Average Filter by VHDLlibrary IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_ARITH.all;
entity AVG4 isport(CLK : in std_logic;
FMINPUT : in std_logic_vector(7 downto 0);AVGOUT : out std_logic_vector(7 downto 0));
end AVG4;
architecture RTL of AVG4 is
signal FF1, FF2, FF3, FF4 : std_logic_vector(7 downto 0);signal SUM : std_logic_vector(9 downto 0);
begin
-- SHIFT REGISTERprocess(CLK) beginif (CLK'event and CLK = '1') then
FF1 <= FMINPUT;FF2 <= FF1;FF3 <= FF2;FF4 <= FF3;
end if;end process;
-- SUMSUM <=signed(FF1(7)&FF1(7)&FF1)+signed(FF2(7)&FF2(7)&FF2)
+signed(FF3(7)&FF3(7)&FF3)+signed(FF4(7)&FF4(7)&FF4);
-- DIVIDE BY 4 (SHIFT 2 bit), OUTPUT REGISTERprocess(CLK) beginif (CLK'event and CLK='1') then
AVGOUT <= SUM(9 downto 2);end if;
end process;
end RTL;
![Page 27: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/27.jpg)
272011/12/12
Simulated Waveform
![Page 28: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/28.jpg)
282011/12/12
Synthesized Circuit
![Page 29: Field Programmable Gate Array - ie.u-ryukyu.ac.jp › ~wada › system11 › 60-SYSARC2011... · Field Programmable Gate Array. 2011/12/12 13 XILINX XC3000 Family I/O](https://reader033.vdocuments.us/reader033/viewer/2022060423/5f19ba59a6b0b957e67c7a22/html5/thumbnails/29.jpg)
292011/12/12
XILINX VP70 FLOORPLAN