Solid-State Electronics 95 (2014) 36–41

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Solid-State Electronics

journal homepage: www.elsevier .com/locate /sse

Field controlled RF Graphene FETs with improved high frequencyperformance

http://dx.doi.org/10.1016/j.sse.2014.03.0030038-1101/� 2014 Elsevier Ltd. All rights reserved.

⇑ Corresponding author. Tel.: +1 305 348 3016.E-mail address: npala@fiu.edu (N. Pala).

C. Al-Amin, M. Karabiyik, P.K. Vabbina, R. Sinha, N. Pala ⇑Department of Electrical and Computer Engineering, Florida International University, Miami, FL 33174, USA

a r t i c l e i n f o

Article history:Received 18 October 2013Received in revised form 10 February 2014Accepted 18 March 2014

The review of this paper was arranged byDr. Y. Kuk

Keywords:GrapheneGraphene FET (GFET)MicrowaveHigh frequencyCut-off frequency

a b s t r a c t

We propose a novel Graphene FET (GFET) with two capacitively coupled field-controlling electrodes(FCEs) at the bottom of the ungated access regions between gate and source/drain. The FCEs could beindependently biased to modulate sheet carrier concentration and thereby the resistance in the ungatedregions. The reduction of source/drain access resistance results in increased cut off frequency comparedto those of conventional GFETs with the same geometry. We studied the DC and improved RF character-istics of the proposed device using both analytical and numerical techniques and compared with thebaseline designs.

� 2014 Elsevier Ltd. All rights reserved.

1. Introduction

Graphene, a novel electro-optic material consisting of one or afew atomic layers of carbon sheets is considered to be promisingfor high performance nanoelectronics due to its high carrier con-centration, mobility and stability [1,2]. It is a prime candidate formany other electrical and optical applications due to its extremelyhigh thermal conductivity, long phonon mean free path and as a 2Dmaterial it could also enable extreme device scaling [3,4]. With itslarge band structure velocity (1 � 108 cm/s), large saturation veloc-ity (4 � 107 cm/s) and low 1/f noise characteristics [5–8], Grapheneis particularly attractive for high frequency electronics and numer-ous groups have reported Graphene analog devices with amplifica-tion and phase detection capabilities [9,10]. Moreover, because ofstrong ambipolar effect and lack of bandgap [2], it is believed tobe more suitable for analog applications than it is for digital elec-tronics. Significant progress has been made on Graphene analogdevices to achieve good high frequency performance with intrinsicon-chip cut-off frequency up to 300 GHz [11].

It is well known that the source/drain resistances comprising ofcontact resistance and access resistance impose important set oflimitations on the high frequency performance of sub-micrometer

FETs. These resistances delay the transition of carriers through thedevice and reduce the external transconductance leading to a low-er drain current. In terms of delay time, reduction of transit delayand parasitic delay ensure high cut-off frequency that can beachieved through shorter gate length and smaller access regionswith smaller contact resistances, respectively. Self-aligned fabrica-tion process has been used to reduce the access region length toachieve fT = 23 GHz for the gate length Lg = 110 nm and ungated re-gions with the length of 20 nm. [12] However self-aligned processmakes fabrication more complex with smaller tolerances.

Reduction of access resistance for enhanced RF performance inIII-N HEMTs [13] and in Graphene FETs have been proposed[14,15]. In this paper, rather than reducing the access resistanceby minimizing ungated region length or by channel doping, wepropose and extensively analyze a novel device structure including2 field-controlling electrodes (FCEs) capacitively coupled to theungated regions at the bottom of the device to control the accessresistance. Using the proposed device as an amplifier, along withhigh cut-off frequency due to parasitic delay time minimization,at a fixed DC biasing condition, one would have control over thegain at a certain frequency by tuning the FCE bias. The capacitivecoupling technique of the additional contacts ensures mitigationfrom additional power consumption and the proposed position ofFCEs at the bottom of the device would make the fabrication sim-pler than the top FCE GFETs [16].

C. Al-Amin et al. / Solid-State Electronics 95 (2014) 36–41 37

2. Theory

The schematic of a conventional 3-terminal GFET on SiO2 withthe small-signal equivalent circuit overlaid on top is shown inFig. 1(a).

The gate to source (drain) capacitance Cgs (Cgd) is composed ofboth internal and external parts:

Cgd ¼ Cgd;i þ Cgd;ex Cgs ¼ Cgs;i þ Cgs;ex ð1Þ

The external capacitances Cgd,ex and Cgs,ex are fringe capacitancesand independent on gate length whereas the internal capacitancesCgd,i and Cgs,i directly scale with gate length. If gm is the intrinsictransconductance, the transit delay, strans consisting of intrinsicand extrinsic delay of the device can be expressed as [17,18]:

strans ¼ ðCgs;in þ Cgs;exÞ þ ðCgd;in þ Cgd;exÞ� �

=gm ð2Þ

The parasitic time delay due to parasitic resistances and capac-itances can be expressed as [17]:

spar ¼ CgdðRS þ RDÞ � 1þ ð1þ Cgs=CgdÞg0=gm

� �ð3Þ

where g0 = 1/RSD is the output conductance with RSD is the Drain toSource resistance and RS and RD are the source and drain resistancerepresenting the ohmic contact resistance, RC and source/drain ac-cess resistance, Racs in series:

RD ¼ RS ¼ RC þ ðLacs=lqn0WÞ ð4Þ

here Lacs is the access region length (Lgs and Lgd), l is the carriermobility, q is electronic charge, n0 is the residual carrier densityin Graphene and W is the device width. The current gain cut-off fre-quency fT is inversely proportional to the total delay time in the de-vice and can be expressed as:

1=2pfT ¼ strans þ spar ð5Þ

Thus, summing up all the delay times and rearranging, the fT ofthe device can be related to the small signal circuit parameters asfollows:

fT ¼gm=ð2pÞ

½Cgs þ Cgd� � ½1þ ðRS þ RDÞ=RSD� þ Cgd � gm � ðRS þ RDÞð6Þ

where RSD is the Graphene channel resistance that can be expressedas follows [12]:

RSD ¼ LG=lqðn20 þ n2

gÞ1=2

W ð7Þ

where ng is the carrier density due to gate modulation. One needs tominimize the delay times to increase the current gain cut-offfrequency.

Fig. 1(b) clearly show that the effect of parasitic time delay spar

becomes more prominent compared to other delays for short chan-nel GFETs. Similar results were obtained for short channel In0.7

Ga0.3As HFETs as well [19]. The indispensable minimization of par-asitic delay time for GFETs with improved RF performance

Fig. 1. (a) Schematic of a typical GFET on SiO2 with small-signal equivalent circuit overlafrom [17].

becomes possible by reducing the source and drain access resis-tance using FCEs. As proposed, an FCE of length LFCE placed at theaccess region making two no-FCE regions named LS/D-FCE andLg-FCE at the S/D and gate end of each FCE respectively can changesthe expression of RS and RD as follows:

RS ¼ RD ¼ 2RC þ2Lg-FCE

lqn0 �Wþ 2LS=D-FCE

lqn0 �Wþ 2LFCE

lqðn20 þ n2

FCEÞ1=2W

ð8Þ

The resistance of the ungated access regions decreases by theinduced carriers nFCE due to FCE modulation which results in a dec-rement of spar and increment of fT.

3. Results and discussion

To validate our simulation method, we selected a baseline con-ventional GFET with experimental data reported in the literatureand replicated its measured DC and RF characteristics [3]. Laterto validate our proposed method of improving RF characteristics,we added the FCEs at the bottom of ungated regions of the deviceand estimated the improvement of fT over the reported one usingboth analytical and numerical techniques. The baseline devicehas CVD grown Graphene channel with electron mobility oflE = 336 cm2/V s and hole mobility of lH = 530 cm2/V s on300 nm SiO2 with gate length of Lg = 3 lm, source/drain accesslength of Lgs/Lgd = 1.5 lm and 24 nm thick gate dielectric as shownin Fig. 2(a). We named this long channel low mobility device asGFET-A. From the reported DC characteristics of the device, we ex-tracted the residual carrier (hole) concentration of Graphene as7.02 � 1012 cm�2. This value of residual carrier concentration leadsto an access resistance value of 25.2 X for the 1.5 lm long ungatedregions on both sides of the gate considering the device width to be100 lm. We have used physically-based device simulation tool tosimulate our device. This type of simulation approximates theoperation and transportation of carriers through the structure byapplying a set of differential equations including Poisson’s Equa-tion, Carrier Continuity Equations and Drift–Diffusion Equation,derived from Maxwell’s laws, onto a 2D grid, consisting of a num-ber of grid points called nodes. This way the electrical performanceof a device can be modeled in DC, AC or transient modes of opera-tion [20]. The simulated DC and RF characteristics of the baselinedevice using such a tool with parameters modified for Grapheneare presented in Fig. 2(c) which are in good agreement with the re-ported ones. The extracted fT and fMAX are 1.0 GHz and 1.2 GHz,respectively.

In the Id–Vg characteristics of a GFET, the lowest current point isthe Dirac point which has the hole dominant region on its left andelectron dominant region on right. Though the operating regime ofGFETs is user’s choice, the total device current on either regime isalso supported by the low density residual carriers available at theungated regions contributing to the source/drain resistance whichaffects the RF performance.

id on top. (b) Intrinsic and parasitic time delays vs. gate length of GFET reproduced

Fig. 2. Schematics of (a) baseline GFET-A, (b) modified GFET with 2 bottom FCEs at the ungated region and (c) DC and RF characteristics (current gain, |h21| and UnilateralPower Gain, UPG) of the baseline device.

38 C. Al-Amin et al. / Solid-State Electronics 95 (2014) 36–41

To improve the RF performance we added FCEs at the 1.5 lmlong ungated regions on bottom of GFET-A shown in Fig. 2(b). Aswe cannot make the gate dielectric so thick that the gate loses goodcontrol over the channel, we have a limitation on the gate voltagetoo not to surpass the gate dielectric breakdown electric field. Asthe dielectric between FCEs and channel is much thicker comparedto the gate dielectric, the FCE voltage was much higher than thegate voltage. To determine the optimum FCE length and positionproviding maximum fT for GFET-A, we placed FCEs of differentlengths at the center of the access regions leaving two equalno_FCE regions both sides and simulated the RF performance atVFCE = �9 V which represents an electric field moderately lowerthan the breakdown electric field of SiO2 [21]. It was reported thatcarrier mobility did not show significant dependence on carrierconcentration in the range of concentration we consider here[22]. Therefore, the hole and electron mobility was kept constantat 530 cm2/V s and 336 cm2/V s respectively for VFCE = �9 V as wellas for rest of the analyses performed on GFET-A throughout the

Fig. 3. At VFCE = �9 V (a) fT plotted against different LFCE. (b) At LS/D-FCE = 50 nm

entire range of FCE bias. The dependence of fT over LFCE shown inFig. 3(a) reveals that two 1.4 lm long FCEs at the access regionsleaving 50 nm no_FCE regions on each side is the optimum condi-tion in this case. Keeping the source/drain to FCE distance (LS/D-FCE)unchanged to 50 nm, we gradually decreased the gate to FCE dis-tance down to zero (FCE edge aligned to gate edge) and plotted fT

against them as shown in Fig. 3(b). The decrement of Lg-FCE showeddeterioration of fT rather than improvement here. At Lg-FCE = 50 nm,we later decreased the LS/D-FCE from 50 nm down to zero gradually.This time, the decrement of LS/D-FCE increased the fT as shown inFig. 3(c).

From Fig. 3, the optimum LFCE, LS/D-FCE and Lg-FCE were found1.45 lm, 0 lm and 50 nm respectively. Using the FCEs with opti-mum length and position, for hole regime operation of GFET-A(Vgs = �2.0 V), the DC simulations showed that the drain currentincreased with increasing negative FCE bias (VFCE) shown in Fig. 4which reveals reduction of access resistance. Analytical calcula-tions based on the equations presented above were used to

, fT plotted against Lg-FCE. (c) At Lg-FCE = 50 nm, fT plotted against LS/D-FCE.

Fig. 4. Increment of drain current with FCE bias at Vds = 5.0 V and Vgs = �2.0 V.Fig. 7. Current gain and Unilateral Power Gain vs. frequency of the short channelhigh mobility baseline GFET.

C. Al-Amin et al. / Solid-State Electronics 95 (2014) 36–41 39

quantify the reduction and was found that for Lgs/Lgd = 1.5 lm withFCEs of optimum size and position, the access resistanceRacc = 36.8 X of the baseline device went down to 23.0 X atVFCE = �9 V.

We used analytical and numerical investigation to estimate theRF improvement in both electron and hole regime of operation.Fig. 5(a) shows the simulated current gain, |h21|–frequency rela-tionship of the device for the DC biasing conditions of Vgs = �2 V,Vds = 5 V which represents hole regime operation of GFET-A andfor different FCE biases. The current gain cutoff frequency, fT wasextracted from the data in Fig. 5(a) and compared to the ones ana-lytically calculated in Fig. 5(b). As the simulation tool estimates the

Fig. 5. (a) Current gain |h21|–frequency relationship of the GFET-A with FCEs at varyinganalytical technique and also extracted from (a).

Fig. 6. (a) Current gain |h21|–frequency relationship of GFET-A with FCEs at different VF

analytical technique and also extracted from (a).

transportation of carriers through the structure by applying differ-ential equations onto the nodes of a 2D grid, it was capable ofincluding the additional capacitances arisen due to the presenceof the additional contacts (FCEs) by itself. To include them in theanalytical calculation part, we modified the capacitance values ofCgs and Cgd in the RF equations derived for conventional 3-terminalFETs by calculating the FCE capacitances using geometric andmaterial parameters.

For electron regime of the same device, DC biasing of Vds = 5 Vand Vgs = 6 V was considered for similar analytical and numericalestimation of the cut off frequency, fT. The fT of baseline GFET-A

VFCE values in hole regime of operation. (b) fT vs. VFCE where fT is calculated using

CE values in electron regime of operation. (b) fT vs. VFCE where fT is calculated using

Fig. 8. At VFCE = �9 V (a) fT plotted against different LFCE. (b) At LS/D-FCE = 150 nm, fT plotted against Lg-FCE. (c) At Lg-FCE = 150 nm, fT plotted against LS/D-FCE.

Fig. 9. Extracted fT from frequency response and from analytical calculations plotted against VFCE for (a) hole regime operation and (b) electron regime operation.

40 C. Al-Amin et al. / Solid-State Electronics 95 (2014) 36–41

in this condition was extracted to be 0.57 GHz. Fig. 6(a) shows the|h21|–frequency relationship of GFET-A with FCEs at different VFCE

and the extracted fT values along with those from analytical tech-nique are plotted against VFCE in Fig. 6(b).

We also explored the effect of biased FCEs on RF improvementin short channel high mobility GFETs. The baseline GFET chosen forthis analysis is similar to the one reported in [17]. The device hasCVD-grown Graphene channel with carrier mobility ofl = 2234 cm2/V s on sapphire substrate with Lg = 210 nm,Lsd = 1.5 lm and named as GFET-B. Considering the device geome-try to be symmetrical, access region length is Lgs = Lgd = 645 nm.The simulated RF performance of the baseline device presentedin Fig. 7 is in good agreement with the reported one after de-embedding. fT and fMAX were extracted as 22.1 GHz and 23.3 GHz,respectively. To improve the RF performance, FCEs are added onbottom of two 645 nm long ungated regions and biased up to±9.0 V as before not to exceed the breakdown voltage of Al2O3 re-ported in [23]. Graphene hole and electron mobility was consid-ered to be significantly dependent on carrier concentration andtheir values at different VFCE were estimated using the data in[24] for all analyses.

To determine the optimum FCE length and position for GFET-B,we placed FCEs of different lengths as before and simulated the RFperformance. The dependence of fT over LFCE, Lg-FCE and LS/D-FCE

shown in Fig. 8 reveals that the optimum values of LFCE, LS/D-FCE

and Lg-FCE are 495 nm, 0 nm and 150 nm respectively.Using the optimum FCE length and position, we estimated the

RF improvement in both electron and hole regime of operationusing both simulations and analytical technique. Analytical calcu-lation showed that the access resistance of 645 nm long access re-gion with an initial value of 3.66 X went down to 2.31 X forVFCE = �9 V. In frequency domain AC simulations, a biasing condi-tion of Vds = �1.6 V, Vgs = �0.6 V was assumed for hole regimeand Vds = �1.6 V, Vgs = 1 V was assumed for electron regime. Theextracted fT values from the frequency response for hole regimealong with those from analytical calculation using modified RF

equation for 5-terminal GFET are plotted against VFCE in Fig. 9(a)whereas that for electron regime in Fig. 9(b).

4. Conclusion

In conclusion, we have proposed and extensively analyzed highperformance RF GFETs with two field controlling electrodes placedunder the source-to-gate and gate-to-drain regions of the device toreduce the resistance in those regions. Simulations supported byanalytical calculations show that for hole regime operation ofGFETs with optimum FCE length and position, at VFCE = �9 V, fT ofthe proposed long channel low mobility GFET reached a value21.3% higher than that previously reported for conventional GFETof the same geometry. For the short channel high mobility GFET,considering mobility degradation with increasing carrier concen-tration in Graphene, at the same FCE bias the increment was26.7% over the reported fT of the baseline GFET. For electron regimeoperation, at VFCE = 9 V, the improvement for long channel andshort channel GFETs were 33.3% and 29.3% respectively. The pro-posed GFETs with improved RF characteristics can be used for highfrequency applications.

Acknowledgements

This work was supported in part by the National Science Foun-dation CAREER Program under Award 1149059 and the Army Re-search Office under Grant W911NF-12-1-0071.

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