fic 486 vip-io-manual

8/9/2019 FIC 486 Vip-Io-Manual

1/15

H NDLING PREC UTIONS

NOTE : Static ote


2/15

..

Cha t r

Overview

lla.l'd on lh<

VIA GMC

chips< ,

the

486-VIl'-IO·maJnboard

combinc1

an ISANvbu•

platf'orm

with the

advonc


3/15

1 2

Overview

• Optional Flash ROM.

• Award BIOS.

• Supports 128K/256K/512K/1M direct-mapped write

back/write-through cache memory.

• 72-pin SIMM sockets supports

up

to 64MB DRAM, pro-

vides page mode DRAM operation.

• Supports system and video BIOS cacheable

imd

shadpw.

• Supports decoupled DRAM refresh.

• Optional built-in ZIF socket that accepts· Intel s Over

Drive™ processors.

• Optional Regulator Daughter Board provides 3.45V for

IntelDX4™ CPU.

• Supports three 16-bit ISA expansion slots.

• Supports two VESA bus expansion slots.

• Supports four PCI bus expansion slots.

• DALLAS DS1288SQ real time clock/calendar.

• Provides built-in power management features necessary for

Green PCs.

• Cable for the PS/2 mouse interface (optional).

• Supports VIA 83C461/Promise PDC20230C (optional)

Local IDE.

• Optional enhanced IDE support allows for up to four host

interface devices.

• Built-in IDE HDD/FDD and Local Bus IDE interface. ·

• NS PC87311/312/332 chipset for two serial/one parallel

port.

• Supports ECP/EPP Protocol (NS 332 only).

486-VlP-10

f

(

_

Overview

Mainboard ayout

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TAGRAM M1

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MS

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J32 J31 J30 • c= : J

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80486SX/

DX/DX2/DX4

Cx486S/Cx486DX

P24D/P24T/P24CT

P4S/P23S/P24S

Jl:B· c;: =i

igure 1 1. Mainboard Layout

486-VIP-10


4/15

2 2

Mainboard Settings

JUMPER

P23SIP4SI 486SXIOX/ Cx486S/OX' lnteiDX4/ I

(RP008P4R) P24S/P24T

lnteiDX2

(M ,M7) P24DIP24CT

JC5

short open

open short

RN18

empty empty inserted ei:npty

RN19

empty empty empty

inserted

RN20 empty empty empty empty

P24S*/P4S*/

c x g ~ ~ l

JUMPER

486SX/

486DX/

P24CT/

Cx486S

. 1240

P23S Intel DX21

P24T*

M6)

Cx487S.

lnte1DX4 (M6+C6)

JC1,

JC2

2-3 1-2

1-2

2-3 1-2 1-2

'

JC3 open open short

open

open '

open.

i

JC4 1-2 1-2 2-3

1-2 1-2 2-3

JC6

short short short

open open short

-

* P23S, P24S, P24D and P4S are the SL-enhanced CPUs while P24T is the Penttum

OverDrive Processor.

NOTE : When the on board 3.3-volt regulator is

not

present,

1

the

3.3-volt

daughter

board

should

be inserteded.

If not,

please read page 2-14.

JUMPER PIN DEfli\IITION

Write-back/write-through select for P24D/P24T

JC7

1-2 write-back

2-3 write-through

For Intel's 3.3V CPU or Cyrix's 3.6V CPU

JC8 1-2 Intel DX4

2-3 Cyrix 486DX/DX2-V

JC9

1-2 lntei-S CPU

2-3 P24D/P24T/Cyrix 486DX

If onboard regulator is present, selector for Intel's 3.3v cpu

JC10

or Cyrix's 3.6V CPU

open Intel DX4

short Cyrix 486DX/DX2-Y

-

Table 2-1. Jumper Setting or PU Selector (Crmtinued)

486-VIP-10

( c

( (

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l

Mainboard Settings

2 3

l

JUMPER

PIN

DEFINITION

DX4 clock mode select

J27

1-2

2.5X mode

2-3

2X mode

open

3X mode

JX1, J20, J23

1-2 (default)

JX2, JX5

2-3 (default)

JT3

1-2

IRQ14

2-3

IRQ10 (default)

1-2

PCICLK=CPUCLK (default)

JT4, J19

2-3

PCICLK=CPUCLK/2

(40MHz

is

recommended

for

better performance.)

Table 2-1. Jumper Setting or PU Selector

NOTE : Users are

not

encouraged to change the jumper

settings not

listed in

this

manual. Changing the jumper

settings improperly may adversely

affect

system

perform-

ance.

NS87311/312

Jumper

Setting

BASE 1/0

ADDRESS

I

I

INDEX ADDRESS

I

DATA ADDRESS

JF

I

1-2

I

26EH*

I

26FH*

L I

2-3

I

398H

I

399H

~ U M P R

PRINTER

PORT

DIRECTION SELECT

INPUT

BIDIRECTION

JG

1-2

..2-3

JH

1-2

N/A

*

actory default

Table 2-2. NS87311/312 Jumper Setting

486-VIP-10

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Some millfunttion problems

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3 Ground

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11/15

3 2

Memory Subsystem

Installing DR M

SIMM Banks

The 486-VIP-10 can accommodate onboard

m ~ r y

from I to

64MB using SIMMs (Single-In-Line Memory l yiodules). The

mainboard has four

memory

banks

Bank

0

I, 2,

3.

Each

bank can accept either a

1MB

4MB, or 16MB SIMM in-t;ach

socket.

DR M Configuration

Memory can be installed in a variety

o

configurations, as

shown in the next table:

TOTAL

BANKO

BANK

BANK2

BANK3

MEMORY

72-PIN)

72-PIN)

72-PIN)

72-PIN)

1MB

1MB

1MB

1MB

1MB

1MB

2MB

1MB

1MB

1MB

1MB

1MB

1MB

1MB

1MB

1MB

3MB

1MB

1MB

1MB

1MB

1MB

1MB

1

1MB

1MB

1MB

1MB

4MB

4MB

4MB

4MB

MB

1MB

1MB

4MB

I

5MB

1MB

4MB

4MB

1MB

1MB

4MB

4MB

1MB

Table 3-1. DR M Configurations Continued)

486-VIP-10

Memory Subsystem

3 3

TOTAL

BANKO

BANK

BANK2

BANK3

MEMORY

72-PIN)

72-PIN) 72-PIN)

72-PIN)

4MB

1MB 1MB

1MB 1MB

4MB

I

6MB

1MB

4MB

1MB

4MB 1MB 1MB

4MB

1MB 1MB

·

7MB

4MB

1MB 1MB 1MB

1MB 4MB 1MB

1MB

4MB 4MB

8MB

4MB

4MB

•

4MB

4MB

4MB 4MB

1MB 4MB

4MB

4MB 1MB

4MB

9MB

4MB 4MB

1MB

1MB

4MB 4MB

1MB 4MB 4MB

10MB

1MB 1MB

4MB 4MB

4MB 4MB

1MB 1MB

4MB 4MB

4MB

12MB

4MB 4MB

4MB

4MB

4MB 4MB

13MB

1MB

4MB

4MB 4MB

4MB 1MB

4MB 4MB

4MB 4MB 4MB 4MB

16MB

16MB

16MB

16MB

16MB

1MB

1MB 16MB

17MB

1MB

16MB

_

16MB

1MB

1MB 16MB

Table 3 1. DRAM Configurations Continued)

486-VIP-10


12/15

3 4

Memory Subsystem

TOTAL BANKO

BANK1 BANK2 BANK3

MEMORY (72-PIN) (72-PIN) (72-PIN)

(72-PIN)

t

I [

I

16MB 1MB 1MB

-

18MB

1MB 1MB 16MB

1MB 16MB 1MB

I

16MB 1MB 1MB

16MB 1MB 1MB

1MB

19MB

-

1MB

16MB 1MB

1MB

16MB 4MB

4MB 16MB

20MB

4MB 16MB

4MB

16MB

»}

16MB 4MB

16MB 4MB 1MB

1MB 4MB 16MB

21MB

1MB 16MB 4MB

4MB 1MB 16MB

4MB 16MB 1MB

( I (

22MB

16MB 4MB 1MB

1MB

4MB 16MB 1MB

1MB

16MB 4MB

4MB

24MB

4MB 4MB 16MB

4MB 16MB 4MB

16MB 4MB

4MB

25MB 1MB

16MB 4MB

4MB

28MB

16MB

4MB 4MB

4MB

4MB 16MB 4MB

4MB

16MB 16MB

16MB

32MB

16MB 16MB

32MB*

32MB*

Table

3 1.

DR M Configurations Continued)

(

_

486-VIP-10

Memory Subsystem

3 5

TOTAL

BANKO BANK1

BANK2 BANK3

MEMORY (72-PIN) (72-PIN) (72-PIN)

(72-PIN)

16MB 16MB

1MB

33MB

1MB

16MB

16MB

1MB 16MB

16MB

1MB

16MB 16MB

34MB

16MB 16MB

1MB 1MB

1MB 1MB

16MB 16MB

16MB 16MB

4MB

36MB

4MB 16MB

16MB

4MB 16MB

16MB

4MB

1

16MB 16MB

37MB

1MB 4MB

16MB 16MB

r

4MB 1MB 16MB

16MB

40MB

16MB 16MB

4MB 4MB

4MB 4MB

16MB 16MB

48MB

16MB 16MB

16MB

16MB 16MB 16MB

49MB

1MB 16MB

16MB

16MB

52MB

4MB 16MB

16MB 16MB

64MB

16MB 16MB

16MB 16MB

32MB

32MB

*

Double RAS SIMM

Table

3 1.

DR M

Configurations

NOTE : Only Banks 0 and 2 can accept double-RAS SIMM. i

If Bank 0 has a double-RAS SIMM inserted, then Bank 1

I

should be free

of

SIMM. Likewise,

if

Bank 2 has a double-

i

RAS SIMM inserted, then Bank 3

should

be free of SIMM.

I

486-VIP-10


13/15

3 6

Memory Subsystem

Installation Instructions

NOTE : Always observe static electricity precautions. See

I

Handling Precautions at the start of this manuat

j

I. Locate the SlMM banks on the mainboard. Determine·

your desired configuration to be installed.

2. Insert the SIMM edge connector at a 90-degree·angle

onto the socket.

Figure 3 2. Installing SfMMs

3. Carefully push the S MM down and back into the socket until

the retaining clips

of

he socket snap, holding the SIMM in

place. The holes in the SIMM should match the pins on the

socket s retaining clips.

To remove the SIMMs, pull the retaining latch on both ends of

the socket and reverse the procedure above.

Cache Memory

The 486-VIP-10 can accept cache memory of 128KB, 256KB,

512KB, or 1MB.

NOTE :

e

sure to use the correct chips for the amount of['

cache memory you want to add. You must install both the

correct Cache and Tag

~ R A M

1

486-VIP-10

f

(_

Memory Subsystem

3 7

Installing Cache Memory

NOTE : Always observe static electricity precautions. See 1

Handling Precautions at the beginning of this manual. .

fyou do not have the confidence to make the installation, bett er

consult a service technician for assistance.

I. Locate the cache memory on the mainboard.

See Figure 3 1 again.

2. Be guided by the Cache SRAM settings depending on

your desired SRAM configuration.

Correct orientation of the chips is necessary for the cache to

operate properly. Normally, the chips have either a curved

notch or a dot. This marker on the chip must be matched to the

marker on the socket for correct alignment.

Install the chips individually as follows:

3. Align the chip with the marker on the socket.

Press the chip onto the socket, ensuring that the pins on the

chip are aligned with the corresponding connecti0ns on

the socket.

4. Carefully apply enough pressure to partially seat the chi p

into the socket.

Ensure that all pins are properly ali gned with the connectors and

that there are no bent pins. If here are any bent pins, remove the

chip, straighten the pin and repeat the

p r o c e ~ s

5. Press the chip completely into the socket so that the pins

are properly seated.

486-VIP-10


14/15

3 · 8

M

elllOIY

Subsystem

Cache SRAM Specifications and Sett ings

128K Cache SRAM

L t 3 ~ . 1 : K _

Memo.y Subsystem 3 • 9

512K Cache SRAM

U •-. . .-

..

5

Wfd ft -

' I • t ___] I

OR

f t M U ' f '

256KCacheSRA M

II

,M

t 1 3 ~ ~ : ~

L 6

_

lola

8 ~ f l ~

OR

..

1MB Cache SRAM

M ~ H f t

•

-t .M:n,_

M 5 ~

••9

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__j I ...

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t

4.56 VIP·IO

4.56 VIP 10


15/15

10

I

BankO

Bank 1

Tag RAM

(M1)

JS

(Jumper)

JS2

(Jumper)

JS3

(Jumper)

JS4

(Jumper)

JS5

(Jumper)

JS6

(Jumper)

Memory Subsystem

The cache size is jumper selectable. M2-M5 are assigned as

Bank 0 and M6-M9 are assigned as Bank I.

128K

I

256K

I

512K

1

1M

I

32Kx 8

32Kx 8 64Kx 8 128K x 8 64Kx8 128K x 8

I

Empty

32Kx8 Empty Empty s4Kxa

128K x 8

8Kx 8/

32Kx 8

32Kx 8 32Kx8

32Kx.at·

6 4 ~ ) 8 /

32Kx

8 64Kx

a· 128K x 8

1-2 2-3 2-3 2-3 2-3 2-3

1-2 2-3

2-3 2-3 2-3 2-3

I

1-2

1-2 1-2 2-3 2-3 2-3

1-2

1-2 1-2 1-2 1-2 2-3

1-2

1-2 1-2 2-3 2-3 2-3

1-2

1-2 1-2 1-2

1-2 2-3

Table 3 2. Cache Configuration Size

486-VIP-10

{ r

(

_

l

Chapter

ward BIOS Setup

The 486-VIP-10 comes with the Award BIOS chip that con

tains the ROM Setup information of your system. This chip

serves

as

an interface between the CPU and the rest of the

mainboard's components. This chapter explains the informa

. ion contained in the Setup program and tells you how to modify

the settings according to your system configuration.

System Setup

A Setup program, built into the system BIOS,

is

stored

in

the

CMOS RAM that allows the configuration settings to be

changed. This program

is

executed when:

1.

User changes system configuration.

2. User changes system backup battery.

3. System detects a configuration error and asks fhe user

to run the Setup program.

After power-on RAM testing, the message TO ENTER

SETUP BEFORE BOOT, PRESS CTRL-ALT-ESC or

appears. After pressing the above mentioned keys, the

following screen appears:

~ O M P C ~ ~ ~ ~ A - B I O S - 2 A 4 L 4 ~ 0 t D - - - - - - - , ~

STANDARD CMOS SETUP

AWARD SOFTWARE. INC.

1

STANDARD CMOS SETUP - ~ - S U P E R V I S ~ ; P A S S W O ~ - t

BIOS FEATURES SETUP I USER PASSWORD

I

CHIPSET FEATURES SETUP IDE HDD AUTO DETECTION I

POWER MANAGEMENT SETUP i SAVE & EXIT SETUP • I

PCI CONFIGURATION SETUP ll

. '

I

XIT WITHOUT SAVING

LOAD BIOS DEFAULTS

LOAD SETUP DEFAULTS

- - -

Esc Quit -> < Select Item

P

() ~ a v e and

Ex t_

Setup

- ~ j f t ~ h n g e

Ce>lc>r_

Time,

Date. Hard

D sk

Type

J

-

-

-

486-VIP-10

fic 486 vip-io-manual

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