トランスポート層 tcp輻輳制御（3.7）...2015/2/20 2 osaka university6 cam can search its...

2015/2/20

1

Osaka University

Design of a High-speed

Content-centric-networking Router

Using Content Addressable Memory

Atsushi Ooka

Osaka University

Japan

1Osaka University

Overview of Content-Centric Networking (CCN)

Challenges to implement CCN router

Propose an architecture of CCN router

Name Lookup Entity (NLE)

Interest Count Entity (ICE)

Hardware Design

Evaluation

April 28th, 2014 INFOCOM2014 NOM Workshop

Outline

2Osaka University

Content-based addressing with “name”

Natively supported mechanisms to distribute content

Interest aggregation

Data multicasting

In-network caching


Content-Centric Networking (CCN)

name：/movie/olympic.mp4

/movie/olympic.mp4

cacheaggregate

multicast

Interest Data

3Osaka University

Handles two types of packets (Interest and Data)

Contains three types of tables to support new mechanisms

FIB*1: Forwards Interest

PIT*2: Aggregates Interest and multicasts Data

CS*3: Caches Data

CCN Router Model

*1 Forwarding Information Base, *2 Pending Interest Table, *3 Content Store

Interest Data CCN Router

Face 1

Face 2

Face 3

FIB

PIT

CS

Consumer

Producer

Contro

ller

4Osaka University

Variable-length, hierarchically structured names

The number of content names is very large.

The Latency of tree-based approaches is high.

Limited cache capacity of CCN router

Popular content is replaced by unpopular one

Challenge

unpopularname: /A/B/C/…/X/Y/Z

cache memory

A

B D

C

Zcached

data, port,

etc.


popular

5Osaka University

Discuss an accurate communication model for CCN that

properly handles all packets

Design an architecture of CCN Router

Fast lookup hierarchical name using CAM and Bloom filter

Identify content worth caching

Evaluate performance and cost of the hardware


Approach

2015/2/20

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6Osaka University

CAM can search its entire memory in a single lookup.

Bloom filter is low-cost and fast memory for testing

membership.

Lookup Using CAM and Bloom Filter


/A/B/…/Z

/A/B

/A

name Bloom filter CAM

hit

not hit

not hit

/A/B/…/Z 1000

cached data, destination

port, etc.

nameRAM

address

RAM

/A/B/…/Z

Bloom filter greatly reduces

the workload on the CAM.

CAM searches a name

in a single lookup.

split n

am

e in

to p

refix

es

7Osaka University

Cache content depending on the number of requests

Small amount of popular content covers the majority of

requests. (Ex. Only 10% of content requested more than

three times covers 50% of traffic. [6] )

Identify Content Worth Caching

unpopular content

popular content

consumer

cache memory

3

content requests

1

[6]F. Guillemin, et al, “Experimental analysis of caching efficiency for YouTube traffic in an ISP network,” in Proceedings of the 25th International Teletraffic Congress, September 2013, pp. 1–9.

8Osaka University

Name Lookup Entity (NLE)

Hardware to lookup name quickly

Interest Count Entity (ICE)

Hardware to select content worth caching


Hardware Design of Proposed CCN Router

NLEICE

namedata

Packet parser

RAM controller

Face 1 Face 2 ・・・Face 3 Face n

RAM (FIB, PIT, CS)

data pointer

hit storage hit storageNLEICE

RAM read/write operation

Input Output

9Osaka University

NLE consists of Bloom filter, CAM, and two buffers.

We split the monolithic CAM into multiple smaller CAM

Reduce the cost and power

Perform a lookup process in parallel and improve throughput


Hardware Design of Name Lookup Entity (NLE)

[ Partial name buffer ]

<Partial name> <Address>

1 /aaa/.../bb/c 1

2 ccc/.../ddd 3

3 /ee/.../ffff 4

・・・

・・・

・・・

M

[ Partial prefix buffer ]

<Partial prefix>

1 /www/.../xxx/yy/zzzz 35

2 /www/.../xxx/yy 30

3 /www/.../xxx 27

・・・

・・・

・・・

N /aaa 4

5

5

5

・・・

1

CA

M h

and

ler

CAM 1

CAM 2

CAM 3

・・・

CAM D

prefix [1..W] Prio

rity encod

er (LP

M)

DL

B-B

F h

and

ler

Partial p

refix parser

Partial n

ame p

arser

DLB-BF

・・・

BF h

it vector

RA

M-p

oin

ters mem

ory

CSlength

name, len[1..l ]name, len[1..l ]

PITFIB

prefix[1..W2]

・・・

・・・

・・・

prefix[1..W2],

addr[1..s]

prefix[1..W1]

prefix[1..W1],

len[1..l ],Index[1.. l ]

#partial name[1.. l ], lpm index[1..l ]

#partial prefix[1.. l ]

・・・

hit

add

r[1..s ]

prefix[1..W1]

addr[1..s ]

prefix[1..W2],addr[1..s]

hitvector[1..N]

name: /aaa/... /bb/cccc/.../ddd/ee/.../ffff/.../www/.../xxx/yy/zzz

name[1..W1]

RAM

<Index><Length>

po

inte

r[1..p

]

pre

pro

ce

ssin

g u

nits

CA

MB

loo

m filte

r

10Osaka University

NLE consists of Bloom filter, CAM, and two buffers.

We split the monolithic CAM into multiple smaller CAM

Reduce the cost and power

Perform a lookup process in parallel and improve throughput


Hardware Design of Name Lookup Entity (NLE)



1 /aaa/.../bb/c 1

2 ccc/.../ddd 3

3 /ee/.../ffff 4

・・・

・・・

・・・

M


<Partial prefix>



3 /www/.../xxx 27

・・・

・・・

・・・

N /aaa 4

5

5

5

・・・

1

CA

M h

and

ler

CAM 1

CAM 2

CAM 3

・・・

CAM D

prefix [1..W] Prio

rity encod

er (LP

M)

DL

B-B

F h

and

ler

Partial p

refix parser

Partial n

ame p

arser

DLB-BF

・・・

BF h

it vector

RA

M-p

oin

ters mem

ory

CSlength


PITFIB

prefix[1..W2]

・・・

・・・

・・・

prefix[1..W2],

addr[1..s]

prefix[1..W1]

prefix[1..W1],




・・・

hit

add

r[1..s ]

prefix[1..W1]

addr[1..s ]


hitvector[1..N]


name[1..W1]

RAM

<Index><Length>

po

inte

r[1..p

]

①Input Packets

②Preprocessing

• Partition input name into fixed length

partial names.

• Split the partial names into partial

prefixes delimited by

the character ``/’’.

③Bloom Filter Process

• Test whether each partial prefix is stored in CAM.

④CAM Process

• Lookup only names accepted by Bloom filter

in parallel.

⑤Return Results

pre

pro

ce

ssin

g u

nits

CA

MB

loo

m filte

r

11Osaka University

ICE is implemented as a simple hash table.

Key: a name address

Value: the count of Interest


Hardware Design of Interest Count Entity (ICE)

data

[ Interest counter ]

<Name>

1 /xxx/yyy/zzz 1

2 /abc/def/ghi 2

3 0

・・・

・・・

・・・

H(name) /aaa/ ... /bb/cccc 3

<Ind

ex>

<Co

unter>

・・・

・・・

・・・

N /123/456/789 1

name: /aaa/... /bb/cccc

data

CS-RAM

hash

Hash

fun

ction

H(n

am

e)

hit CS

name, count

Inte

rest co

unt h

and

ler

NLE

nam

e

Ha

sh ta

ble

Input

Outp

ut

(ca

che

)

2015/2/20

3

12Osaka University

Analyze the cost and performance of NLE.

Because the memory required for NLE implemented using

CAM is the most serious problem.

We calculate the required memory size, cost of the memory,

and throughput according to the hardware design.

Parameter Setting

The number of entries: 10 million [1,2]

Average packet size: 256 B (Interest: 40 B, Data: 1500 B)

The length of name: 99% of names are no longer than 40 B

and have no more than six components [3]


Evaluation

[1] Y. Wang, et al, “Wire speed name lookup: a GPU-based approach,” in Proceedings of the 10th USENIX Conference on Networked Systems

Design and Implementation, April 2013, pp. 199–212.

[2] Y. Wang, et al., “Scalable name lookup in NDN using effective name component encoding,” in Proceedings of the IEEE 32nd International

Conference on Distributed Computing Systems 2012, June 2012, pp. 688–697.

[3] D. Perino and M. Varvello, “A reality check for Content Centric Networking,” in Proceedings of the ACM SIGCOMM workshop on Information-

centric networking, August 2011, pp. 44–49.

13Osaka University

Throughput: 163 Gpbs

We can greatly improve by concurrent lookups.

Latency: 12.25 ns

The latency of existing tree-based approach[1]: 100 𝜇𝑠

Throughput and Latency

0 50 100 150 200

NCE

ENPT

Name Filter

MATA-NW

NLE

Throughput [Gbps]

[1]

[5]

[4]

[2]

[1] Y. Wang, et al, “Wire speed name lookup: a GPU-based approach,” in Proceedings of the 10th USENIX Conference on Networked Systems Design and Implementation, April 2013.

[2] Y. Wang, et al., “Scalable name lookup in NDN using effective name component encoding,” in Proceedings of the IEEE 32nd International Conference on Distributed Computing

Systems 2012, June 2012

[4]H. Dai, et al, “On pending interest table in Named Data Networking,” in Proceedings of the ACM/IEEE 8th Symposium on Architectures for Networking and Communications Systems

2012, October 2012

[5] Y. Wang, et al, “NameFilter: Achieving fast name lookup with low memory cost via applying two-stage bloom filters,” in Proceedings of the IEEE INFOCOM 2013, April 2013

14Osaka University

SRAM (Buffer and Bloom filter): 4.6 GB

CAM: 3.2 Gbit

3.2 Gbit TCAM is impractical in terms of memory size and

power.

We plan to use more scalable memory (ex. BCAM, hash

table).


Required Memory Size and Cost



1 /aaa/.../bb/c 1

2 ccc/.../ddd 3

3 /ee/.../ffff 4

・・・

・・・

・・・

M


<Partial prefix>



3 /www/.../xxx 27

・・・

・・・

・・・

N /aaa 4

5

5

5

・・・

1

CA

M h

and

ler

CAM 1

CAM 2

CAM 3

・・・

CAM D

prefix [1..W] Prio

rity encod

er (LP

M)

DL

B-B

F h

and

ler

Partial p

refix parser

Partial n

ame p

arser

DLB-BF

・・・

BF h

it vector

RA

M-p

oin

ters mem

ory

CSlength


PITFIB

prefix[1..W2]

・・・

・・・

・・・

prefix[1..W2],

addr[1..s]

prefix[1..W1]

prefix[1..W1],




・・・

hit

add

r[1..s ]

prefix[1..W1]

addr[1..s ]


hitvector[1..N]


name[1..W1]

RAM

<Index><Length>

po

inte

r[1..p

]

Buffer（SRAM）

CAM

Bloom filter（SRAM）

Memory size：3.2 Gbit→

Power：3 kW

Memory size：4.6 GB

NLE

15Osaka University

Summary

We designed a CCN router hardware architecture.

NLE: Fast lookup name using CAM and Bloom filter

ICE: Select content worth caching

We evaluated the throughput and cost of a CCN router.

Future work

Scale the memory capacity and the number of entries

Evaluate a CCN router performance based on a hardware

implementation

Evaluate network-level performance using the implemented

CCN router


Summary and Future Work

16Osaka University


17Osaka University

Hardware Design of NLE



1 /aaa/.../bb/c 1

2 ccc/.../ddd 3

3 /ee/.../ffff 4

・・・

・・・

・・・

M


<Partial prefix>



3 /www/.../xxx 27

・・・

・・・

・・・

N /aaa 4

5

5

5

・・・

1

CA

M h

and

ler

CAM 1

CAM 2

CAM 3

・・・

CAM D

prefix [1..W] Prio

rity encod

er (LP

M)

DL

B-B

F h

and

ler

Partial p

refix p

arser

Partial n

ame

parser

DLB-BF

・・・

BF h

it vecto

rR

AM

-po

inters m

em

ory

CSlength


PITFIB

prefix[1..W2]

・・・

・・・

・・・

prefix[1..W2],

addr[1..s]

prefix[1..W1]

prefix[1..W1],




・・・

hit

add

r[1..s ]

prefix[1..W1]

addr[1..s ]


hitvector[1..N]


name[1..W1]

RAM

<Index><Length>

po

inte

r[1..p

]

2015/2/20

4



1 /aaa/.../bb/c 1

2 ccc/.../ddd 3

3 /ee/.../ffff 4

・・・

・・・

・・・

M


<Partial prefix>



3 /www/.../xxx 27

・・・

・・・

・・・

N /aaa 4

5

5

5

・・・

1

CA

M h

and

ler

CAM 1

CAM 2

CAM 3

・・・

CAM D

prefix [1..W] Prio

rity encod

er (LP

M)

DL

B-B

F h

and

ler

Partia

l prefix

parser

Partial n

ame

parser

DLB-BF

・・・

BF h

it vecto

rR

AM

-po

inters m

em

ory

CSlength


PITFIB

prefix[1..W2]

・・・

・・・

・・・

prefix[1..W2],

addr[1..s]

prefix[1..W1]

prefix[1..W1],




・・・

hit

add

r[1..s ]

prefix[1..W1]

addr[1..s ]


hitvector[1..N]


name[1..W1]

RAM

<Index><Length>

po

inte

r[1..p

]



1 /aaa/.../bb/c 1

2 ccc/.../ddd 3

3 /ee/.../ffff 4

・・・

・・・

・・・

M


<Partial prefix>



3 /www/.../xxx 27

・・・

・・・

・・・

N /aaa 4

5

5

5

・・・

1

CA

M h

and

ler

CAM 1

CAM 2

CAM 3

・・・

CAM D

prefix [1..W] Prio

rity encod

er (LP

M)

DL

B-B

F h

and

ler

Partial p

refix p

arser

Partial n

ame

parser

DLB-BF

・・・

BF h

it vecto

rR

AM

-po

inters m

em

ory

CSlength


PITFIB

prefix[1..W2]

・・・

・・・

・・・

prefix[1..W2],

addr[1..s]

prefix[1..W1]

prefix[1..W1],




・・・

hit

add

r[1..s ]

prefix[1..W1]

addr[1..s ]


hitvector[1..N]


name[1..W1]

RAM

<Index><Length>

po

inte

r[1..p

]



1 /aaa/.../bb/c 1

2 ccc/.../ddd 3

3 /ee/.../ffff 4

・・・

・・・

・・・

M


<Partial prefix>



3 /www/.../xxx 27

・・・

・・・

・・・

N /aaa 4

5

5

5

・・・

1

CA

M h

an

dle

r

CAM 1

CAM 2

CAM 3

・・・

CAM D

prefix [1..W] Prio

rity e

nco

der (L

PM

)

DL

B-B

F h

and

ler

Partia

l prefix

pa

rser

Pa

rtial na

me

parse

r

DLB-BF

・・・

BF

hit v

ector

RA

M-p

oin

ters me

mo

ry

CSlength


PITFIB

prefix[1..W2]

・・・

・・・

・・・

prefix[1..W2],

addr[1..s]

prefix[1..W1]

prefix[1..W1],




・・・

hit

add

r[1..s ]

prefix[1..W1]

addr[1..s ]


hitvector[1..N]


name[1..W1]

RAM

<Index><Length>

po

inte

r[1..p

]

トランスポート層 tcp輻輳制御（3.7）...2015/2/20 2 osaka university6 cam can search its...

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