fet

EE101B: Common-source amplifier 7 – 1

Lecture 7

EE101B: Common-sourceamplifier

EE101BDepartment of Electrical Engineering Prof. M. HershensonStanford University Prof. K.V. Shenoy

• Common-source amplifier in ICs

– A simple common-source amplifier

∗ Circuit analysis

∗ Equivalent amplifier model

∗ Signal range

∗ Graphical analysis

– Degenerated common-source amplifier

• Discrete common-source amplifier

– Coupling capacitors

– Analysis

– Loading effects

• Example


Reading for this lecture

From Sedra & Smith

• Section 4.7.1

• Section 4.7.2

• Section 4.7.3

• Section 4.7.4

Practice problems

• Example 4.11


A simple common-sourceamplifier

Consider the common-source amplifier

VDD

M

RD

VO

vin

VI

• We call it common-source amplifier because thesource is connected to ground (the commonterminal)

• The input AC signal is fed from the gate

• The output AC signal is measured at the drain


Circuit analysis of the simplecommon-source amplifier

To analyze this amplifier we will do the following:

1. Perform DC analysis (find bias point: drain DCcurrent and check that the transistor is in thesaturation region)

2. Find circuit small-signal AC model (based on thebias point obtained)

3. Perform AC analysis

So far we have seen how to perform the DC analysis ofsimple CMOS circuits (Lecture 5) and how to obtaintheir small-signal AC model (Lecture 6). In this lecturewe focus on how to perform the small-signal ACanalysis.

In the remainder of this lecture, we assume that thetransistor operates in the saturation region at its biaspoint.


AC small-signal analysis:model

Now we find the AC (small-signal) model for thecommon-source amplifier shown in the first slide.For AC analysis:

• Kill the DC sources (i.e., short the DC voltagesources and open the DC current sources)

• Substitute the transistors by their AC (small-signal)model.

RD

vout

vin

+

−

rogmvgsvgs


AC small-signal analysis:voltage gain

1. Voltage gain=vout

vin:

• The input source is directly connected to thegate so we have vin = vgs

• so the current through the dependent currentsource is gmvin

• Now it is easy to find vout,

RD ‖ ro

vout

gmvin

We have ro in parallel with RD and all thecurrent from the dependent source flowsthrough the total drain resistance so

vout = −gmvin (RD ‖ ro)

and the gain is

Av =vout

vin

= −gm (RD ‖ ro)

Note that the gain is negative. (When vin

increases, vgs also increases. This means that idincreases so the drain voltage (vd) decreases.Since when vin increases, vd decreases the gainis negative. Note that the absolute gain can stillbe greater than one !!)


AC small-signal analysis:input and output resistances

The input and output resistances (Rin and Rout) of anamplifier are two important characteristics of theamplifier. We will be interested in them when theamplifier is connected to a source with non-zeroimpedance, when it is connected to a load or when it isconnected to another amplifier

VDD

M

RD

VO

vin

Rout

Rin

• The input resistance is the total resistancelooking into the amplifier (or in other words, is theresistance presented to the input signal source)

• The output resistance is the total resistance seenfrom the output of the amplifier.


AC analysis: input resistance

1. Input resistance: To compute the input resistancewe connect a test voltage source at the input of theamplifier and we compute how much current isflowing through it.

RD

vout

vtest

imeas

Rin

+

−rogmvgsvgs

Since the gate resistance is infinite, we have

imeas = 0

and the input resistance is just

Rin = ∞


AC analysis: outputresistance

2. Output resistance: To compute the outputresistance we kill the input source, connect a testvoltage source at the output of the amplifier and wecompute how much current is flowing through it.

vtest

imeas

Rout

+

−ro ‖ RD

gmvgsvgs

• Since vgs = 0, we have that gmvgs = 0 so thedependent current source is like an open circuit.

• then we have

vtest = imeas (RD ‖ ro)

• and the output resistance is

Rout = RD ‖ ro


Output resistance

Let’s try to understand the expression we obtained forRout. Looking into the output node we see RD inparallel with ro.

• For AC signals, RD is connected between thetransistor drain and ground

• ro is the small-signal resistance looking into thedrain of the transistor (since its source is connectedto ground).

vtest

imeas

id,2

id,1

RD

M1

In the figure id,1 = vtest/ro and id,2 = vtest/RD. Thenwe can write,

imeas = id,1 + id,2 =vtest

ro+

vtest

RD

sovtest

imeas=

11ro

+ 1RD

= RD ‖ ro


Equivalent amplifier ACmodel

An equivalent AC amplifier model for thecommon-emitter amplifier just seen is

vout

vin

Rout

vRin AvvRin

where

Av = −gm (RD ‖ ro)

Rout = RD ‖ ro

Note that Rin = ∞. This is a quite useful high-levelmodel. We will make use of it when we study multistageamplifiers.


Signal range: linear amplifier

We first take a look at the actual voltages at drain,source and gate for the common-source amplifier: theyhave both a DC component and an AC component.

Instantaneous voltages at transistor nodes

• Source voltage. The source is grounded so it hasno AC (or small-signal) component, i.e.,vS = VS = vs = 0.

• Gate voltage. Assuming the input AC signal isvin = vin sin(ωt) and the input DC signal is VI ,

vG = VI + vin sin(ωt)

Sometimes (if gain is large) we can neglect the ACcomponent at the gate because it is pretty smallcompared to the AC component in the drain. Themaximum and minimum values of the gate voltageare:

– max. gate instantaneous voltagevG,max = VI + vin

– min. gate instantaneous voltagevG,min = VI − vin

• Drain voltage.

vD = VD+vinAv sin(ωt) = VDD−IDRD+vinAv sin(ωt)

We call VM = |vinAv| (amplitude of AC signal atthe drain) and we have


– max. drain instantaneous voltagevD,max = VDD − IDRD + VM

– min. drain instantaneous voltagevD,min = VDD − IDRD − VM


Graphically,

VDD

M VM

VM

vin

vin

RD

VD

vin

VI

VG

• So far we have assumed that the transistor is biasedin saturation.

• We also have assumed that the transistor remains insaturation for the entire range of the AC inputsignal.

• If the transistor enters another region of operation,the analysis we just did would not be valid(remember we derived the small-signal model forthe transistor in saturation!)

• We now find out for what values of the input signalthe transistor remains in saturation


Signal range: limits

• If the drain voltage is too low (a threshold belowthe gate voltage), the transistor will enter the linearregion. The transistor behaves like a resistor andthe output voltage is no longer a linearamplification of the input voltage (it is clippedbelow). This is not a desirable behavior (in generalwe want to build linear amplifiers).

VDD

Mvin

vin

RD

VD

vin

VI

VG


In order to keep the transistor in saturation, weneed vD ≥ vGS − Vt. This has to be true at alltimes. The critical case is when the drain voltage isminimum and the gate voltage is maximum

vD,min ≥ vGS,max − Vt

so a limit on the swing at the drain is given by

VM ≤ VDD − IDRD − VI − vin + Vt

or equivalently, in terms of an upper limit on theinput signal

vin ≤ VDD − IDRD − VI + Vt

1 + |Av|• The drain voltage cannot be above the supply

voltage. Otherwise the transistor drain currentwould be flowing out of the drain which is notpossible. For very low values of the gate voltage,the signal at the drain clips at VDD.

VDD

Mvin

vin

RD

VD

vin

VI

VG

To avoid this behavior and keep the transistor insaturation, we need

vD,max ≤ VDD


so another limit on the signal swing at the drain is

VM ≤ IDRD

which in terms of a lower limit in the input signalcan be written as

vin ≤ IDRD

|Av|• There is also a limit on how large the input AC

signal can be so that our linearity approximationholds. We saw in Lecture 6 that for the small-signalmodel to be valid we need vgs 2 (VGS − Vt). Inthis case, vin = vgs so the requirement for vin is

vin 2 (VGS − Vt)

Taking to mean at least a factor of 10, we havethe condition

vin ≤ 0.2 (VGS − Vt)

in terms of VI ,

vin ≤ 0.2 (VI − Vt)

• Note that the condition above is more stringentthat the condition imposed by making sure that thetransistor is not turned off. To keep the transistoron, we need vGS ≥ Vt. The minimum value of vGS

is VI − vin. Thus, another limit on vin is

vin ≤ VI − Vt


Designing for maximumsignal range

• Normally we want to bias the amplifier at a pointthat allows maximum signal swing.

• If the DC drain voltage is too high (close to VDD),we will be able to have large negative swings but wewon’t be able to have large positive swings

• Similarly if the DC drain voltage is too low (close toground), we will be able to have large positiveswings but we won’t be able to have large negativeswings

• Thus, it makes sense to pick a DC value for thedrain voltage that is somewhere in the middle ofVDD and ground. The point for maximumsymmetrical swing (same amplitude of positiveswing than negative swing) can be obtained byequating the first two limits we derived above forthe input signal vin.

IDRD

|Av| =VDD − IDRD − VI + Vt

1 + |Av|if |Av| 1

IDRD = VDD − IDRD − VI + Vt

or in terms of VI

VI = VDD − 2IDRD + Vt


Maximum voltage gain

• Consider the common-source amplifier with RD verylarge (so RD ‖ ro ≈ ro) and VDD also very large (sowe can allow a large voltage drop across RD).

Under these circumstances the amplifier gain is

Av,max =vout

vin= −gm (RD ‖ ro) ≈ −gmro

or

Av,max = −gmro = − 2VA

(VGS − Vt)

The ratio 2VA/ (VGS − Vt) is an upper bound on thegain we can obtain from a common-source.

• In practice we have |Av,max| ≈ 10 − 100 (in sub0.1µm technologies, this value is more between1 − 10).

• A resistively loaded common-source, has gainsmuch smaller than Av,max. The reason is that RD

cannot be made very large for output voltage swingconsiderations.

• There are other amplifiers (amplifiers loaded withtransistors) in which one can get gains close toAv,max. We will see these amplifiers in the nextlecture.


Design trade-offs

How do we design an amplifier for high gain? Let’sassume for now that ro RD. Then we can write,

Av =vout

vin= −gmRD = − 2VRD

VGS − Vt= −2

√kVRD√ID

where VRD= IDRD is the DC drop across RD.

To have a large gain, we can:

• Increase k. For a given process µ and Cox arefixed, so to increase k we must make the ratio W/L

large. But we cannot make W/L arbitrarily large. Alarge W means large areas, large capacitances andslow circuits (more on this in later lectures). Thesmallest L is limited by the process technology.Also (in reality) a small L means small ro and worsebehavior predictability.

• Increase VRD. Since we have a finite supply

voltage, we cannot increase VRDarbitrarily.

Typically the maximum VRDwe can have is limited

by the voltage swing requirements.

• Decrease ID (assuming constant VRD). Small

currents give raise to smaller values of gm andlarger values of ro. This in turn, gives raise to largertime constants and thus slower amplifiers (more onthis in later lectures).


• Increase ID (assuming constant RD). We cannotincrease ID arbitrarily because of swing constraintsand also power constraints.

As you can see, there are a lot of design trade-offs, wemust consider when designing a circuit.


Graphical analysis

In Lecture 5, we saw how to plot the large signal V0/VI

characteristic of a grounded common-source amplifier.We don’t repeat the analysis here but show again theresulting transfer characteristic.

VI(V)

VO(V

)

00

1

1

2

2

3

3

4

4

5

5

slope=Av

6

6

• There is a range of VI for which the circuit behavesas a somewhat large gain amplifier. This is theregion where the slope V0/VI is high.

• The gain is negative since as we increase VI , V0

decreases.


• The gain (−gm (ro ‖ RD)) we found using thesmall-signal equivalent model is just the slope ofthis transfer characteristic in the region of high gain.

Remember in Lecture 5 (page 5.4), we derived thatfor λ = 0, the relationship V0/VI in the high gainregion was,

VO = VDD − 1

2µnCox

W

L(VI − Vt)

2 RD

Taking partial derivatives, we find

∂VO

∂VI= −µnCox

W

L(VI − Vt) RD = −gmRD

which is the same as we obtain with the small-signalanalysis if we consider ro = ∞ (corresponding toλ = 0).


Degenerated common-sourceamplifier

A degenerated common-source has:

• The input AC signal is fed from the gate

• The output AC signal is measured at the drain

• The source connected to ground with a resistor RS

VDD

M1

RD

RS

VO

VI

This circuit is an example of shunt-series feedbackwhich we will study at the end of the quarter.


Degenerated common-sourceamplifier: circuit analysis

For circuit analysis we follow the next steps:

1. Perform the DC-analysis as was covered in Lecture5.

2. We find the AC-model, which is similar to theprevious common-source except that we have asource resistance and we need to add anothertransconductance to show the body effect.

RD

RS

vout

vin

+

+

−

−rogmvgs gmbvbsvgs

vsb

3. We perform the AC-analysis using the AC-modelfound in previous step.


Degenerated common-sourceamplifier: voltage gain

1. Voltage gain=vout

vin: For this analysis we assume

ro = ∞.

RD

RS

is

idvout

vin

+

+

−

−gmvgs gmbvbsvgs

vsb

• We apply KVL, across the source resistor tocompute the source voltage is

vs = isRs (1)

• We apply KVL, across the drain resistor tocompute the output voltage is

vout = −idRD (2)

• We apply KCL at the drain and source

id = gmvgs + gmbvbs (3)

• Since vgs = vin − vs and vbs = 0 − vs, we canwrite equation (3) as

id = gm (vin − vs)−gmbvs = gmvin−(gm + gmb) vs

(4)


• Now we substitute equations (1) and (3) in (4)and have

id = gmvin − (gm + gmb) idRs (5)

which we can rewrite as

idvin

=gm

1 + (gm + gmb) RS(6)

• Now substituting (2) in (6), we find thesmall-signal voltage gain,

vout

vin= − gm

1 + (gm + gmb) RSRD

Some comments,

• For RS = 0, Av = −gmRD (same as we derivedbefore for ro = ∞).

• We have,vout

vin= − gm

1 + (gm + gmb) RSRD = −gm,effRD

where gm,eff = gm/(1 + (gm + gmb) RS). Wehave effectively reduced the transconductance(and gain) of the common-source amplifier by afactor 1 + (gm + gmb) RS.


• This amplifier has a smaller gain but also betterlinearity. For the same values of vin, we have asmaller vgs, and thus the small-signalassumption is valid for larger values of vin,

vgs = vin1 + gmbRD

1 + (gm + gmb) RS

• Assuming (gm + gmb) RS 1, we can write

vout

vin= − gmRD

(gm + gmb) RS= − 1

1 + χ

RD

RS

where χ = gmb

gm≈ 0.2 − 0.3.


Degenerated common-sourceamplifier: input/output

resistances

1. Input resistance: Since the gate current is zero,we have

Rin = ∞2. Output resistance: To compute the output

resistance, we short the input source, connect a testcurrent source itest at the output and measure theresulting voltage across it vmeas.

RD

RS

+

+

+

−

−

−rogmvgsvgs gmbvbs

iout

vsb

iditestvmeas

Since vg = 0 and vb = 0, we can simplify theschematic to,


RD

RS

+

+−

−

ro(gm + gmb)vs

iout

vs

idiro

itestvmeas

• The output resistance is given by

Rout =vmeas

itest= RD ‖ Rdrain (1)

whereRdrain =

vmeas

iout

• Applying KVL at the drain node, we can write

vmeas = Rsiout + roiro(2)

• Applying KCL at output node, and sincevs = RSiout, we can write

iro= iout+(gm + gmb) vs = iout [1 + (gm + gmb) RS]

(3)

• Substituting eq.(3) in eq.(2), we have,

vmeas = iout [RS + ro + roRS (gm + gmb)] (4)

and thus,

Rdrain = RS + ro + roRS (gm + gmb)

• So the output resistance is

Rout = RD ‖ [RS + ro + roRS (gm + gmb)]


Some comments:

• Note that Rdrain = ∞ if we assume ro = ∞.

• The resistance looking into the drain of atransistor whose source is connected to groundvia a resistor RS is much larger than that of atransistor whose source is directly connected toground. For RS = 0, we have

Rdrain,non−degen = ro

but for the degenerate case we have

Rdrain,degen = ro [1 + RS (gm + gmb)] + RS

which if ro RS, can be approximated by

Rdrain,degen ≈ ro [1 + RS (gm + gmb)]

Note that the resistance is 1 + RS (gm + gmb)times bigger in the degenerate case. It is thesame amount we have reduced the gain. Thereason behind this factor will become clearerwhen we study feedback.


Degenerated common-sourceamplifier

In a degenerated common-source amplifier we get lessgain than in a non-degenerated common-source for thesame value of transistor transconductance. Why wouldwe want to use degenerated common-source amplifier?

• Well, gain is not all that matters

• If we are concerned about linearity, the degeneratedis a better choice (for the same value of inputsignal, we get a smaller gate-to-source voltage andthus our linearity approximation is better)

• Also the gain in a degenerated amplifier can bemade less process dependent than in anon-degenerated case. We saw that for(gm + gmb) RS 1, we can write

Av = − 1

1 + χ

RD

RS

χ depends slightly on the process and the ratio ofresistors RD and RS is tightly controlled in an ICprocess. In contrast, the non-degenerated amplifierhas

Av = −gmRD

which is depends much more heavily on processparameters.


Discrete common-sourceamplifier

Let’s study now the implementation of acommon-source amplifier in a discrete environment.Typically you will not find this circuit in practicebecause MOSFETS are used mostly as switches notamplifiers in discrete applications.

Consider the following common-source amplifier.

RS CS

RD

vout

vin RG2

RG1

CG

CD

VDD


Discrete common-sourceamplifier: DC analysis

To perform the DC analysis:

• Kill the AC sources (i.e., short the AC voltagesources and open the AC current sources)

• open all capacitors (since capacitors are opencircuits at DC)

and we obtain....

RS

RD

RG2

RG1

VDD

We already studied this circuit in Lecture 5 . . .


Discrete common-sourceamplifier: AC analysis

The small-signal AC model is

RD

CD

CSRS

rogmvgsvgs

CG

vin

vout

RGG

• Capacitors CG and CD are called a couplingcapacitors. Capacitor CG AC couples the inputsource to the amplifier input. Capacitor CD ACcouples the drain voltage to the output of theamplifier. (AC couples means that it lets the ACsignal through)

• Capacitor CS is called a bypass capacitor.

In practice, we consider that these coupling/bypasscapacitors act like short-circuits at the signal frequency.

Note: RGG = RG1 ‖ RG2


Coupling capacitors

Why do we consider the coupling/bypass capacitorsshort circuits at the signal frequency?

• The magnitude of the impedance of a capacitor isgiven by

|ZC | =1

ωCFor these coupling/bypass capacitors, we have thatat the signal frequency |ZC | is much less than theresistance at the capacitor terminals, i.e.

|ZC | RC

Since their impedance is much less than theimpedances they see we consider them short-circuits(we will see this in the example at the end of thelecture)

Typically, a circuit has more capacitors than justcoupling and bypass capacitors. For example, we willhave capacitors coming from the actual transistors.How do we recognize the coupling/bypass capacitors?

• Generally they are pretty large (in the order of µF)


• If you remove these capacitors from the circuit, theAC signal path can be broken (for example, ifinstead of CG, we had an open-circuit no signalwould arrive to the amplifier). Also, if you removethem, the AC gain generally drops (for example, ifwe remove CS, at the signal frequency we have adegenerated common-source amplifier instead of anon-degenerated).


Discrete common-sourceamplifier: AC analysis

We want to perform the AC analysis at frequencies forwhich the coupling and bypass capacitors act as shorts.Shorting the coupling and bypass capacitors we have,

RDrogmvgsvgsvin

vout

RGG

This is very similar to the small-signal model for thecommon source amplifier (with the exception of RGG)

1. Voltage gain: Since RGG is in parallel with vin, wecan ignore RGG for the analysis and then,

Av =vout

vin

= −gm (RD ‖ ro)

2. Input resistance: The input resistance is justRGG in parallel with the resistance looking into thegate of the transistor (which is infinite).

Rin = RGG

3. Output resistance: The output resistance is thesame as for the common-source amplifier.

Rout = RD ‖ ro


Discrete common-sourceamplifier: equivalent AC

model

An equivalent AC model for this amplifier is:

Rin

vout

vin

Rout

vRin AvvRin

where where Av = −gm (RD ‖ ro), Rin = RGG andRout = RD ‖ ro.

This is a quite useful high-level model. We will makeuse of it when we study multistage amplifiers.


Discrete common-sourceamplifier: Loading effects

We now consider a common-emitter amplifier with

• non-zero source impedance

• non-infinite load impedance

RS CS

RD

RL

vout

vin RG2

RG1

CG

CD

VDD

Rs

The DC analysis is the same that when Rs = 0 andRL = ∞.

To compute the small-signal AC gain we use theequivalent AC model we derived for the idealcase(Rs = 0 and RL = ∞).

Rin

vout

vin

Rout

vRin Av,idealvRin RL

Rs


The gain is,

vout = vinRin

Rin + RsAv,ideal

RL

RL + Rout= −vingmRout

Rin

Rin + Rs

RL

Rout + RL

which is just

Av =vout

vin= −gm

RGG

RGG + Rs(RD ‖ RL ‖ ro)

To have a high-gain amplifier one must reduce thesignal lost in the input and output divider. This meanshigh input resistance (or high RGG) and low outputresistance (or small RD).


common-source example

Example Design the amplifier in the figure to have thefollowing characteristics:

• |vout/vin| ≥ 25 at intermediate frequencies

• load is RL = 50kΩ

• output must swing 4V peak-to-peak

• Supply is 5V

• Input source has Rs = 1kΩ

• Hand analysis assume µnCox = 200µA/V2,Vt = 0.75, λ = 0.

• coupling and bypass capacitors are 10µF

RS CS

RD

RL

vout

vin RG2

RG1

CG

CD

VDD

Rs


There are many ways to design this amplifier. Here wejust show a possible way but keep in mind that it is notthe only way.

To reduce the number of components and simplify theproblem, we will design the circuit with RS = 0 and nobypass capacitor CS.

1. We start by looking at the gain specification. Thesmall-signal gain is given by,

Av = −gmRGG

RGG + Rs(RD ‖ RL)

where we have assumed ro = ∞. We now make twoassumptions:

• We assume we can make RGG sufficiently largeso RGG/(RGG + Rs) ≈ 1

• We assume we have Rout RL so thatRD ‖ RL ≈ RD.


With those assumptions we can approximate thegain expression by,

Av ≈ −gmRD = − 2VRD

VGS − Vt(1)

Since we also have a requirement on the swing of4V peak-to-peak, we must have VRD

≥ 2V. Thisrequirement together with the gain requirementimposes a limit on the effective gate overdrive(VGS − Vt). To compensate for the gain loss due toloading we will design for an absolute gain of atleast 40V/V (this is arbitrary!). Then going toequation (1), we have,

VGS − Vt ≤ −2 · 2V

−40= 100mV

We choose VGS − Vt = 100mV. Since Vt = 0.75V,this means VGS = 0.85V.

2. Now we continue with the swing requirement. Weneed a swing VM = 2V. We have two limits on VM

VM ≤ IDRD VM ≤ VDD − IDRD − VGS + Vt

We need then

IDRD ≥ 2VIDRD ≤ 2.9V

We choose a point in the middle so IDRD = 2.5V.Now we choose a value for RD. Since we made theassumption RD RL, we have RD 50kΩ, orequivalently RD ≤ 5kΩ. We choose RD = 2.5kΩand thus ID = 1mA.


3. Since we have the DC drain current and gateoverdrive voltage, we can design the transistordimensions. Since we assumed that the transistor isin saturation, we have,

ID = k (VGS − Vt)2

so k = 1mA/(0.1V)2 = 100mA/V2.

1

2µnCox

W

L= 100mA/V2

Since µnCox = 200µA/V2, this meansW/L = 1000. We can choose L = 1µm andW = 1000µm.

4. Now, we can compute the biasing networkRG1 − RG2. We made the assumption thatRG1 ‖ RG2 Rs and since we have VS = 0.85V,we have,

RG1 ‖ RG2 ≥ 10kΩRG2

RG1 + RG2=

0.85

5

Solving the two equations above we haveRG1 = 58.8kΩ, RG2 = 11.7kΩ

The final circuit becomes:


50kΩ1kΩ

2.5kΩ

vout

vin 11.7kΩ

58.8kΩ

CG

CD

5V

Now we need to check that the design requirements aremet.

• VG is just given by a voltage divider RG1 − RG2 andit is exactly 0.85V

• Then VGS − Vt = 100mV and the drain current(assuming saturation) is

ID = k′n

W

L(VGS − Vt)

2 = 1mA

• Then the drain voltage is

VD = VDD − IDRD = 5V − 1mA2.5kΩ = 2.5V

• The signal swing at the output is

VM = min1mA2.5kΩ, 5V − 2.5V − 0.1V = 2.4V

which is larger than the required 2V


• The gain is

Av = −gmRGG

RGG + Rs(RD ‖ RL ‖ ro)

= −2mA

0.1V

10kΩ

11kΩ(2.5kΩ ‖ 50kΩ) = −43.3V/V

which meets the requirements

The instantaneous voltages at the transistor nodes forvin = 10mV are:

• Gate voltage

vG = VG + vinRGG

RGG + Rs= 0.85V + 9.1mV sin(ωt)

• Source voltagevS = 0

• Drain voltage

vD = VD + Avvin = 2.5V − 433mV sin(ωt)


common-source example:coupling capacitors

Let’s compute the magnitude of the coupling capacitorsat let’s say f = 1kHz

|ZC | =1

ωC=

1

2π · 103 · 10 · 10−6 ≈ 16Ω

• Note that this is pretty small! For example,capacitor CG is in series with Rs = 1kΩ so atf = 1kHz it makes sense to assume that CG actslike a short.

• To be precise, capacitor CG sees a resistance acrossit RCG

= Rs + Rin. (We will see this in a couple ofweeks)

• Note that at some low frequency (for examplef = 0.01Hz), the capacitor has a large impedanceso we cannot consider it a short-circuit.

• The point here is to realize that after somereasonable frequency (low-cutoff frequency) thesecoupling/bypass capacitors can be considered shortsbecause their impedance is much smaller than theimpedances in the circuit. In approximately twoweeks we will learn how to compute this low-cutofffrequency. For now, just assume they are shorts forthe frequencies of interest in the AC analysis.

fet

Documents