fet biasing 1. introduction for the jfet, the relationship between input and output quantities is...
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FET Biasing
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Introduction
For the JFET, the relationship between input and output quantities is nonlinear due to the squared term in Shockley’s equation.
Nonlinear functions results in curves as obtained for transfer characteristic of a JFET.
Graphical approach will be used to examine the dc analysis for FET because it is most popularly used rather than mathematical approach
The input of BJT and FET controlling variables are the current and the voltage levels respectively
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Introduction
JFETs differ from BJTs:
Nonlinear relationship between input (VGS) and output (ID) JFETs are voltage controlled devices, whereas BJTs are
current controlled
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Introduction
Common FET Biasing Circuits• JFET
– Fixed – Bias – Self-Bias – Voltage-Divider Bias
• Depletion-Type MOSFET– Self-Bias– Voltage-Divider Bias
• Enhancement-Type MOSFET– Feedback Configuration– Voltage-Divider Bias
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General Relationships For all FETs:
For JFETs and Depletion-Type MOSFETs:
For Enhancement-Type MOSFETs:
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AIG 0
SD II
2
P
GSDSSD )
V
V(1II
2)( TGSD VVkI
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Fixed-Bias Configuration The configuration includes the ac levels Vi and Vo and
the coupling capacitors. The resistor is present to ensure that Vi appears at the
input to the FET amplifier for the AC analysis.
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Fixed-Bias Configuration For the DC analysis,
Capacitors are open circuits and
The zero-volt drop across RG permits replacing RG by a short-circuit
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AIG 0 VRARIV GGGRG 0)0(
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Fixed-Bias Configuration
Investigating the input loop
IG=0A, therefore
VRG=IGRG=0V
Applying KVL for the input loop,
-VGG-VGS=0
VGG= -VGS
It is called fixed-bias configuration due to VGG is a fixed
power supply so VGS is fixed
The resulting current,
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2)1(P
GSDSSD V
VII
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Investigating the graphical approach. Using below tables, we can draw the graph
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VGS ID
0 IDSS
0.3VP IDSS/2
0.5 IDSS/4
VP 0mA
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The fixed level of VGS has been superimposed as a
vertical line at
At any point on the vertical line, the level of VG is -VGG---
the level of ID must simply be determined on this vertical
line.
The point where the two curves intersect is the common
solution to the configuration – commonly referrers to as
the quiescent or operating point.
The quiescent level of ID is determine by drawing a
horizontal line from the Q-point to the vertical ID axis.10
GGGS VV
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Output loop
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DDDDDS RIVV
VVS 0
SDDS VVV
SDSD VVV 0SV
DSD VV
SGGS VVV
SGSG VVV 0SV
GSG VV
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Example
Determine VGSQ, IDQ, VDS, VD, VG, VS
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Exercise
Determine IDQ, VGSQ, VDS, VD, VG and VS
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Self Bias Configuration The self-bias configuration eliminates the need for two
dc supplies. The controlling VGS is now determined by the voltage
across the resistor RS
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For the indicated input loop:
Mathematical approach:
rearrange and solve.
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SDGS RIV
2
2
1
1
P
SDDSSD
P
GSDSSD
V
RIII
V
VII
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Graphical approach Draw the device transfer characteristic Draw the network load line
Use to draw straight line.First point,Second point, any point from ID = 0 to ID = IDSS. Choose
the quiescent point obtained at the intersection of the straight line plot and the device characteristic curve.
The quiescent value for ID and VGS can then be determined and used to find the other quantities of interest.
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SDGS RIV 0,0 GSD VI
2
2
SDSSGS
DSSD
RIV
thenI
I
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For output loopApply KVL of output loopUse ID = IS
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RDDDSDSD
SDS
DSDDDDS
VVVVV
RIV
RRIVV
)(
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ExampleDetermine VGSQ, IDQ,VDS,VS,VG and VD.
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ExampleDetermine VGSQ, IDQ, VD,VG,VS and VDS.
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Voltage-Divider Bias The arrangement is the same as BJT but the DC analysis is different In BJT, IB provide link to input and output circuit, in FET VGS does
the same
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Voltage-Divider Bias The source VDD was separated into two equivalent sources to permit
a further separation of the input and output regions of the network.
IG = 0A ,Kirchoff’s current law requires that IR1= IR2 and the series
equivalent circuit appearing to the left of the figure can be used to find the level of VG.
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DD2G
RR
VRV
SDGGS
RSGSG
RIVV
VVV
0
Voltage-Divider Bias
VG can be found using the voltage divider rule :
Using Kirchoff’s Law on the input loop:
Rearranging and using ID =IS:
Again the Q point needs to be established by
plotting a line that intersects the transfer curve.24
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Procedures for plotting
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1. Plot the line: By plotting two points: VGS = VG, ID =0 and VGS = 0, ID = VG/RS
2. Plot the transfer curve by plotting IDSS, VP and calculated values of ID.
3. Where the line intersects the transfer curve is the Q point for the circuit.
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Once the quiescent values of IDQ and VGSQ are determined, the
remaining network analysis can be found.
Output loop:
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2121 RR
VII DDRR
)( SDDDDDDS RIRIVV
DDDDD RIVV
SDS RIV
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Effect of increasing values of RS
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ExampleDetermine IDQ, VGSQ, VD, VS, VDS and VDG.
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ExampleDetermine IDQ, VGSQ, VDS, VD and VS
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