feng-xiang huang a low-cost soc debug platform based on on-chip test architectures
Post on 19-Dec-2015
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Research TreeCombining Scan and
Trace Buffers for Enhancing Real-time Observability in Post-
Silicon Debugging
A Scan Cell Design for Scan-
Based Debugging of an
SoC With Multiple Clock
Domains
NIFD: Non-Intrusive FPGA DebuggerDebugging FPGA
‘Threads’ for Rapid HW/SW Systems
Prototyping
A Design-for-Debug(DfD) for NoC-
based SoC Debugging via NoC
A Low-Cost SOC Debug Platform
Based on On-Chip Test Architecutures
While the complexity of System-on-a-chip (SoC) design keeps growing rapidly, today the need for an efficient approach to catch design errors at silicon stage has become an urgent issues. In this paper we present a platform for silicon debugging that makes use of an existing test architecture and thus can provide many powerful debug features while requiring very low extra overhead. It supports multi0core debugging for general purpose cores in an SOC chip with the capabilities of on-line tracing, hardware breakpoint insertion and cycle-based stepping. An automatic design tool is also together users can easily control debug operations and examine trace results to efficiently identify the root cause of failures in the silicon.
Abstract
Related Work[3]A Retargetable
Embedded In-Circuit Emulation Module for
Microprocessors
[5] Exploiting and I-IP for both Test and Silicon Debug of Microprocessor
Cores
[12]In-System Silicon Validation and Debug
[10] Toward Automatic
Synthesis of SoC Test Platform
[6]A Debug Probe for Concurrently Debugging
Multiple Embedded Cores and Inter-Core Transactions in NoC-
Based Systems
[4]Parameterized Embedded In-Circuit Emulator and Its
Retargetable Debugging Software for
Microprocessor/Microcontroller/DSP Processor
[9]An Embedded Processor Based
SoC Test Platform
[this] A Low-Cost SOC Debug
Platform Based on On-Chip Test Architectures
microprocessor based
Signal Tracer
NoC based
Tool
Low controllability and observability in post-silicon. Even if SoC designers can fetch trace data
。How to determine in what time intervals bugs occurred to get useful data ?
A mechanism able to check multi-core data is needed to find inter-core bugs
What is the problem
They develop a low cost yet very powerful on-chip silicon debug platform. Leveraging on-chip resources
。Embedded CPU, memory, and system bus
Dedicated circuitry。Test Access Mechanism(TAM) Controller。Test bus。IEEE 1149.1 and/or 1500 Wrapped cores
The advantage of the proposed debug platform Testability circuitry has been indispensable Reusable Without using expensive external automatic equipment
Proposed Method
Proposed Debug Platform architecture
1
2
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Clock Gating• Prevent from signal glitch
Hold Control• Suspend the CUD
TAPC• Convert signals for IEEE1500
TAM Controller (Test Access Mechanism)
• Next slide will be presented
AMBA AHB Interface• To communicate with system components through bus
Memory Access Unit TAM as a master, calculates proper addresses to access
the embedded memory
Control Unit TAM as a slave, decode and setup registers to determine
which core to be debugged
TMS Generator Convert these TMS signals to control signals for IEEE 1500
BKT Control Unit Detect triggering conditions
Shift Buffer Unit Receive trace responses of CUD’s from TAM OUT port Restore CUDs’ status via TAM IN port
TAM controller components
Multi-Core Debugging Multi-core debugging is needed to identify inter-core bugs
Multiple cores can be connected to different shift buffers and thus can be accessed simultaneously. Bugs can be identified by observing the sources and destinations of the signals through the
inter-core interconnects.
It is very difficult to implement without these existing test components. Test bus
A set of test buffers
Some required control circuitry
Experimental results Successfully implemented this debug platform on the ARM Versatile/PB926EJ-S
development system
DASTEP
In comparison with the original test platform
The additional debug area overhead is 36840(um2), which translates to about 7300 gates for the 0.13um technology. TAM controller is independent of the umber of CUD’s BKT Control Unit added
Experimental results
Silicon debug is a complicated, time-consuming, but inevitable task for today’s SoC designs. They present a cost-effective debug solution Multiple core debugging is also supported An enhanced DASTEP was developed to help carry out the
debug procedure By reusing existing test components The area overhead of the extra DfD (design for debug) logic
is limited
Conclusions