features description Î application Î - diodes incorporated · features ÎÎ1.62v to 3.6v ......
TRANSCRIPT
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Diodes IncorporatedPI7C9X754 Document Number DS40311 Rev 5-2
FeaturesÎÎ 1.62V to 3.6V with 5V Tolerant Serial Inputs ÎÎ Programmable Sleep Mode with automatic wake-up
à Intel or Motorola Data Bus Interface select ÎÎ Each UART is independently controlled with:
à 16C550 Compatible Register Set à 64-byte Transmit and Receive FIFOs à Transmit and Receive FIFO Level Counters à Programmable TX and RX FIFO Trigger Levels for
DMA and Interrupt Generation → Programmable Receive FIFO Trigger Levels for
Software/Hardware Flow Control → Programmable hysteresis(Table A-D) for Software/
Hardware Flow Control à Automatic RTS/CTS Flow Control à Automatic Xon/Xoff Software Flow Control with
Optional Data Flow Resume by Xon Any Character → DMA Signaling Capability for both Received and
Transmitted Data à RS485 HDX Control Output à RS485 auto address detection à Infrared (IrDA 1.0/1.1) Data Encoder/Decoder à Programmable Data Rate with Prescaler
ÎÎ Up to 16 Mbps Serial Data Rate with 64MHz external clock input ÎÎ Crystal oscillator(up to 24MHz) or external clock(up to
80MHz) inputÎÎ Built in Power-On-Reset circuitÎÎ Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)ÎÎ Halogen and Antimony Free. “Green” Device (Note 3)
DescriptionThe PI7C9X754 (754), is a 1.62V to 3.6V quad Universal Asyn-chronous Receiver and Transmitter (UART) with 5V tolerant se-rial (modem) inputs. The highly integrated device is designed for high bandwidth requirement in communication systems. Each UART has its own 16C550 compatible set of configuration regis-ters, TX and RX FIFOs of 64 bytes, fully programmable transmit and receive FIFO trigger levels, TX and RX FIFO level counters, automatic RTS/CTS hardware flow control with programmable hysteresis, automatic software (Xon/Xoff) flow control, RS-485 half-duplex direction control, Intel or Motorola bus interface and sleep mode for power saving.
ApplicationÎÎ Remote Access ServersÎÎ Ethernet Network to Serial PortsÎÎ Network Management ÎÎ Factory Automation and Process ControlÎÎ Point-of-Sale SystemsÎÎ Multi-port RS-232/RS-422/RS-485 Cards
A product Line ofDiodes Incorporated
PI7C9X754
High Performance 1.62V To 3.6V Quad Uart with 64-Byte FIFO
Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm
antimony compounds.
bPLead-free Green
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Diodes IncorporatedPI7C9X754 Document Number DS40311 Rev 5-2
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PI7C9X754
Block Diagram PI7C9X754 BLOCK DIAGRAM
HostInterface
Crystal OSC/Buffer
TX & RX
UARTRegs
UART-A
IR 1.0/1.1
ENDEC
TXA,RXA,IRTXA, DTRA#
DSRA#, RTSA#
64 Byte TX FIFO
64 Byte RX FIFOBRG
UART-B
UART-C
UART-D
CTSA#,CDA#,RIA#
TXD,RXD,IRTXD,DTRD#
DSRD#, RTSD#
CTSD#,CDD#,RID#
XTAL1
XTAL2
CHCCLK
Reset
A[2:0]
D[7:0]
IOR#
IOW#
CSD#
INTD
16/68#
CSA#
CSB#
CSC#
INTA
INTB
INTC
TXRDY# A-D
RXRDY# A-D
INTSEL
CLKSEL
FSRS#
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PI7C9X754
Pin Configuration 100-MQFP
9
10111213141516
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50494847
4645
44434241
4039383736
35343332
31
81828384
8586
87888990
9192939495
96979899
100
RXRDYC#
CDC#RIC#
GND
RESET
TXRDY#RXRDY#
A0
CHCCLKXTAL2
CLKSELRXB
16/68#
RIB#
PI7C9X754100-MQFP
N.C
.
N.C
.
N.C
.N
.C.
TX
RD
YA#
IRT
XA
DS
RA
#
CT
SA
#D
TR
A#
VC
CR
TS
A#
INTA
/IR
Q#
CS
A#
/CS
#T
XA
IOW
#/R
/W#
TX
B
CS
B#
/A3
INT
B/N
.C.
RT
SB
#G
ND
DT
RB
#C
TS
B#
DS
RB
#
IRT
XB
TX
RD
YB
#
N.C
.
N.C
.
N.C
.N
.C.
N.C
.
RXC
XTAL1
A1A2
CDB#RXRDYB#
N.C
.
N.C
.
N.C
.N
.C.
FS
RS
#IR
TX
D
DS
RD
#C
TS
D#
DT
RD
#
VC
C
RT
SD
#
CS
D#
/ N
.C.
TX
C
INT
D/
N.C
.
IOR
#/
N.C
.
CS
C#
/A4
INT
C/
N.C
.R
TS
C#
GN
D
DT
RC
#
CT
SC
#D
SR
C#
IRT
XC
TX
RD
YC
#
N.C
.
N.C
.
N.C
.N
.C.
N.C
.
TX
D
TXRDYD#RXRDYD#
CDD#
RID#RXDVCC
INTSELD0D1D2
D3D4D5
D6
D7GNDRXA
RIA#CDA#
RXRDYA#
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PI7C9X754
Pin Configuration 64-LQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
333231
DSRD#
GND
CTSD#DTRD
TXD
RTSD#
INTD
INTCRTSC#
CSC#
VCC
PI7C9X75464-LQFP
DS
RB
#C
DB
#
RX
BR
IB#
CL
KS
EL
A2
A1
A0
XTA
L1
XTA
L2
RE
SE
TG
ND
RX
CR
IC#
CD
C#
DS
RC
#
CSD#
IOR#
TXC
DTRC#CTSC#
CD
A#
RIA
#R
XA
GN
D
D7
CD
D#
D5
D3
D0
D4
D1
VC
C
RX
DR
ID#
D6
D2
DSRA#
CTSA#DTRA#
VCCRTSA#
INTACSA#TXA
IOW#TXB
CSB#INTB
RTSB#
GNDDTRB#CTSB#
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
29
30
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
GND
CTSD#
RXD
TXD
RTSD#
INTD
INTC
RTSC#
CSC#
PI7C9X75448-TQFN
16
/68
#
RX
B
VC
C
CT
SC
#
A2
A1
A0
XTA
L1
XTA
L2
RE
SE
T
GN
D
RX
C
CSD#
IOR#
TXC
RX
A
GN
D
D7
D5
D3
D0
D4
D1
VC
C
INT
SE
L
D6
D2
CTSA#
VCC
RTSA#
INTA
CSA#
TXA
IOW#
TXB
CSB#
INTB
RTSB#
CTSB#
Pin Configuration 48-TQFN
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PI7C9X754
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
2021 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40393837363534333231
RX
RD
YC
#
CD
C#
RIC
#
GN
D
RE
SE
T
TX
RD
Y#
A0
CL
KS
EL
XTA
L2
RX
B
PI7C9X75480-LQFP
Intel Mode only
N.C.
N.C.
DSRA#
CTSA#
DTRA#
VCC
RTSA#
INTB
CSA#
TXA
IOW#
TXB
CSB#
INTA
RTSB#
GND
DTRB#
CTSB#
DSRB#
N.C.
N.C.
N.C.
N.C
.
N.C
.
N.C
.
N.C
.
RX
C
XTA
L1
A1
A2
CD
B#
N.C
.
N.C
.
DSRD#
CTSD#
DTRD#
VCC
RTSD#
CSD#
TXC
INTD
IOR#
CSC#
INTC
RTSC#
GND
DTRC#
CTSC#
DSRC#
N.C.
TXD
CD
D#
RID
#
RX
D
VC
C
INT
SE
L
D0
D1
D2
D3
D4
D5
D6
D7
GN
D
RX
A
RIA
#
CD
A#
RIB
#
N.C
.
Pin Configuration 80-LQFP
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PI7C9X754
Pin Description
Pin Name
48-QFPPin#
64-QFPPin#
80-QFPPin#
100-QFPPin# Type Description
Data Bus InterfaceA2A1A0
151617
222324
282930
373839
IAddress data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A-D during a data bus transaction.
D7D6D5D4D3D2D1D0
4645444342414039
6059585756555453
7574737271706968
9594939291908988
I/O Data bus lines [7:0] (bidirectional).
IOR# 29 40 51 66 I
When 16/68# pin is HIGH, the Intel bus interface is selected and this input becomes read strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte on the data bus to allow the host processor to read it on the rising edge.When 16/68# pin is LOW, the Motorola bus interface is selected and this input is not used and should be connected to VCC.
IOW# (R/W#) 7 9 11 15 I
When 16/68# pin is HIGH, it selects Intel bus interface and this input becomes write strobe (active low). The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines.When 16/68# pin is LOW, the Motorola bus interface is se-lected and this input becomes read (logic 1) and write (logic 0) signal.
CSA#(CS#) 5 7 9 12 I
When 16/68# pin is HIGH, this input is chip select A (active low) to enable channel A in the device.When 16/68# pin is LOW, this input becomes the chip se-lected (active low) for the Motorola bus interface.
CSB#(A3) 9 11 13 17 I
When 16/68# pin is HIGH, this input is chip select B (active low) to enable channel B in the device.When 16/68# pin is LOW, this input becomes address line A3 which is used for channel selection in the Motorola bus interface.
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Pin Name
48-QFPPin#
64-QFPPin#
80-QFPPin#
100-QFPPin# Type Description
CSC#(A4) 27 38 49 64 I
When 16/68# pin is HIGH, this input is chip selected C (ac-tive low) to enable channel C in the device.When 16/68# pin is LOW, this input becomes address line A4 which is used for channel selection in the Motorola bus interface.
CSD# (VCC) 31 42 53 68 I
When 16/68# pin is HIGH, this input is chip select D (active low) to enable channel D in the device.When 16/68# pin is LOW, this input is not used and should be connected VCC.
INTA (IRQ#) 4 6 8 12 O (OD)
When 16/68# pin is HIGH for Intel bus interface, this output becomes channel A interrupt output. The output state is de-fined by the user and through the software setting of MCR[3]. INTA is set to a logic 0 (default). See MCR[3].When 16/68# pin is LOW for Motorola bus interface this out-put becomes device interrupt output (active low, open drain). An external pull-up resistor is required for proper operation.
INTBINTCINTD (N.C.)
102632
123743
144854
186369
O
When 16/68# pin is HIGH for Intel bus interface, these outputs become the interrupt output for channel B, C and D. The output state is defined by the user through the software setting of MCR[3]. The interrupt outputs are set to the active mode when MCR[3] is set to a logic 1 and are set to the three state mode when MCR[3] is set to a logic 0 (default). See MCR[3].When 16/68# pin is LOW for Motorola bus interface, these outputs ate unused and will stay at logic zero level. Leave these outputs unconnected.
INTSEL 38 - 67 87 I
Interrupt Select ( active high, input with internal pull-down.)When 16/68# pin is HIGH for Intel bus interface, this pin can be used in conjunction with MCR bit-3 to enable the interrupt outputs. Interrupt outputs are enabled continuously when this pin is HIGH. MCR bit-3 enables and disables the inter-rupt output pins. In this mode, MCR bit-3 is set to a logic 1 to enable the continuous outputs. See MCR bit-3 description for full detail. This pin must be LOW in the Motorola bus interface mode. For the 64 pin packages, this pin is bonded to GND internally in the PI7C9X754 and therefore requires set-ting MCR bit-3 for enabling the interrupt output pins.
TXRDYA#TXRDYB#TXRDYC#TXRDYD#
----
----
----
5255681
OUART channels A-D Transmitter Ready (active low). The out-puts provide the TXFIFO/THR status for transmit channels A-D. If these outputs are unused, leave them unconnected.
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Pin Name
48-QFPPin#
64-QFPPin#
80-QFPPin#
100-QFPPin# Type Description
RXRDYA#RXRDYB#RXRDYC#RXRDYD#
----
----
----
100315082
OUART channels A-D Receiver Ready (active low). This output provides the RXFIFO/RHR status for receive channels A-D. If these outputs are unused, leave them unconnected.
TXRDY# - - 35 45 OTransmitter Ready (active low). This output is a logically ANDed status of TXRDY# A-D. If this output is unused, leave it unconnected.
RXRDY# - - 34 44 OTransmitter Ready (active low). This output is a logically AN-Ded status of RXRDY# A-D. If this output is unused, leave it unconnected.
FSRS# - - - 76 I
FIFO Status Register Select (active low input with internal pull-up)The content of the FSTAT register is placed on the data bus when this pin becomes active. However it should be noted, D0-D3 contain the inverted logic states of TXRDY# A-D pins and D4-D7 the logic states (uninverted) of RXRDY# A-D pins. A valid address is not required when reading this status register.
Modem Or Serial I/O Interface
TXATXBTXCTXD
682830
8103941
10125052
14166567
O
UART channels A-D Transmit Data and infrared transmit data. Standard transmit and receive interface is enabled when ASR[1] = 0. In this mode, the TX signal will be a logic 1 dur-ing reset, or idle (no data). Infrared IrDA transmit and receive interface is enabled when ASR[1] = 1. In the infrared mode, the inactive state (no data) for the Infrared encoder/decoder interface is a logic 0.
IRTXAIRTXBIRTXCIRTXD
----
----
----
6245775
O
UART channel A-D Infrared Transmit Data. The inactive state (no data) for the Infrared encoder/decoder interface is LOW. Regardless of the logic state of ASR bit-1, this pin will be operating in the Infrared mode.
RXARXBRXCRXD
48132236
62202951
77253765
97344785
I UART channel A-D Receive Data or infrared receive data. Normal receive data input must idle HIGH.
RTSA#RTSB#RTSC#RTSD#
3112533
5133644
7154755
11196270
O
UART channels A-D Request-to-Send (active low) or general purpose output. This output must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1], and IER[6]. If these outputs are not used, leave them unconnected.
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Pin Name
48-QFPPin#
64-QFPPin#
80-QFPPin#
100-QFPPin# Type Description
CTSA#CTSB#CTSC#CTSD#
1122335
2163347
4184458
8225973
I
URAT channels A-D Clear-to-Send (active low) or general purpose input. It can be used for auto CTS flow control, see EFR[7], and IER[7]. These input should be connected to VCC when not used.
DTRA#DTRB#DTRC#DTRD#
----
3153446
5174557
9216072
OUART channels A-D Data-Terminal-Ready (active low) or general purpose output. If these outputs are not used, leave them unconnected.
DSRA#DSRB#DSRC#DSRD#
----
1173248
3194359
7235874
IUART channels A-D Data-Set-Ready (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART.
CDA#CDB#CDC#CDD#
----
64183149
79233963
99324983
IUART channels A-D Carrier-Detect (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART.
RIA#RIB#RIC#RID#
----
63193050
78243864
98334884
IUART channels A-D Ring-Indicator (active low) or general purpose input. This input should be connected to VCC when not used. This input has no effect on the UART.
Ancillary Signals
XTAL1 18 25 31 40 ICrystal or external clock input. Caution: this input is not 5V tolerant.
XTAL2 19 26 32 41 O Crystal or buffered clock output.
16/68# 14 - - 36 I
Intel or Motorola Bus Select (input with internal pull-up).When 16/68# pin is HIGH, 16 or Intel Mode, the device will operate in the Intel bus type of interface.When 16/68# pin is LOW, 68 or Motorola mode, the device will operate in the Motorola bus type of interface.Motorola bus interface is not available on the 64 pin package.
CLKSEL - 21 26 35 I
Baud-Rate-Generator Input Clock Prescaler Select for chan-nels A-D. This input is only sampled during power up or a reset. Connect to VCC for divide by 1 (default) and GND for divide by 4. MCR[7] can over-ride the state of this pin follow-ing a reset of initialization.
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PI7C9X754
Pin Name
48-QFPPin#
64-QFPPin#
80-QFPPin#
100-QFPPin# Type Description
CHCCLK - - - 42 I
This input provide the clock for URAT channel C. An exter-nal 16X baud clock or the crystal oscillator's output, XTAL2, must be connected to this pin for normal operation. This in-put may also be used with MIDI (Musical Instrument Digital Interface) applications when an external MIMD clock is pro-vide. This pin is only available in the 100-pin QFP package.
RESET (RESET#) 20 27 33 43 I
When 16/68# pin is HIGH for Intel bus interface, this input becomes the Reset pin (active high). In this case, a 40 ns minimum HIGH pulse on this pin will reset the internal registers and all outputs. The UART transmitter output will be held HIGH, the receiver input will be ignores and outputs are reset during reset period (Table 17).When 16/68# pin is at LOW for Motorola bus interface, this input becomes Reset# pin (active low). This pin functions similarly, but instead of a HIGH pulse, a 40 ns minimum LOW pulse will reset the internal registers an outputs.Motorola bus interface is not available on the 64 pin package.
VCC 2, 24, 37 4, 35, 52 6, 46, 66 10, 61, 86 Pwr1.62V to 3.6V power supply. All inputs, except XTAL1, are 5V tolerant.
GND 21, 47 14, 28, 45, 61
16, 36, 56, 76
20, 46, 71, 96 Pwr Power supply common, ground.
GND Center Pad N/A N/A N/A Pwr
The center pad on the backside of the QFN package is metal-lic and should be connected to GND on the PCB. The thermal pad size on the PCB should be the approximate size of this center pad and should be solder mask defined. The solder mask opening should be at least 0.0025" inwards from the edge of the PCB thermal pad.
N.C. - -
1, 2, 20, 21, 22, 27, 40, 41, 42, 60, 61, 62,
80
No Connection, These pins are not used in either the Intel or Motorola bus modes.
Pin type: I=Input, O=Output, I/O=Input/Output, OD= Output Open Drain.
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PI7C9X754
Functional DescriptionThe PI7C9X754 integrates the functions of 4 enhanced 16550 UARTs. Each UART channel has its own 16550 UART compatible con-figuration register set for individual channel control, status, and data transfer. Additionally, each UART channel has 64-byte of trans-mit and receive FIFOs, automatic RTS/CTS hardware flow control with hysteresis control, automatic Xon/Xoff and special character software flow control, programmable transmit and receive FIFO trigger levels, FIFO level counters, infrared encoder and decoder (IrDA ver. 1.0 and 1.1), programmable baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 16Mbps with 4X sampling clock. The PI7C9X754 is a 1.62-3.6V device with 5 volt tolerant inputs (except XTAL1).The PI7C9X754 comes with four different packages: 100-pin QFP, 80-pin LQFP,64-pin LQFP and 48-pin QFN. The 64-pin and 80-pin packages only offer the Intel mode interface, but the 48 and 100 pin packages offer an additional 68 mode interface which allows easy integration with Motorola processors.The 100 pin package provides additional FIFO status outputs (TXRDY# and RXRDY# A-D), separate infrared transmit data outputs (IRTX A-D) and channel C external clock input (CHCCLK).
1. Trigger LevelsThe PI7C9X754 provides independent selectable and programmable trigger levels for both Receiver and transmitter DMA and inter-rupt generation. After reset, both transmitter and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of one character. The selectable trigger levels are controlled via Register TLR(if TLR is non-zero) or (if TLR is zero) via FIFO Control Register(FCR) and Feature Control Register(FCTR). Refer to Table 1.
Table 1. Transmit and Receive FIFO Trigger Table and Level SelectionTrigger FCTR
BIT-5FCTRBIT-4
FCRBIT-7
FCRBIT-6
FCRBIT-5
FCRBIT-4
Receive Trigger Level Transmit Trigger Level
Table-A 0 00011
0101
0 01(Default)
4814
1(Default)
Table-B 0 1
0011
0101
0011
0101
8162428
168
2430
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RXFIFO
Figure 1. Auto �ow control (Auto-RTS and Auto-CTS) example
TXFIFO
SERIAL TOPARALLEL
FLOWCONTROL
PARALLELTO SERIAL
FLOWCONTROL
RXFIFO
TXFIFO
SERIAL TOPARALLEL
FLOWCONTROL
PARALLELTO SERIAL
FLOWCONTROL
UART 1 UART 2
TX
TX
RX
RX
RTS
RTS
CTS
CTS
Table-C 1 0
0011
0101
0011
0101
8165660
8163256
Table-D 1 1 X X X X Programmable via RX-TRG register
Programmable via TX-TRG register
2. Hardware Flow ControlHardware flow control is comprised of Auto-CTS and Auto-RTS (see Figure 1). Auto-CTS and Auto-RTS can be enabled/disabled independently by programming EFR[7:6].With Auto-CTS, CTS must be active before the UART can transmit data.Auto-RTS only activates the RTS output when there is enough room in the FIFO to receive data and de-activates the RTS output when the RX FIFO is sufficiently full. The halt and resume trigger levels is controlled by FCR and FCTR bits.If both Auto-CTS and Auto-RTS are enabled, when RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has empty space. Thus, overrun errors are eliminated during hardware flow control. If not enabled, overrun errors occur if the transmit data rate exceeds the receive FIFO servicing latency.
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RX
INT
Start
Figure 2. RTS functional timing
ReceiveFIFORead
characterN
Stop Start characterN + 1
Stop Start
1 2 N N + 1
002aab040
(1) N = receiver FIFO trigger level.(2) The two blocks in dashed lines cover the case where an additional character is sent.
2.1 Auto RTS Hardware Flow Control OperationFigure 2 shows RTS# functional timing. The RTS# output pin is used to request remote unit to suspend/resume data transmission. The flow control features are individually selected to fit specific application requirement:•Enable auto RTS flow control using EFR bit-6.•The auto RTS function must be started by asserting the RTS# output pin (MCR bit-1 to a logic 1) after it is enabled. With the Auto RTS function enabled, the RTS# output pin will be de-asserted (HIGH) when the FIFO reaches the halt level. The halting level is setting by TCR[3:0](if non-zero) or is the next trigger level for Trigger Tables A-C (See Table 1), or is the RX trigger level plus the hysteresis level for Trigger Table D.The RTS# output pin will be asserted (LOW) again after the FIFO is unloaded to programmed resume level. The resume level is setting by TCR[7:4](if non-zero), or is the next trigger level below the programmed trigger level for Trigger Table A-C, or is the RX trigger level minus the hysteresis level if Table D is selected. However, even under these conditions, the 754 will continue to accept data until the receive FIFO is full if the remote UART transmitter continues to send data.•If used, enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the RTS# pin makes a transition: ISR bit-5 will be set to 1.
2.2 Auto CTS Flow ControlTThe CTS pin is monitored to suspend/restart local transmitter. The flow control features are individually selected to fit specific ap-plication requirement:•Enable auto CTS flow control using EFR bit-7. With the Auto CTS function enabled, the UART will suspend transmission as soon as the stop bit of the character in the Transmit Shift Register has been shifted out. Transmission is resumed after the CTS# input is re-asserted (LOW), indicating more data may be sent.•If used, enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the CTS# pin makes a transition: ISR bit-5 will be set to a logic 1, and UART will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input returns LOW, indicating more data may be sent.
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I2C-bus Addressing
TX Start
Figure 3. CTS functional timing
characterN
Stop Stop
002aab041
(1) When CTS is LOW, the transmitter keeps sending serial data out.(2) When CTS goes HIGH before the middle of the last stop bit of the current character, the transmitter finishes sending the currentcharacter, but it does not send the next character.(3) When CTS goes from HIGH to LOW, the transmitter begins sending data again.
Start bit 0 to bit 7
CTS
3 Software Flow ControlSoftware flow control is enabled through the Enhanced Features Register and the Modem Control Register. Different combinations of software flow control can be enabled by setting different combinations of EFR[3:0]. Table 1 shows software flow control options.
Table 2. Software flow control options (EFR[3:0])
EFR[3] EFR[2] EFR[1] EFR[0] TX, RX software flow control
0 0 x x No transmit flow control
1 0 x x Transmit Xon1, Xoff1
0 1 x x Transmit Xon2, Xoff2
1 1 x x Transmit Xon1 and Xon2, Xoff1 and Xoff2
x x 0 0 No receive flow control
x x 1 0 Receiver compares Xon1, Xoff1
x x 0 1 Receiver compares Xon2, Xoff2
1 0 1 1 Transmit Xon1, Xoff1 receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0 1 1 1 Transmit Xon2, Xoff2 receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1 1 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2 receiver compares Xon1 and Xon2, Xoff1 and Xoff2
There are two other enhanced features relating to software flow control:• Xon Any function (MCR[5]): Receiving any character will resume operation after recognizing the Xoff character. It is possible that an Xon1 character is recognized as an Xon Any character, which could cause an Xon2 character to be written to the RX FIFO.
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• Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the special character sets the Xoff interrupt (ISR[4]) but does not halt transmission. The Xoff interrupt is cleared by a read of the Interrupt Status Register (ISR). The special character is transferred to the RX FIFO.
3.1 Receive Flow ControlWhen software flow control operation is enabled, UART will compare incoming data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2 must be received sequentially). When the correct Xoff characters are received, transmission is halted after completing transmission of the current character. Xoff detection also sets ISR[4] (if enabled via IER[5]) and causes IRCE#to go LOW.To resume transmission, an Xon1/Xon2 character must be received (in certain cases Xon1 and Xon2 must be received sequentially). When the correct Xon characters are received, ISR[4] is cleared, and the Xoff interrupt disappears.
3.2 Transmit Flow ControlXoff1/Xoff2 character is transmitted after the receive FIFO crosses the programmed halting level in TCR[3:0](if non-zero) or pro-grammed receiver trigger level (for all trigger tables A-D). Xon1/Xon2 character is transmitted as soon as receive FIFO is below the programmed resuming level in TCR[7:4](if non-zero) or less than one trigger level below the programmed receiver trigger level (for Trigger Tables A, B, and C) or when receive FIFO is less than the trigger level minus the hysteresis value (for Trigger Table D). This hysteresis value is the same as the Auto RTS Hysteresis value in Table 3.
Table 3. Selectable Hysteresis Levels When Trigger Table-D IS Selected
FCTR BIT-3 FCTR BIT-2 FCTR BIT-1 FCTR BIT-0RTS Hysteresis
(Characters)
0 0 0 0 0
0 0 0 1 +/- 4
0 0 1 0 +/- 6
0 0 1 1 +/- 8
0 1 0 0 +/- 8
0 1 0 1 +/- 16
0 1 1 0 +/- 24
0 1 1 1 +/- 32
1 1 0 0 +/- 12
1 1 0 1 +/- 20
1 1 1 0 +/- 28
1 1 1 1 +/- 36
1 0 0 0 +/- 40
1 0 0 1 +/- 44
1 0 1 0 +/- 48
1 0 1 1 +/- 52
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TRANSMIT FIFO
PARALLEL-TO-SERIAL
SERIAL-TO-PARALLEL
Xon1 WORD
Xon2 WORD
Xoff1 WORD
Xoff2 WORD
Figure 4. Example of so�ware �ow control
RECEIVE FIFO
SERIAL-TO-PARALLEL
PARALLEL-TO-SERIAL
Xon1 WORD
Xon2 WORD
Xoff1 WORD
Xoff2 WORD
data
Xoff–Xon–Xoff
compareprogrammed
Xon-Xoffcharacters
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4. Hardware Reset, Power-On Reset (POR) and Software ResetThese three reset methods are identical and will reset the internal registers as indicated in Table 4.Table 4 summarizes the state of register after reset.
Table 4. UART Reset Conditions
Register Reset state
DLL Bits 7-0 = 0x01
DLM Bits 7-0 = 0x00
DLD Bits 7-0 = 0x00
RHR Bits 7-0 = 0xXX
THR Bits 7-0 = 0xXX
IER Bits 7-0 = 0x00
FCR Bits 7-0 = 0x00
ISR Bits 7-0 = 0x01
LCR Bits 7-0 = 0x1D
MCR Bits 7-0 = 0x00
LSR Bits 7-0 = 0x60
MSRBits 3-0 = logic 0Bits 7-4 = logic level of the inputs
SPR Bits 7-0 = 0xFF
FCTR Bits 7-0 = 0x20
EFR Bits 7-0 = 0x00
TRG Bits 7-0 = 0x00
FC Bits 7-0 = 0x00
TCR Bits 7-0 = 0x00
TLR Bits 7-0 = 0x00
FSRDY Bits 7-0 = 0x0F
XON1 Bits 7-0 = 0x00
XON2 Bits 7-0 = 0x00
XOFF1 Bits 7-0 = 0x00
XOFF2 Bits 7-0 = 0x00
Remark: Registers DLL, DLH, APR, XON1, XON2, XOFF1, XOFF2 are not reset by the top-level reset signal RESET, Software Reset, that is, they hold their initial-ization values during reset.
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5. InterruptsThe UART has interrupt generation and prioritization (seven prioritized levels of interrupts) capability. The interrupt enable registers (IER and IOIntEna) enable each of the seven types of interrupts and the INT signal in response to an interrupt generation. When an interrupt is generated, the ISR indicates that an interrupt is pending and provides the type of interrupt through ISR[5:0]. Table 4 sum-marizes the interrupt control functions.
Table 6. Interrupt Source and Priority Level
ISR[5:0] Priority level Interrupt type Interrupt source
00 0001 None None None
00 0110 1 Receiver line status Overrun Error (OE), Framing Error (FE), Parity Error (PE), or Break Interrupt (BI) errors occur in characters in the RX FIFO
00 1100 3 RX time-out Stale data in RX FIFO
00 0100 2 RHR interrupt Receive data ready (FIFO disable) or RX FIFO above trigger level (FIFO enable)
00 0010 4 THR interrupt Transmit FIFO empty (FIFO disable) or TX FIFO passes above trigger level (FIFO enable)
00 0000 5 Modem status Change of state of modem input pins
01 0000 6 Xoff interrupt Receive Xoff character(s)/special character
10 0000 7 CTS, RTS RTS pin or CTS pin change state from active (LOW) to inactive (HIGH)
It is important to note that for the framing error, parity error, and break conditions, Line Status Register bit 7 (LSR[7]) generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always represent the error status for the received character at the top of the RX FIFO. Reading the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon flow character detec-tion. If a special character detection caused the interrupt, the interrupt is cleared by a read of the ISR.
Table 5. Output Signals after Reset
Signal Reset state
TX HIGH
RTS/DTR HIGH
IRTX LOW
RXRDY# HIGH
TXRDY# LOWINT Hi-Z (INTSEL=LOW) or LOW (INTSEL=HIGH)
IRQ# Hi-Z (INTSEL=LOW)
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5.1 Interrupt GenerationÎÎ LSR is by any of the LSR bits 1, 2, 3, 4 and 7.ÎÎ RXRDY is by RX trigger level.ÎÎ RXRDY Time-out is by a 4-char delay timer.ÎÎ TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control).ÎÎ MSR is by any of the MSR bits 0, 1, 2 and 3.ÎÎ Receive Xoff/Special character is by detection of a Xoff or Special character.ÎÎ CTS# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control.ÎÎ RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control.
5.2 Interrupt ClearingÎÎ LSR interrupt is cleared by reading all characters with errors out of the RX FIFO if it is Frame/Parity/Break Error, and is cleared
by reading LSR if it is Overrun Error.ÎÎ RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.ÎÎ RXRDY Time-out interrupt is cleared by reading RHR.ÎÎ TXRDY interrupt is cleared by a read to the ISR register or writing to THR.ÎÎ MSR interrupt is cleared by a read to the MSR register.ÎÎ Xoff interrupt is cleared when Xon character(s) is received or reading ISR.ÎÎ Special character interrupt is cleared by a read to ISRÎÎ RTS# and CTS# flow control interrupts are cleared by a read to the MSR register
5.3 Interrupt Mode OperationIn Interrupt mode (if any bit of IER[3:0] is 1) the host is informed of the status of the receiver and transmitter by an interrupt signal, IRQ# Therefore, it is not necessary to continuously poll the Line Status Register (LSR) to see if any interrupt needs to be serviced. Figure 5 shows Interrupt mode operation.
read ISR
HOST
11 1 1
THR RHR
ISR
IER
IRQ#
Figure 5. Interrupt mode operation
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5.4 Polled Mode OperationIn Polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be checked by polling the Line Status Register (LSR). This mode is an alternative to the FIFO Interrupt mode of operation where the status of the receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 6 shows FIFO Polled mode operation.
read LSR
HOST
00 0 0
THR RHR
LSR
IER
Figure 6. FIFO Polled mode operation
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6 Sleep ModeSleep mode is an enhanced feature of the UART. It is enabled when EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when:• The serial data input line, RX, is idle (see Section 8 “Break and time-out conditions”).• The TX FIFO and TX shift register are empty.• There are no interrupts pending except THR.• Modem inputs are not togglingRemark: Sleep mode will not be entered if there is data in the RX FIFO.In Sleep mode, the clock to the UART is stopped. Since most registers are clocked using these clocks, the power consumption is greatly reduced. The UART will wake up when any change is detected on the RX line, when there is any change in the state of the modem input pins, or if data is written to the TX FIFO.Remark: Writing to the divisor latches DLL and DLH to set the baud clock must not be done during Sleep mode. Therefore, it is advis-able to disable Sleep mode using IER[4] before writing to DLL or DLH.
7. DMA SignalingThere are two modes of DMA operation, DMA mode 0 or 1, selected by FCR[3]. In DMA mode 0 or FIFO disable(FCR[0]=0), DMA occurs in single character transfers. In DMA mode 1, multi-character DMA transfers are managed to relieve the processor for longer periods of time. Single DMA Transfers(DMA mode 0/FIFO disable):Transmitter: When empty, the TXRDY# signal becomes active. TXRDY# will go inactive after one character has been loaded into it.Receiver: RXRDY# is active when there is at least one character in the FIFO. It becomes inactive when the receiver is empty.
Figure 7. Shows TXRDY# and RXRDY# in DMA mode 0/FIFO disable
FIFO Empty
At Least One Location Filled
TX RX
wrptr
wrptr
TXRDY
TXRDY RXRDY
RXRDY
At Least One Location Filled
rdptr
rdptr FIFO Empty
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Block DMA Transfers(DMA mode 1):Transmitter: TXRDY# is active when a trigger level number of spaces are available. It becomes inactive when the FIFO is full.Receiver: RXRDY# becomes active when the trigger level has been reached or when a timeout interrupt occurs. It will go inactive when the FIFO is empty or an error in the RX FIFO is flagged by LSR(7).
8. Break and Time-out ConditionWhen the UART receives a number of characters and these data are not enough to set off the receive interrupt (because they do not reach the receive trigger level), the UART will generate a time-out interrupt instead, 4 character times after the last character is re-ceived. The time-out counter will be reset at the center of each stop bit received or each time the receive FIFO is read.A break condition is detected when the RX pin is pulled LOW for a duration longer than the time it takes to send a complete character plus start, stop and parity bits. A break condition can be sent by setting LCR[6], when this happens the TX pin will be pulled LOW until LSR[6] is cleared by the software.
9. Programmable Baud Rate GeneratorThe UART contains a programmable baud rate generator that takes any clock input and divides it by a divisor in the range between 1 and (216 - 1). An additional divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in Figure 7. The formula for the baud rate is:
FIFO Full
TX RXwrptr
wrptrTXRDY
TXRDY RXRDY
RXRDY
At Least One Location Filled
rdptr
rdptr FIFO Empty
TriggerLevel
TriggerLevel
rate samplex divisor
)prescaler
frequencyinput crystal XTAL1( rate Baud =
Figure 8 shows TXRDY# and RXRDY# in DMA mode 1.
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Where:prescaler = 1, when MCR[7] is set to logic 0 after reset (divide-by-1 clock selected)prescaler = 4, when MCR[7] is set to logic 1 after reset (divide-by-4 clock selected).Divisor = {DLH, DLL}Sample rate = 4 if DLD[5] = 1, or = 8 if DLD[4] = 1, or = 16-SCR+CPR if DLD[5:4] = 2'b0.Remark: The default value of prescaler after reset is divide-by-1.DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and most significant byte of the baud rate divisor. If DLL and DLH are both zero, the UART is effectively disabled, as no baud clock will be generated.Remark: The programmable baud rate generator is provided to select both the transmit and receive clock rates.Table 7 to 10 show the baud rate and divisor correlation for crystal with frequency 1.8432 MHz, 3.072 MHz, 14.74926 MHz, and 24MHz respectively.
Table 7. Baud Rates Using a 1.8432 MHz Crystal
Desired baud rate (bit/s)Divisor used to generate 16x clock Sample rate
Percent error difference between desired and actual
50 2304 16 0
75 1536 16 0
110 1047 16 0.026
134.5 857 16 0.058
150 768 16 0
300 384 16 0
600 192 16 0
1200 96 16 0
1800 64 16 0
2000 46 20 0.617
2400 48 16 0
3600 32 16 0
4800 24 16 0
7200 16 16 0
9600 12 16 0
19200 6 16 0
38400 3 16 0
56000 2 16 2.86
Table 8. Baud Rates Using a 3.072 MHz Crystal
Desired baud rate (bit/s)Divisor used to generate 16x clock Sample rate
Percent error difference between desired and actual
50 2304 16 0
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75 2560 16 0
110 1745 16 0.026
134.5 1428 16 0.034
150 1280 16 0
300 640 16 0
600 320 16 0
1200 160 16 0
1800 90 19 0.195
2000 96 16 0
2400 80 16 0
3600 45 19 0.195
4800 40 16 0
7200 25 17 0.392
9600 20 16 0
19200 10 16 0
38400 5 16 0
Table 9. Baud Rates Using a 14.74926 MHz Crystal
Desired baud rate (bit/s)Divisor used to generate 16x clock Sample rate
Percent error difference between desired and actual
38400 24 16 0.025
56000 11 24 0.235
57600 16 16 0.025
115200 8 16 0.025
153600 6 16 0.025
921600 1 16 0.025
Table 10. Baud Rates Using a 24 MHz Crystal
Desired baud rate (bit/s)Divisor used to generate 16x clock Sample rate
Percent error difference between desired and actual
4800 250 20 0
7200 159 21 0.17
25000 48 20 0
38400 25 25 0
57600 22 19 0.32
115200 8 26 0.16
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225000 6 18 1.2
400000 3 20 0
921600 1 26 0.16
1000000 1 24 0
10. RS-485 Features
10.1 Auto RS-485 RTS ControlNormally the RTS pin is controlled by MCR bit 1, or if hardware flow control is enabled, the logic state of the RTS pin is controlled by the hardware flow control circuitry. RS485 register bit 4 will take the precedence over the other two modes; once this bit is set, the transmitter will control the state of the RTS pin. The transmitter automatically de-asserts the RTS pin (logic 1) once the host writes data to the transmit FIFO, and asserts RTS pin (logic 0) once the last bit of the data has been transmitted.To use the auto RS-485 RTS mode the software would have to disable the hardware flow control function.
10.2 RS-485 RTS Output InversionRS485 register bit 5 reverses the polarity of the RTS pin if the UART is in auto RS-485 RTS mode. When the transmitter has data to be sent it asserts the RTS pin (logic 0), and when the last bit of the data has been sent out the transmitter de-asserts the RTS pin (logic 1).
10.3 Auto RS-485RS485 register bit 0 is used to enable the RS-485 mode (multidrop or 9-bit mode). In this mode of operation, a ‘master’ station trans-mits an address character followed by data characters for the addressed ‘slave’ stations. The slave stations examine the received data and interrupt the controller if the received character is an address character (parity bit = 1). To use the auto RS-485 RTS mode the software would have to disable the hardware flow control function.
10.3.1 Normal Multidrop ModeThe 9-bit mode in RS485 register bit 0 is enabled, but not Special Character Detect (EFR bit 5). The receiver is set to Force Parity 0 (LCR[5:3] = 111) in order to detect address bytes.With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an address byte is received (parity bit = 1). This address byte will cause the UART to set the parity error. The UART will generate a line status interrupt (IER bit 2 must be set to ‘1’ at this time), and at the same time puts this address byte in the RX FIFO. After the controller examines the byte it must make a decision whether or not to enable the receiver; it should enable the receiver if the address byte addresses its ID address, and must not enable the receiver if the address byte does not address its ID address.If the controller enables the receiver, the receiver will receive the subsequent data until being disabled by the controller after the controller has received a complete message from the ‘master’ station. If the controller does not disable the receiver after receiving a message from the ‘master’ station, the receiver will generate a parity error upon receiving another address byte. The controller then determines if the address byte addresses its ID address, if it is not, the controller then can disable the receiver. If the address byte ad-dresses the ‘slave’ ID address, the controller take no further action; the receiver will receive the subsequent data.
10.3.2 Auto address detectionIf Special Character Detect is enabled (EFR[5] is set and XOFF2 contains the address byte) the receiver will try to detect an address byte that matches the programmed character in XOFF2. If the received byte is a data byte or an address byte that does not match the
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programmed character in XOFF2, the receiver will discard these data. Upon receiving an address byte that matches the XOFF2 char-acter, the receiver will be automatically enabled if not already enabled, and the address character is pushed into the RX FIFO along with the parity bit (in place of the parity error bit). The receiver also generates a line status interrupt (IER bit 2 must be set to 1 at this time). The receiver will then receive the subsequent data from the ‘master’ station until being disabled by the controller after having received a message from the ‘master’ station.If another address byte is received and this address byte does not match XOFF2 character, the receiver will be automatically disabled and the address byte is ignored. If the address byte matches XOFF2 character, the receiver will put this byte in the RX FIFO along with the parity bit in the parity error bit (LSR[2]).
11. Host InterfaceThe host interface is 8 data bits wide with 8 address lines and control signals to execute data bus read and write transactions. The PI7C9X754 data interface supports the Intel compatible types of CPUs and it is compatible to the industry standard 16C550 UART. No clock (oscillator nor external clock) is required for a data bus transaction. Each bus cycle is asynchronous using CS# IOR# and IOW# or CS#, R/W#, All four UART channels share the same data bus for host operations. Please refer to pin description and host interface read/write timing(Fig 10 and Fig 11).
11.1 UART Channel SelectionDuring Intel Bus Mode (16/68# pin is connected to VCC), a logic 0 on chip select pins, CSA#, CSB#, CSC# or CSD# allows the user to select UART channel A, B, C or D to configure, send transmit data and/or unload receive data to/from the UART. Selecting all four UARTs can be useful during power up initialization to write to the same internal registers, but do not attempt to read from all four UARTs simultaneously. Individual channel select functions are shown in Table 11.Table 11. Channel A-D Select In 16 Mode
CSA# CSB# CSC# CSD# Function
1 1 1 1 UART de-selected
0 1 1 1 Channel A selected
1 0 1 1 Channel B selected
1 1 0 1 Channel C selected
1 1 1 0 Channel D selected
0 0 0 0 Channel A-D selected
During Motorola Bus Mode (16/68# pin is connected to GND), the package interface pins are configured for connection with Mo-torola, and other popular microprocessor bus types. In this mode the V654 decodes two additional addresses, A3 and A4, to select one of the four UART ports. The A3 and A4 address decode function is used only when in the Motorola Bus Mode. See Table 12.
Table 12. Channel A-D Select In 68 Mode
CS# A4 A3 Function
1 X X UART de-selected
0 0 0 Channel A selected
0 0 1 Channel B selected
0 1 0 Channel C selected
0 1 1 Channel D selected
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12. Infrared ModeThe UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0 and 1.1. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide HIGH-pulse for each “0” bit in the transmit data stream with a data rate up to 115.2 Kbps. For the IrDA 1.1 standard, the infrared encoder sends out a 1/4 of a bit time wide HIGH-pulse for each "0" bit in the transmit data stream with a data rate up to 1.152 Mbps. This signal encoding reduces the on-time of the infrared LED, hence reduces the power consumption. See Figure 9 below.The infrared encoder and decoder are enabled by setting ASR register bit-1 to a ‘1’. With this bit enabled, the infrared encoder and decoder is compatible to the IrDA 1.0 standard. For the infrared encoder and decoder to be compatible to the IrDA 1.1 standard, ASR bit-4 will also need to be set to a ’1’. When the infrared feature is enabled, the transmit data output, TX, idles LOW. Likewise, the RX input also idles LOW, see Figure 9.The wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin. Each time it senses a light pulse, it returns a logic 1 to the data bit stream.
Tx Data
TransmitIR Pulse(TX Pin)
Character
Data Bits
0 0 0 0 0
0 0 0 0 01 1 1 1 1
1 1 1 1
Bit Time3/16 or 1/4 Bit Time
1/2 Bit Time
ReceiveIR Pulse(RX Pin)
RX Data
1/16 Clock Delay
Bit Time
Character
Data Bits
Start
Start
Stop
Stop
IrEncoder-1
IRdecoder-1Figure 9. Infrared transmit data receive data deconding
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13. Configuration Registers
Offset 00H(default=xxH)---Receiver Holding Register (RHR). Accessible when LCR[7]=0.
Bit Type Description
[7:0] RORx Holding - When data are read from the RHR,they are removed from the top of the receiver's FIFO. Data read from the RHR when FIFO is empty are invalid. The Line Status Register(LSR) indicates the full or empty status of the FIFOs.
Offset 00H(default=xxH)---Transmitter Holding Register (THR). Accessible when LCR[7]=0
Bit Type Description
[7:0] WOTx Holding - When data are written to the THR,they are written to the bottom of the transmitter's FIFO. Data written to the THR when FIFO is full are lost. The Line Status Register(LSR) indicates the full or empty status of the FIFOs.
Offset 01H(default=00H)--- Interrupt Enable Register (IER). Accessible when LCR[7]=0.
Bit Type Description
7 RW CTS interrupt - "1": enable CTS/DSR interrupt
6 RW RTS interrupt - "1": enable RTS/DTR interrupt
5 RW Xoff/Special character interrupt - "1": enable the Software Flow Control interrupt
4 RW
Sleep mode - "1" : enable sleep mode. (it requires EFR[4]=1) the Uart may enter sleep mode when all conditions met: * no interrupts pending * modem inputs are not toggled * RX input pin is idling HIGH * TX/RX FIFO are emptyit will exit from sleep mode when any below condition met: * modem inputs are toggling * RX input pin changed to LOW * a data byte is loaded to the TX FIFOAt sleep mode, Crystal is stopped and no Uart clock
3 RW Modem Status interrupt - "1": enable Modem Status interrupt
2 RW Receiver Line Status interrupt - "1": enable Receiver Line Status interrupt
1 RWTx Ready interrupt - "1": enable THR Ready interrupt1 = Interrupt is issued whenever the THR becomes empty in non-FIFO mode or when spaces in the FIFO is above the trigger level in the FIFO mode.
0 RW Rx Data Ready interrupt - "1": enable Data Ready interrupt
Note: IER[7:4] can only be modified if EFR[4]=1.
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Offset 02H(default=01H)--- Interrupt Status Register (ISR). Accessible when LCR[7]=0.
Bit Type Description
[7:6] RO Mirror the content of FCR[0]
[5:1] RO 5-bit encoded interrupt.
0 RO Interrupt status. "1": no interrupt is pending. "0": an interrupt is pending.
Priority Level ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of Interrupt
1 0 0 0 1 1 0 Receive Line Status Error
2 0 0 0 1 0 0 RHR interrupt
3 0 0 1 1 0 0 Receiver timeout
4 0 0 0 0 1 0 THR interrupt
5 0 0 0 0 0 0 Modem interrupt
6 0 1 0 0 0 0 Rx Xoff signal/special character
7 1 0 0 0 0 0 CTS,RTS change from active to inactive
- 0 0 0 0 0 1 None (default)
Note: ISR[4] is cleared by Xon detection if the interrupt is caused by Xoff detection, or cleared by a read of the ISR if it is caused by special char detection.
Offset 02H(default=00H)--- FIFO Control Register (FCR). Accessible when LCR[7]=0.
Bit Type Description
[7:6] WO RX trigger. Sets the trigger level for the RX FIFO
[5:4] WO TX trigger. Sets the trigger level for the TX FIFO
Trigger Table FCTR[5] FCTR[4] FCR[7] FCR[6] FCR[5] FCR[4] RXTGL TXTGLTable-A 0 0
0011
0101
0 014814
1
Table-B 0 10011
0101
0011
0101
8162428
1682430
Table-C 1 00011
0101
0011
0101
8165660
8163256
Table-D 1 1 X X X X RXTRG TXTGL
if Table A-C is selected: the RX FIFO Halt level for Hardware flow control is the next level after RXTGL. the RX FIFO Halt level for Software flow control is the at RXTGL. the RX FIFO Resume level for Hardware/Software flow control is one level below RXTGLif Table D is selected: the RX FIFO Halt level for Hardware flow control is the RXTRG plus Hystersis (FCTR[3:0]). the RX FIFO Halt level for Software flow control is the at RXTRG. the RX FIFO Resume level for Hardware/Software flow control is the RXTRG minus Hystersis (FCTR[3:0]) and the Halt level is maximum 60 characters, and the Resume level is minimum 0 characters.
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3 WO DMA mode enabled when set
2 WOS Reset TX FIFO. 0 = no FIFO transmit reset 1 = clears the contents of Tx FIFO and resets the FIFO level logic. TSR is not cleared. This bit will return to logic 0 after clearing the FIFO
1 WOS Reset RX FIFO. 0 = no FIFO receive reset 1 = clears the contents of Rx FIFO and resets the FIFO level logic. RSR is not cleared. This bit will return to logic 0 after clearing the FIFO
0 WO FIFO enable 0 = disable the transmit and receive FIFO, and TX/RX can only hold one character at a time. Other FCR bits are not programmable, and the trigger level is set to one character. 1 = enable the transmit and receive FIFO, and TX/RX FIFO can hold 64 characters.
Note: FCR[5:4] can only be modified and enabled if EFR[4]=1. Table-D see below FCTR description for the detail.
Offset 03H(default=1DH)--- Line Control Register (LCR).
Bit Type Description
7 RW Divisor latch enabled when set
6 RWBreak control bit.0 = no TX break condition1 = forces TX to logic 0 to alert a line break condition
5 RWSet forced parity format(if LCR[3]=1)0 = parity is not forced.1 = parity bit is forced to high if LCR[4]=0,or low if LCR[4]=1.
4 RW Parity type select.0 = odd parity is generated(if LCR[3]=1)1 = even parity is generated(if LCR[3]=1)
3 RW Parity enable when set
2 RWNumber of Stop bits0 = 1 stop bit.1 = 1.5 stop bits for word length=5, or 2 stop bits for word length=6,7,8
[1:0] RW
Word length bits: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits
Offset 04H(default=00H)--- Modem Control Register (MCR). Accessible when LCR[7]=0.
Bit Type Description
7 RWClock pre-scaler select. 0 = divide-by-1 clock input1 = divide-by-4 clock input
6 RW When set, TCR and TLR read/write enable
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Offset 05H(default=60H)--- Line Status Register (LSR). Accessible when LCR[7]=0.
Bit Type Description
7 RO
Receiver FIFO Data Error Flag.0 = No FIFO Error1 = a flag for the sum of all error bits(parity error, framing error, or break)in the RX FIFO, this bit clears when there is no more error in any of the bytes in the RX FIFO
6 ROTHR and TSR Empty FlagThis bit is set whenever the transmitter goes idle, it clears whenever either the THR or TSR contains a data character.
5 ROTHR Empty FlagThis bit is set when the last data byte is transferred from THR to TSR.
5 RWWhen set,Xon Any function is enabled and receiving any character will resume transmit operation. The RX character will be loaded into the RX FIFO, unless the RX character is an Xon/Xoff character and receiver software flow control is enabled.
4 RW When set, internal loopback mode is enabled and TX output is looped back to the RX input internally, and MCR[1:0] signals are looped back into MSR[4:5]
3 RW
Interrupt output control0 = Forces the INT(A-D) output to high-impedance state (interrupt disable)1 = INT(A-D) outputs to the active state (interrupt enable)The interrupt enable state can be overridden by INTSEL pin:
INTSEL MCR[3] INTA-D outputs in 16 mode
0 0 Hi-Z0 1 Active1 X Active
If Internal Loopback Mode(MCR[4]=1) is enabled, This bit is OP2 and is outputted to CD internally
2 RW FIFORdy register read enabled when MCR[4]=0 and ASR[0]=0 or OP1 if Internal Loopback Mode(MCR[4]=1) is enabled and is outputted to RI internally
1 RW
RTS pin control: 0 = force RTS pin High 1 = force RTS pin LowWhen internal loopback mode, it controls MSR[4].If Auto-RTS is enabled, the RTS pin is controlled by hardware flow controlIf the modem interface is not used, this output may be used as a general purpose output
0 RW
DTR pin control: 0 = force DTR pin High 1 = force DTR pin Lowuart_transmitter.vWhen internal loopback mode, it controls MSR[5].If the modem interface is not used, this output may be used as a general purpose output
Note: MCR[7:5] can only be modified if EFR[4]=1.
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4 RO
Receiver Break Error Flag0 = No Break Error1 = break condition occurred in data to be read from RX FIFO(RX was LOW for at least one character frame time).
3 RO
Receiver Data Framing Error Flag0 = No Data Framing Error1 = framing error occurred in data to be read from RX FIFO(The receive character did not have a valid stop bits).
2 ROReceiver Data Parity Error Flag0 = No Data Parity Error1 = parity error in data to be read from RX FIFO
1 ROReceiver Overrun Error0 = No Overrun Error1 = additional data received while the RX FIFO is full, this data should not be transferred into FIFO.
0 ROReceiver Data Ready Indicator0 = No data in received in RX FIFO1 = Data has been received and saved in the RX FIFO
Offset 06H(default=x0H)--- Modem Status Register (MSR). Accessible when LCR[7]=0 and MCR[6]=0.
Bit Type Description
7 ROCD input statusNormally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to MCR[3]
6 RORI input statusNormally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to MCR[2]
5 RODSR input statusNormally this bit is the complement of the DSR# input. In the loopback mode this bit is equivalent to MCR[0]
4 ROCTS input statusNormally this bit is the complement of the CTS# input. In the loopback mode this bit is equivalent to MCR[1]
3 RO
Delta CD# input flag0 = No change on CD# input1 = The CD# input has changed state. A modem status interrupt will be generated if MSR interrupt is enabled.
2 RO
Delta RI# input flag0 = No change on RI# input1 = The RI# input has changed from a LOW to HIGH. A modem status interrupt will be generated if MSR interrupt is enabled
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Note: the default of MSR[7:4]= logic levels of the inputs inverted
Offset 07H(default=FFH)--- Scratch Pad Register (SPR). Accessible when LCR[7]=0 and MCR[6]=0.
Bit Type Description
[7:0] RW This is 8-bit general purpose register for the user to store temporary data, the content is preserved during sleep mode.
Offset 00H(default=01H)--- Divisor Latch LSB(DLL). Accessible when LCR[7]=1 and LCR!=0xBF.
Bit Type Description
[7:0] RW LSB bits of divisor for baud rate generator. Note: It is reset only when Power-On-Reset.
Offset 01H(default=00H)--- Divisor Latch MSB(DLM). Accessible when LCR[7]=1 and LCR!=0xBF.
Bit Type Description
[7:0] RW MSB bits of divisor for baud rate generator.
Note: It is reset only when Power-On-Reset.
Offset 02H(default=00H)--- Divisor Fractional Register (DLD). Accessible when EFR[4]=1,LCR[7]=1
Bit Type Description
[7:6] RW Reserved
[5:4] RW
Sampling rate select: 00: 16X 01: 8X 1x: 4X
[3:0] RW Reserved
1 RO
Delta DSR# input flag0 = No change on DSR# input1 = The DSR# input has changed state. A modem status interrupt will be generated if MSR interrupt is enabled.
0 RO
Delta CTS# input flag0 = No change on CTS# input1 = The CTS# input has changed state. A modem status interrupt will be generated if MSR interrupt is enabled.
Note: Pre_Scaler = 2**(2*MCR[7])
Baud_Rate = XIN / ((256*DLM+DLL)*Pre_Scaler*(16-12*DLD[5])), when DLD[5]=1 or
Baud_Rate = XIN / ((256*DLM+DLL)*Pre_Scaler*(16-8*DLD[4])), when DLD[5]=0 or
Baud_Rate = XIN / ((256*DLM+DLL)*Pre_Scaler*(16-SCR+CPR)), when DLD=8'h00
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Offset 02H(default=00H)--- Enhanced Feature Register (EFR). Accessible when LCR=0xBF.
Bit Type Description
7 RWAuto CTS Flow Control Enable0 = Automatic CTS flow control is disabled.1 = Automatic CTS flow control is enabled.
6 RWAuto RTS Flow Control Enable0 = Automatic RTS flow control is disabled.1 = Automatic RTS flow control is enabled.
5 RW
Special character detect0 = Special character detect is disabled.1 = Special character detect is enabled. If received data matches Xoff2 data, the received data is trans-ferred to RX FIFO and ISR[4] is set to high to indicate a special character detection. However,if flow control is set for comparing Xoff2,then flow control works normally and Xoff2 will not go to the FIFO and will generate an Xoff interrupt and a special character interrupt.
4 RWEnhanced Function Bits EnableThis bit enables IER[7:4],ISR[5:4],FCR[5:4],MCR[7:5],TCR,TLR and ASR[7:0] to be modified, and enables the sleep mode.
[3:0] RW
Software Flow Control Select:00xx = No TX flow control10xx = Transmit Xon1,Xoff101xx = Transmit Xon2,Xoff211xx = Transmit Xon1 and Xon2,Xoff1 and Xoff2xx00 = No RX flow controlxx10 = Receiver compares Xon1,Xoff1xx01 = Receiver compares Xon2,Xoff21011 = Transmit Xon1,Xoff1; Receiver compares Xon1 or Xon2,Xoff1 or Xoff20111 = Transmit Xon2,Xoff2; Receiver compares Xon1 or Xon2,Xoff1 or Xoff21111 = Transmit Xon1 and Xon2,Xoff1 and Xoff2; Receiver compares Xon1 and Xon2,Xoff1 and Xoff20011 = No transmit flow control; Receiver compares Xon1 and Xon2,Xoff1 and Xoff2
Offset 04H(default=00H)--- XON1 character Register (XON1). Accessible when LCR=0xBF.
Bit Type Description
[7:0] RW XON1 character
Offset 05H(default=00H)--- XON2 character Register (XON2). Accessible when LCR=0xBF.
Bit Type Description
[7:0] RW XON2 character
Offset 06H(default=00H)--- XOFF1 character Register (XOFF1). Accessible when LCR=0xBF.
Bit Type Description
[7:0] RW XOFF1 character
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Offset 07H(default=00H)--- XOFF2 character Register (XOFF2). Accessible when LCR=0xBF.
Bit Type Description
[7:0] RW XOFF2 character
Offset 00H(default=00H)--- Device Revision Register (DREV). Accessible when LCR[7]=1,LCR!=0xBF,DLL=0x00 and DLM=0x00
Bit Type Description
[7:0] RO Revision number of the PSC754
Offset 01H(default=54H)--- Device Identification Register (DVID). Accessible when LCR[7]=1,LCR!=0xBF,DLL=0x00 and DLM=0x00
Bit Type Description
[7:0] RO The device ID for PSC754
Offset 00H(default=00H)--- Trigger Level Register (TRG). Accessible when LCR=0xBF.
Bit Type Description
[7] WOSelect TX or RX Trigger level of Table-D"0" - set RX trigger level RXTRG through TRG[6:0]"1" - set TX trigger level TXTRG through TRG[6:0]
[6:0] WO Set Trigger level for trigger Table-D from 0x00 to 0x40
Offset 00H(default=00H)--- RX/TX FIFO Level Counter Register (FC). Accessible when LCR=0xBF.
Bit Type Description
[7] RO
Indication of TX or RX FIFO level counter."0" - FC[6:0] is the number of characters in RX FIFO"1" - FC[6:0] is the number of characters in TX FIFOIt is alternative between RX and TX after each read of FC register
[6:0] RO Indication the number of characters in RX/TX FIFO
Offset 01H(default=20H)--- Feature Control Register (FCTR). Accessible when LCR=0xBF.
Bit Type Description
[7:6] RO Reserved
[5:4] RWSelect the transmit and receive FIFO trigger level table A-DSee above FCR register description for the detail.
[3:0] RW Auto RTS flow control hysteresis select
Note: Auto RTS flow control hysteresis select for receiver FIFO trigger level table D only
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Offset 04H(default=00)--- Advance Special Register (ASR). Accessible when EFR[4]=1,LCR[7]=1 and LCR!=0xBF.
Bit Type Description
7 RW When set, RS-485 control register access enable
6 RW When set, transmitter disabled
5 RW When set, receiver disabled
4 RWIrDA slow/fast mode control0 = IrDA version 1.0, 3/16 pulse ratio,data rate up to 115.2 Kbps1 = IrDA version 1.1, 1/4 pulse ratio,data rate up to 1.152 Mbps
3 RWInfrared RX input logic select 0 = RX input as active HIGH, normal 1 = RX input as active LOW, inverted
2 RW When set, sample clock register enable
1 RW When set, enable IrDA mode
0 RW When set, FIFO ready register access disable
Offset 05H(default=00)--- Sample Clock Register (SNR). Accessible when LCR[7]=1,LCR!=0xBF and ASR[2]=1
Bit Type Description
[7:4] RW SCR - Sample clock value, which is used to baud rate generate
[3:0] RW CPR - N number in calculating, which is used to baud rate generate
Note: 16-SCR+CPR>1, when set SNR to control the baud rate, DLD should be keep the default value 8'h00
Offset 02H(default=00H)--- Alternate Function Register (AFR). Accessible when EFR[4]=0,LCR[7]=1 and LCR!=0xBF.
Bit Type Description
[7:2] RO Reserved
1 RW Not used
0 RO Reserved
FCTR[3] FCTR[2] FCTR[1] FCTR[0] RTS/DTR Hysteresis
(Characters)0 0 0 0 00 0 0 1 +/- 40 0 1 0 +/- 60 0 1 1 +/- 80 1 0 0 +/- 80 1 0 1 +/- 160 1 1 0 +/- 240 1 1 1 +/- 321 1 0 0 +/- 121 1 0 1 +/- 201 1 1 0 +/- 281 1 1 1 +/- 361 0 0 0 +/- 401 0 0 1 +/- 441 0 1 0 +/- 481 0 1 1 +/- 52
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Offset 06H(default=00)--- RS-485 Mode Control Register (RS485). Accessible when LCR[7]=1,LCR!=0xBF and ASR[7]=1
Bit Type Description
[7:6] RO Reserved
5 RW
Auto RS-485 Polarity InversionThis bit changes the polarity of the Auto RS-485 Direction Control output pin (RTS#). It will only af-fect the behavior of RTS# if RS485[4]=10 = RTS# output is HIGH when transmitting and LOW when receiving1 = RTS# output is LOW when transmitting and HIGH when receiving
4 RW
Auto RS-485 direction controlThis bit enables the transmitter to control RTS# pin0 = transmitter does not control RTS# pin1 = transmitter controls RTS# pin
[3:1] RO Reserved
0 RW When set, enable RS-485 9-bit mode
Offset 06H(default=00H)--- Transmission Control Register (TCR). Accessible when LCR[7]=0, MCR[6]=1.
Bit Type Description
[7:4] RW
RX FIFO Resume level.When the RX FIFO is less than or equal to the value(decimal value of TCR[7:4] multiplied by 4),the RTS# output will be re-asserted if Auto RTS flow is used or XON character will be transmitted if Auto XON/XOFF flow control is used. It is recommended that this value is less than the RX Trigger Level.If TCR[7:4] is zero, the RX FIFO Resume level is defined by FCR/FCTR register(Table A-D)
[3:0] RW
RX FIFO Halt level.When the RX FIFO is greater than or equal to the value(decimal value of TCR[3:0] multiplied by 4),the RTS# output will be de-asserted if Auto RTS flow is used or XOFF character will be transmitted if Auto XON/XOFF flow control is used. It is recommended that this value is greater than the RX Trig-ger Level. If TCR[3:0] is zero, the RX FIFO Halt level is defined by FCR/FCTR register(Table A-D)
Offset 07H(default=00H)--- Trigger Level Register (TLR). Accessible when LCR[7]=0, MCR[6]=1.
Bit Type Description
[7:4] RW
RX FIFO Trigger level.When the number of characters received in RX FIFO is greater than or equal to the value(decimal value of TLR[7:4] multiplied by 4), a Receive Data Ready interrupt is generated. If TLR[7:4]=0x0, then the RX FIFO Trigger Level is the value selected by FCR[7:6] if TLR[7:4] is zero, the RX FIFO Trigger level is defined by FCR/FCTR register(Table A-D)
[3:0] RW
TX FIFO Trigger level.When the number of available space in TX FIFO is greater than or equal to the value(decimal value of TLR[3:0] multiplied by 4), a Transmit Ready interrupt is generated. If TLR[3:0]=0x0, then the TX FIFO Trigger Level is the value selected by FCR[5:4] if TLR[3:0] is zero, the TX FIFO Trigger level is defined by FCR/FCTR register(Table A-D)
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Offset 07H(default=FFH)--- FIFO Status Ready Register (FSRDY). Accessible when LCR[7]=0,MCR[4]=0,MCR[2]=1,ASR[0]=0, and any of CSA-D = 0
Bit Type Description
[7:4] RO Channel D-A RX FIFO status.
[3:0] RO Channel D-A TX FIFO status.
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DC Electrical CharacteristicsTA = -40oC to 85oC, VCC is 1.62V to 3.6V
Symbol Parameter
1.8V 2.5V 3.3V
Unit ConditionsMin. Max. Min. Max. Min. Max.
VILCK Clock input low level -0.3 0.3 -0.3 0.6 -0.3 0.6 V
VIHCK Clock input high level 1.4 VCC 1.8 VCC 2.4 VCC V
VIL Input low voltage -0.3 0.2 -0.3 0.5 -0.3 0.7 V
VIH Input high voltage 1.4 5.5 1.8 5.5 2.0 5.5 V
VOL Output low voltage
0.4
0.40.4 V
VV
IOL = 4 mAIOL = 2 mAIOL = 1.5 mA
VOH Output high voltage
1.4
1.82.0 V
VV
IOH = -1 mAIOH = -400 uAIOH = -200 uA
IIL Input low leakage current 10 -10 -10 uA
IIH Input high leakage current 10 10 10 uA
CIN Input pin capacitance 5 5 5 pF
ICC Power supply current 10 10 15 mAEXT Clock=14.75MHzAll inputs at VCC or GND and outputs unloaded
ISLEEP Sleep current 300 350 400 uAFour UARTs asleep. All inputs at VCC or GND and outputs unloaded.
Note: 5.5V steady voltage tolerance on inputs and outputs is valid only when the supply voltage is present.
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the op-erational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Power Supply Range .........................................................................3.8VVoltage at IO Pin ........................................................GND-0.3V to 5.5VStorage Temperature ....................................................–65°C to +150°CJunction Temperature (Tj) ............................................................ 125°C
Maximum Ratings(Above which useful life may be impaired. For user guidelines, not tested.)
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AC Electrical CharacteristicTA = -40oC to +85oC, VCC is 1.62V to 3.6V, 70pF load where applicable
Symbol Parameter UnitMin. Max.
TC1,TC2 Clock Pulse Period 6 ns
TOSC Crystal Frequency 24 MHz
TECK External Clock Frequency 80 MHz
TAS Address Setup (16 Mode) 0 ns
TAH Address Hold (16 Mode) 0 ns
TCS Chip Select Width (16 Mode) 20 ns
TDY Delay between CS# Active Cycles (16 Mode) 20 ns
TRD Read Strobe Width (16 Mode) 20 ns
TWR Write Strobe Width (16 Mode) 20 ns
TRDV Read Data Valid (16 Mode) 30 ns
TWDS Write Data Setup (16 Mode) 10 ns
TRDH Read Data Hold (16 Mode) 10 ns
TWDH Write Data Hold (16 Mode) 5 ns
TADS Address Setup (68 Mode) 0 ns
TADH Address Hold (68 Mode) 0 ns
TRWS R/W# Setup to CS# (68 Mode) 0 ns
TRDA Read Data Access (68 mode) 30 ns
TRDH Read Data Hold (68 mode) 10 ns
TWDS Write Data Setup (68 mode) 10 ns
TWDH Write Data Hold (68 Mode) 5 ns
TRWH CS# De-asserted to R/W# De-asserted (68 Mode) 1 ns
TCSL CS# Width (68 Mode) 20 ns
TCSD CS# Cycle Delay (68 Mode) 20 ns
TWDO Delay from IOW# to Modem Output 50 ns
TMOD Delay to set Interrupt from Modem Input 50 ns
TRSI Delay To Reset Interrupt From IOR# 50 ns
TSSI Delay From Stop To Set Interrupt 1 Bclk
TRRI Delay From IOR# To Reset Interrupt 45 ns
TSI Delay From Stop To Interrupt 45 nsTWRI Delay From IOW# To Reset Interrupt 45 nsTRST Reset Pulse 40 ns
TWT Delay From IOW# To Set TXRDT# 45 ns
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Pin Name Parameter Min. Max. Unit
TSSR Delay From Stop To Set RXRDY# 1 Bclk
TRR Delay From IOR# To Reset RXRDY# 45 ns
TSRT Delay From Center of Start To Reset TXRDY# 8 BclkBclk Baud Clock 16X or 8X of data rate Hz
AC Electrical Characteristic Cont.
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A0-A7
CS#
IOR#
D0-D7
Vaild Address Vaild Address
TASTAH
TASTAH
TCS
TDY
TRD
TRDV TRDVTRDH TRDH
Vaild Data Vaild Data
16Read16 Mode (Intel) Data Bus Read Timing
A0-A7
CS#
IOW#
D0-D7
Vaild Address Vaild Address
TASTAH
TASTAH
TCS
TDY
TWR
TWDH
Vaild Data Vaild Data
16Write16 Mode (Intel) Data Bus Write Timing
TWDHTWDS TWDS
Figure 10. 16 Mode (Intel) data bus read and write timing
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A0-A7
CS#
R/W#
D0-D7
Vaild Address Vaild Address
TADSTADH
TRWH
TCSL
TRDH
Vaild Data Vaild Data
68Read68 Mode (Motorola) Data Bus Read Timing
TCSDTRWS
TRDA
A0-A7
CS#
R/W#
D0-D7
Vaild Address Vaild Address
TADSTADH
TRWH
TCSL
TRDH
Vaild Data Vaild Data
68Write68 Mode (Motorola) Data Bus WriteTiming
TCSDTRWS
TRDA
Figure 11. 68 Mode (Motorola) data bus read and write timing
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PI7C9X754
IOW#
RTS#DTS#
CD#CTS#DSR#
INT
IOR#
RI#
Active
TWDO
Change of stateChange of state
Change of state
Change of state
Active
Active
Active Active
Active Active
Change of state
TMODTMOD
TRSI
TMOD
TRR TRR TRR
Start Bit D0 : D7 D0 : D7 D0 : D7
1 Byte in RHR
1 Byte in RHR
1 Byte in RHR
RX
INT
IOR#(Reading data out of RHR)
Stop Bit
TSSR TSSRTSSR
Active Data
Ready
Active Data
Ready
Active Data
Ready
RXRDY#
TSSR TSSR TSSR
Figure 12. Modem input/output timing
Figure 13. Receive ready & Interrupt timing [Non-FIFO Mode] for Channels A-D
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TWRI
Start Bit D0 : D7 D0 : D7 D0 : D7
TX(Unloading)
INT*
IOW#(Loading data into THR)
Stop Bit
TWRI TWRI
ISR is read ISR is read ISR is readIER[1] enabled
*INT is cleared when the ISR is read or when data is loaded into the THR.
TXRDY#
TSRT TSRT TSRT
TWTTWT TWT
Start Bit
D0 : D7RX
INT
IOR#(Reading data out of RX FIFO)
S S D0 : D7 ST D0 : D7 D0 : D7 T S D0 : D7 T S TD0 : D7 S D0 : D7 T
RX FIFO fills up to RX Trigger Level or RX Data Timeout
RX FIFO drops below RX Trigger Level
TSSI
TRRI TRR
First Byte is Received in RX FIFO
TSSR FIFO Empties
Stop Bit
RXRDY#
Figure 14. Transmit ready & Interrupt timing [non-FIFO mode] for Channel A-D
Figure 15. Receive ready & Interrupt timing [FIFO mode, DMA disabled] for Channels A-D
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Start Bit
D0 : D7RX
INT
IOR#(Reading data out of RX FIFO)
S S D0 : D7 ST D0 : D7 D0 : D7 T S D0 : D7 T S TD0 : D7 S D0 : D7 T
RX FIFO fills up to RX Trigger Level or RX Data Timeout
RX FIFO drops below RX Trigger Level
TSSI
TRRI TRR
TSSRFIFO Empties
Stop Bit
RXRDY#
Figure 16. Receive ready & Interrupt timing [FIFO mode, DMA enabled] for Channels A-D
TSI
Start Bit
D0 : D7TX
(Unloading)
INT*
IOW#(Loading data into
FIFO)
ISR is read
S D0 : D7D0 : D7ST T S D0 : D7 T T S T S D0 : D7 T S D0 : D7 T
Stop BitLast Data Byte Transmitted
TX FIFO Empty
IER [1]enabled
TX FIFO fills up to trigger level
ISR is read
TX FIFO drops below trigger level
TWRI
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
TSRT
TWT
Data in TX FIFO
TX FIFO Empty
TXRDY#
Figure 17. Transmit ready & Interrupt timing [FIFO mode, DMA mode disabled] for Channels A-D
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Start Bit
D0 : D7S S D0 : D7 ST D0 : D7 D0 : D7 T S D0 : D7 T S TD0 : D7 S D0 : D7 T
Stop BitLast Data Byte Transmitted
TX(Unloading)
T
INT*
TXRDY#
IOW#(Loading data into
FIFO)
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
IER [1]enabled
ISR is read
TX FIFO fills up to trigger level
TWRI
TSRT TSIISR is read
TX FIFO drops below trigger level
TX FIFO Full
At least 1 empty loca-tion in FIFO
TWT
Figure 18. Transmit ready & Interrupt timing [FIFO mode, DMA mode enabled] for Channels A-D
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PI7C9X754
PI7C9X754ZBEYYWWXX
YY: YearWW: Workweek1st X: Assembly Code2nd X: Fab Code
Part Marking
PI7C9X754FCE
YYWWXX
YY: YearWW: Workweek1st X: Assembly Code2nd X: Fab Code
PI7C9X754FFE
YYWWXX
YY: YearWW: Workweek1st X: Assembly Code2nd X: Fab Code
PI7C9X754ME
YYWWXX
YY: YearWW: Workweek1st X: Assembly Code2nd X: Fab Code
ZB Package FC Package FF Package
M Package
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Packaging Mechanical: 100-MQFP (M)
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Packaging Mechanical: 80-LQFP (FF)
1
DESCRIPTION: 80-contact, Low Profi le Quad Flat Package (LQFP)PACKAGE CODE: FF (FF80)
DOCUMENT CONTROL #: PD-2064 REVISION: A
DATE: 03/18/09
07-0100
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1
Seating Plane
0.50 BSC.0190.17
0.27.007.010
1.60.063
1.351.45
.053
.057
0.050.15
.002
.006
X.XXX.XX
DENOTES DIMENSIONSIN MILLIMETERS
12.00 BSC
.394
Square
10.00 BSC
.472
SquareGAUGE PLANE
1.00 REF.039
0.450.75
.018
.030
0.090.20
.004
.008
0.25 m
m
Max.
0.10.004
DESCRIPTION: 64-Pin Low Profile Quad Flat Package, LQFP
PACKAGE CODE: FC
DOCUMENT CONTROL NO.PD - 1804
REVISION: CDATE: 03/09/05
Pericom Semiconductor Corporation3545 N. 1st Street, San Jose, CA 951341-800-435-2335 • www.pericom.comNotes:
1. All dimensions in millimeters2. Ref.: JEDEC MS-026D/BCD3. Package Outline Exclusive of Mold Flash and Metal Burr
Packaging Mechanical: 64-LQFP (FC)
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1
DESCRIPTION: 48-Pin, Thin Fine Pitch Quad Flat No-Lead (TQFN)PACKAGE CODE: ZB48
DOCUMENT CONTROL #: PD-2080 REVISION: B
UNIT: mm
Notes:1. All dimensions are in millimeters, angles are in degrees.2. Coplanarity applies to the exposed thermal pad as well as the terminals.3. Refer JEDEC MO-220
DATE: 0543/09/12
12-0459
Packaging Mechanical: 48-TQFN (ZB)
Ordering Information
Ordering Number Package Code Package Description
PI7C9X754ME M 100-Pin, Metric Quad Flat Package (MQFP)
PI7C9X754FFEX FF 80-Contact, Low Profile Quad Flat Package (LQFP)
PI7C9X754FCEX FC 64-Pin, Low Profile Quad Flat Package (LQFP)
PI7C9X754ZBEX ZB 48-Pin, Thin Fine Pitch Quad Flat No-Lead (TQFN)
For latest package info. please check: http://www.diodes.com/design/support/packaging/pericom-packaging/packaging-mechanicals-and-thermal-characteristics/
Notes:
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. 2. See https://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm
antimony compounds.4. E = Pb-free and Green5. X suffix = Tape/Reel
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IMPORTANT NOTICE
DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further no-tice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or trademark rights, nor the rights of others. Any Customer or user of this document or products described herein in such applications shall assume all risks of such use and will agree to hold Diodes Incorporated and all the companies whose products are represented on Diodes Incorporated website, harmless against all damages.
Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel.
Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall indemnify and hold Diodes Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized application.
Products described herein may be covered by one or more United States, international or foreign patents pending. Product names and markings noted herein may also be covered by one or more United States, international or foreign trademarks.
This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the final and determi-native format released by Diodes Incorporated.
LIFE SUPPORT
Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user.
B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or to affect its safety or effectiveness.
Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related information or support that may be provided by Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or systems.
Copyright © 2016, Diodes Incorporated
www.diodes.com
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Revision History
Data Revision number Description
10/27/2014 1.0 First Release
06/13/2017 1.1Change LogoUpdated Maximum Rating Table
10/25/2017 2 Revision numbering system changed to whole number
11/19/2018 3Updated Packaging MechanicalAdded Part Marking
12/04/2018 4 Updated Ordering Information
04/30/2019 5 Proofread content