features descriptio u - analog devices · 2020. 2. 1. · tbr2/050101/02, tbr2/051501/02 1.2mhz...

1

LTC2846

sn2846 2846fs

APPLICATIO SU

DESCRIPTIO

U

FEATURES

TYPICAL APPLICATIO

U, LTC and LT are registered trademarks of Linear Technology Corporation.

Complete DTE or DCE Multiprotocol Serial Interface with DB-25 Connector

Data Networking CSU and DSU Data Routers

Software-Selectable Transceiver Supports:RS232, RS449, EIA530, EIA530-A, V.35, V.36, X.21

Operates from Single 3.3V Supply TUV Rheinland of North America Inc. Certified NET1,

NET2 and TBR2 Compliant, Report No.:TBR2/050101/02, TBR2/051501/02

1.2MHz Boost Switching Regulator for 3.3V to 5VConversion

On-Chip Cable Termination Complete DTE or DCE Port with LTC2844 or LTC2845 Small Footprint Available in 36-Lead SSOP (0.209 Wide) Package

The LTC®2846 is a 3-driver/3-receiver multiprotocol trans-ceiver with on-chip cable termination. When combined withthe LTC2844 or LTC2845, this chip set forms a completesoftware-selectable DTE or DCE interface port that supportsthe RS232, RS449, EIA530, EIA530-A, V.35, V.36 and X.21protocols. All necessary cable termination is provided insidethe LTC2846. The LTC2846 has a boost regulator that takesin a 3.3V input and switches at 1.2MHz, allowing the use oftiny, low cost capacitors and inductors 2mm or less in height.The 5V output drives an internal charge pump that requiresonly five space-saving surface mounted capacitors. TheLTC2846 is available in a 36-lead SSOP surface mountpackage.

3.3V Software-SelectableMultiprotocol Transceiver

with Termination

D2 D1

LTC2844

RTSDTRDSR DCDCTS

D3R2 R1R4 R3

LTC2846

LL TXDSCTETXCRXCRXD

2142411151217931419206 2322513 81018 7 16

2846 TA01

D1

SCTE B

SCTE A (113)

TXD B

TXD A (103)

RXC A (115)

RXC B

RXD A (104)

RXD B

RTS A (105)

RTS B

DTR A (108)

DTR B

CTS A (106)

CTS B

LL A (141)

SG (102)

SHIELD (101)

DB-25 CONNECTOR

TXC A (114)

DCD A (109)

DCD B

DSR A (107)

DSR B

D4 D2D3R1R2R3

TXC B

TTTTT

2

LTC2846

sn2846 2846fs

ORDER PARTNUMBER

(Note 1)VCC Voltage.............................................. –0.3V to 6.5VVIN Voltage .............................................. –0.3V to 6.5VInput Voltage

Transmitters ........................... –0.3V to (VCC + 0.3V)Receivers ............................................... –18V to 18VLogic Pins .............................. –0.3V to (VCC + 0.3V)

Output VoltageTransmitters ................. (VEE – 0.3V) to (VDD + 0.3V)Receivers ................................. –0.3V to (VIN + 0.3V)VEE........................................................ –10V to 0.3VVDD ....................................................... –0.3V to 10V

Short-Circuit DurationTransmitter Output ..................................... IndefiniteReceiver Output .......................................... IndefiniteVEE.................................................................. 30 sec

SW Voltage ............................................... –0.4V to 36VFB Voltage ............................................... –0.3V to 2.5VCurrent into FB Pin .............................................. ±1mASHDN Voltage ........................................... –0.3V to 10VOperating Temperature Range

LTC2846C ............................................... 0°C to 70°CLTC2846I ........................................... –40°C to 85°C

Storage Temperature Range ................ – 65°C to 150°CLead Temperature (Soldering, 10 sec)................. 300°C

LTC2846CGLTC2846IG

TJMAX = 125°C, θJA = 90°C/W, θJC = 35°C/W

ABSOLUTE AXI U RATI GS

W WW U

PACKAGE/ORDER I FOR ATIOU UW

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

TOP VIEW

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

NC

PGND

VIN

SHDN

C1–

C1+

VDD

VCC

D1

D2

D3

R1

R2

R3

M0

M1

VIN

M2

SW

FB

SGND

C2+

C2–

VEE

GND

D1 A

D1 B

D2 A

D2 B

D3/R1 A

D3/R1 B

R2 A

R2 B

R3 A

R3 B

DCE/DTE

R3

CHARGE PUMP

R1

D2

D1

R2

D3

G PACKAGE36-LEAD PLASTIC SSOP

T

T

T

T

T

BOOSTSWITCHINGREGULATOR

The denotes specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VIN = 3.3V, VSHDN = VIN, unless otherwise noted. (Notes 2, 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Supplies

ICC VCC Supply Current (DCE Mode, RS530, RS530-A, X.21 Modes, No Load 14 mAAll Digital Pins = GND or VIN) RS530, RS530-A, X.21 Modes, Full Load 100 130 mA

V.35 Mode 126 170 mAV.28 Mode, No Load 20 mAV.28 Mode, Full Load 35 75 mANo-Cable Mode 300 900 µA

PD Internal Power Dissipation (DCE Mode) RS530, RS530-A, X.21 Modes, Full Load 550 mWV.35 Mode, Full Load 775 mWV.28 Mode, Full Load 200 mW

V + Positive Charge Pump Output Voltage V.11 or V.28 Mode, No Load 8 9.3 VV.35 Mode 7 8.0 VV.28 Mode, with Load 8 8.7 VV.28 Mode, with Load, IDD = 10mA 6.5 V

ELECTRICAL CHARACTERISTICS

Consult LTC Marketing for parts specified with wider operating temperature ranges.

*θJA SOLDERED TO A CIRCUIT BOARD IS TYPICALLY 60°C/W

3

LTC2846

sn2846 2846fs

The denotes specifications which apply over the full operatingtemperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VIN = 3.3V, VSHDN = VIN, unless otherwise noted. (Notes 2, 3)ELECTRICAL CHARACTERISTICS


V – Negative Charge Pump Output Voltage V.28 Mode, No Load –9.6 VV.28 Mode, Full Load –7.5 –8.5 VV.35 Mode –5.5 –6.5 VRS530, RS530-A, X.21 Modes, Full Load –4.5 –6.0 V

fOSC Charge Pump Oscillator Frequency 500 kHz

tr Charge Pump Rise Time No-Cable Mode/Power-Off to Normal Operation 2 ms

Logic Inputs and Outputs

VIH Logic Input High Voltage D1, D2, D3, M0, M1, M2, DCE/DTE 2.0 VSHDN 2.4 V

VIL Logic Input Low Voltage D1, D2, D3, M0, M1, M2, DCE/DTE 0.8 VSHDN 0.5 V

IIN Logic Input Current D1, D2, D3 ±10 µAM0, M1, M2, DCE/DTE = GND – 30 – 75 –120 µAM0, M1, M2, DCE/DTE = VIN ±10 µASHDN = GND ±0.1 µASHDN = 3V 16 32 µA

VOH Output High Voltage IO = –3mA 2.7 3 V

VOL Output Low Voltage IO = 1.6mA 0.2 0.4 V

IOSR Output Short-Circuit Current 0V ≤ VO ≤ VIN ±50 mA

IOZR Three-State Output Current M0 = M1 = M2 = VIN, VO = GND –30 –85 –160 µAM0 = M1 = M2 = VIN, VO = VIN ±10 µA

V.11 Driver

VODO Open Circuit Differential Output Voltage RL = 1.95k (Figure 1) ± 5 V

VODL Loaded Differential Output Voltage RL = 50Ω (Figure 1) 0.5VODO 0.67VODO VRL = 50Ω (Figure 1) ±2 V

∆VOD Change in Magnitude of Differential RL = 50Ω (Figure 1) 0.2 VOutput Voltage

VOC Common Mode Output Voltage RL = 50Ω (Figure 1) 3 V

∆VOC Change in Magnitude of Common Mode RL = 50Ω (Figure 1) 0.2 VOutput Voltage

ISS Short-Circuit Current VOUT = GND ±150 mA

IOZ Output Leakage Current VA and VB ≤ 0.25V, Power Off or ± 1 ±100 µANo-Cable Mode or Driver Disabled

tr, t f Rise or Fall Time (Figures 2, 13) 2 15 25 ns

tPLH Input to Output Rising (Figures 2, 13) 15 40 65 ns

tPHL Input to Output Falling (Figures 2, 13) 15 40 65 ns

∆t Input to Output Difference, tPLH – tPHL (Figures 2, 13) 0 3 12 ns

tSKEW Output to Output Skew (Figures 2, 13) 3 ns

4

LTC2846

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V.11 Receiver

VTH Input Threshold Voltage –7V ≤ VCM ≤ 7V –0.2 0.2 V

∆VTH Input Hysteresis –7V ≤ VCM ≤ 7V 15 40 mV

RIN Input Impedance –7V ≤ VCM ≤ 7V (Figure 3) 100 103 Ωtr, t f Rise or Fall Time CL = 50pF (Figures 4, 14) 15 ns

tPLH Input to Output Rising CL = 50pF (Figures 4, 14) 50 90 ns

tPHL Input to Output Falling CL = 50pF (Figures 4, 14) 50 90 ns

∆t Input to Output Difference, tPLH – tPHL CL = 50pF (Figures 4, 14) 0 4 25 ns

V.35 Driver

VOD Differential Output Voltage Open Circuit, RL = 1.95k (Figure 5) ±1.2 VWith Load, –4V ≤ VCM ≤ 4V (Figure 6) ±0.44 ±0.55 ±0.66 V

VOA, VOB Single-Ended Output Voltage Open Circuit, RL = 1.95k (Figure 5) ±1.2 V

VOC Transmitter Output Offset RL = 50Ω (Figure 5) ±0.6 V

IOH Transmitter Output High Current VA, VB = 0V –9 – 11 – 13 mA

IOL Transmitter Output Low Current VA, VB = 0V 9 11 13 mA

IOZ Transmitter Output Leakage Current VA and VB ≤ 0.25V ±1 ±100 µA

ROD Transmitter Differential Mode Impedance 50 100 150 ΩROC Transmitter Common Mode Impedance –2V ≤ VCM ≤ 2V (Figure 7) 135 150 165 Ωtr, tf Rise or Fall Time (Figures 8, 13) 5 ns

tPLH Input to Output (Figures 8, 13) 15 35 65 ns

tPHL Input to Output (Figures 8, 13) 15 35 65 ns

∆t Input to Output Difference, tPLH – tPHL (Figures 8, 13) 0 16 ns

tSKEW Output to Output Skew (Figures 8, 13) 4 ns

V.35 Receiver

VTH Differential Receiver Input Threshold Voltage –2V ≤ VCM ≤ 2V (Figure 9) –0.2 0.2 V

∆VTH Receiver Input Hysteresis –2V ≤ VCM ≤ 2V (Figure 9) 15 40 mV

RID Receiver Differential Mode Impedance –2V ≤ VCM ≤ 2V 90 103 110 ΩRIC Receiver Common Mode Impedance –2V ≤ VCM ≤ 2V (Figure 10) 135 150 165 Ω

tr, t f Rise or Fall Time CL = 50pF (Figures 4, 14) 15 ns

tPLH Input to Output CL = 50pF (Figures 4, 14) 50 90 ns

tPHL Input to Output CL = 50pF (Figures 4, 14) 50 90 ns

∆t Input to Output Difference, tPLH – tPHL CL = 50pF (Figures 4, 14) 0 4 25 ns

V.28 Driver

VO Output Voltage Open Circuit ±10 VRL = 3k (Figure 11) ±5 ±8.5 V

ISS Short-Circuit Current VOUT = GND ±150 mA

ROZ Power-Off Resistance –2V < VO < 2V, Power Off 300 Ωor No-Cable Mode

SR Slew Rate RL = 7k, CL = 0 (Figures 11, 15) 4 30 V/µs

tPLH Input to Output RL = 3k, CL = 2500pF (Figures 11, 15) 1.5 2.5 µs

tPHL Input to Output RL = 3k, CL = 2500pF (Figures 11, 15) 1.5 2.5 µs

5

LTC2846

sn2846 2846fs


Note 1: Absolute Maximum Ratings are those values beyond which the lifeof the device may be impaired.Note 2: All currents into device pins are positive; all currents out of deviceare negative. All voltages are referenced to device ground unless otherwisespecified.

Note 3: All typicals are given for VCC = 5V, VIN = 3.3V, CVCC = CVIN = 10µF,CVDD = 1µF, CVEE = 3.3µF and TA = 25°C.Note 4: The Boost Regulator is specified for VIN = 3V unless otherwisenoted.Note 5: Current limit guaranteed by design and/or correlation to static test.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSV.28 ReceiverVTHL Input Low Threshold Voltage (Figure 12) 0.8 VVTLH Input High Threshold Voltage (Figure 12) 2 V∆VTH Receiver Input Hysteresis (Figure 12) 0 0.05 0.3 VRIN Receiver Input Impedance –15V ≤ VA ≤ 15V 3 5 7 kΩtr, tf Rise or Fall Time CL = 50pF (Figures 12, 16) 15 nstPLH Input to Output CL = 50pF (Figures 12, 16) 60 300 nstPHL Input to Output CL = 50pF (Figures 12, 16) 160 300 nsBoost Switching Regulator (Note 4)VIN Operating Voltage 3 3.3 3.6 VVFB Feedback Voltage 1.230 1.255 1.280 VIFB FB Pin Bias Current VFB = 1.255V 120 360 nAIQ Quiescent Current VSHDN = 2.4V, Not Switching 4.2 6 mA

Quiescent Current in Shutdown VSHDN = 0V, VIN = 3V 0.01 1 µA∆VFB(LR) Reference Line Regulation 3V ≤ VIN ≤ 3.6V 0.01 0.05 %/Vf Switching Frequency 0.85 1.2 1.6 MHzDCMAX Maximum Duty Cycle 82 90 %ILIM Switch Current Limit (Note 5) 1 1.2 2 AVSAT Switch VCESAT ISW = 900mA 350 mVILEAK Switch Leakage Current VSW = 5V 0.01 1 µA

TYPICAL PERFOR A CE CHARACTERISTICS

UW

V.11 Mode ICC vs Data Rate

DATA RATE (kBd)10

I CC

(mA)

120

130

140

2846 G04

110

100

90100 1000

150

160

170

10000

TA = 25°C

DATA RATE (kBd)10

120

I CC

(mA)

125

130

135

140

150

100 1000

2846 G05

10000

145

TA = 25°C

DATA RATE (kBd)10

30

I CC

(mA)

35

40

45

50

60

20 40 60 80 100

2846 G06

55

TA = 25°C

V.35 Mode ICC vs Data Rate V.28 Mode ICC vs Data Rate

6

LTC2846

sn2846 2846fs

TYPICAL PERFOR A CE CHARACTERISTICS

UW

V.11 Mode ICC vs Temperature V.35 Mode ICC vs Temperature V.28 Mode ICC vs Temperature

TEMPERATURE (°C)–40

I CC

(mA)

100

105

110

20 60

2846 G07

95

90

–20 0 40 80 100

85

80


123.0

I CC

(mA)

123.5

124.5

125.0

125.5

128.0

126.5

0 40 60

2846 G08

124.0

127.0

127.5

126.0

–20 20 80 100


I CC

(mA)

37.0

20

3846 G09

35.5

34.5

–20 0 40

34.0

33.5

37.5

36.5

36.0

35.0

60 80 100

Boost Switching Regulator SHDNPin Current vs Voltage

SHDN PIN VOLTAGE (V)0

SHDN

PIN

CUR

RENT

(µA)

15

20

25

3 5

2846 G10

10

5

01 2 4

30

35

40

6

TA = 25°C TA = 100°C

Boost Switching RegulatorCurrent Limit vs Duty Cycle

DUTY CYCLE (%)10

0.8

1.0

1.4

40 60

2846 G11

0.6

0.4

20 30 50 70 80

0.2

0

1.2

CURR

ENT

LIM

IT (A

)

TA = 25°C

Boost Switching RegulatorOscillator Frequencyvs Temperature

TEMPERATURE (°C)–40 –20

1.05

FREQ

UENC

Y (M

Hz)

1.15

1.30

0 40 60

2846 G12

1.10

1.25

1.20

20 80 100

LOAD CURRENT (mA)0

EFFI

CIEN

CY (%

)

90

85

80

75

70

65

60

55

50400

2846 TA01b

10050 150 250 350 450200 300 500

VIN = 3.3V

TA = 25°C

Efficiency vs Load Current

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LTC2846

sn2846 2846fs

UUU

PI FU CTIO SNC (Pin 1): No Connect.

PGND (Pin 2): Boost Switching Regulator Power Ground.Tie PGND to SGND.

VIN (Pin 3): Input Supply Pin. Input supply to boostswitching regulator. 3V ≤ VIN ≤ 3.6V. Bypass with a 10µFcapacitor to ground.

SHDN (Pin 4): Boost Switching Regulator Shutdown Pin.Tie to 2.4V or more to enable regulator. Ground to shutdown.

C1– (Pin 5): Capacitor C1 Negative Terminal. Connect a1µF capacitor between C1+ and C1–.

C1+ (Pin 6): Capacitor C1 Positive Terminal. Connect a1µF capacitor between C1+ and C1 –.

VDD (Pin 7): Generated Positive Supply Voltage forV.28. Connect a 1µF capacitor to ground.

VCC (Pin 8): Input Supply Pin. Input supply to trans-ceiver. 4.75V ≤ VCC ≤ 5.25V. Connect to output of switch-ing regulator.

D1 (Pin 9): TTL Level Driver 1 Input.



R1 (Pin 12): CMOS Level Receiver 1 Output with Pull-Upto VIN when Three-Stated.



M0 (Pin 15): TTL Level Mode Select Input 0 with Pull-Upto VIN. See Table 1.


VIN (Pin 17): Input Supply Pin. Input supply to transceiver.3V ≤ VIN ≤ 3.6V. Connect to Pin 3.


DCE/DTE (Pin 19): TTL Level Mode Select Input withPull-Up to VIN. See Table 1.

R3 B (Pin 20): Receiver 3 Noninverting Input.

R3 A (Pin 21): Receiver 3 Inverting Input.

R2 B (Pin 22): Receiver 2 Noninverting Input.

R2 A (Pin 23): Receiver 2 Inverting Input.

D3/R1 B (Pin 24): Receiver 1 Noninverting Input andDriver 3 Noninverting Output.

D3/R1 A (Pin 25): Receiver 1 Inverting Input and Driver 3Inverting Output.

D2 B (Pin 26): Driver 2 Noninverting Output.

D2 A (Pin 27): Driver 2 Inverting Output.

D1 B (Pin 28): Driver 1 Noninverting Output.

D1 A (Pin 29): Driver 1 Inverting Output.

GND (Pin 30): Transceiver Ground.

VEE (Pin 31): Generated Negative Supply Voltage. Connecta 3.3µF capacitor to GND.

C2 – (Pin 32): Capacitor C2 Negative Terminal. Connect a1µF capacitor between C2 + and C2 –.

C2 + (Pin 33): Capacitor C2 Positive Terminal. Connect a1µF capacitor between C2+ and C2 –.

SGND (Pin 34): Boost Switching Regulator Signal Ground.Tie PGND to SGND.

FB (Pin 35): Boost Switching Regulator Feedback Pin.Reference voltage is 1.255V. Connect resistive divider taphere. Minimize trace area at FB.

SW (Pin 36): Boost Switching Regulator Switch Pin.Connect inductor/diode here. Minimize trace area at thispin to reduce EMI.

8

LTC2846

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BLOCK DIAGRA

W

C1–

C1+

VDD

VCC

C1–

C1+

VDD

VCC

PGND

VIN

SHDN

C2+

C2–

VEE

GND

C2+

C2–

VEE

GND

CHARGE PUMP

D1

D1A

50Ω

125Ω

50Ω

S1S2

D1B

D1

D2

D2A

50Ω

125Ω

50Ω

S1S2

D2B

S3S2

20k

20k

20k

20k

125Ω

S2S3

125Ω

10k 6k

S1

51.5Ω

D3/R1 A

D3/R1 B

51.5Ω10k

10k

10k

51.5Ω

R2A

R2B

51.5Ω

D2

D3

DCE/DTE

R1

D3

R1

R2 R2

6k

20k

20kMODESELECTION

LOGIC

S2S3

125Ω

10k

10k

51.5Ω

R3A

R3B2846 BD

51.5Ω

R3 R3

6k

335

6

7

8

9

10

11

19

12

13

14

VIN 17

M0 15

M1 16

M2 18

32

31

GND

VIN

SHDN

SW

FB

SGND

SW

FB

GND

BOOST SWITCHING REGULATOR

362

3

4

35

34

30

29

28

27

26

25

24

23

22

21

20

9

LTC2846

sn2846 2846fs

Figure 1. V.11 Driver DC Test Circuit Figure 2. V.11 Driver AC Test Circuit

Figure 4. V.11, V.35 Receiver AC Test CircuitFigure 3. Input Impedance Test Circuit

Figure 5. V.35 Driver Open-Circuit Test Figure 6. V.35 Driver Test Circuit Figure 7. V.35 Driver Common ModeImpedance Test Circuit

Figure 8. V.35 Driver AC Test Circuit Figure 9. V.35 Receiver DC Test Circuit Figure 10. Receiver Common ModeImpedance Test Circuit

Figure 11. V.28 Driver Test Circuit Figure 12. V.28 Receiver Test Circuit

TEST CIRCUITS

2846 F01

VOD

VOC

RL

RLA

BD

A

BD

2846 F02

RL100Ω

CL100pF

CL100pF

R

2846 F03

VCM = ±7V

BIB

A+–

IA

2(VB – VA)IB – IA

RIN =

A

B

2846 F04

R

CL

2846 F05

VOD

VOC

RL50Ω

VOB

VOA

125Ω

50Ω RL

2846 F06

50Ω

VOB

VOA

125Ω 125Ω

50Ω

50Ω

50Ω VCM

2846 F07

50Ω125Ω

50Ω VCM = ±2V+–

2846 F08

50Ω50Ω125Ω 125Ω

50Ω 50Ω

2846 F09

VTH

VCM

+–

+–2846 F10

51.5Ω

125Ω

51.5ΩVCM = ±2V +–

AD

2846 F11

RLCL

RA

2846 F12

CLVA

10

LTC2846

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Mode Name M2 M1 M0 DCE/ D1,2 D3 D1 D2 D3 R1 R2 R3 R1 R2,R3 VDD VEEDTE (Note 2) (Note 2) (Note 2) (Note 3) (Note 3) (Note 4) (Note 5)

A B A B A B A B A B A B

Not Used(Default V.11) 0 0 0 0 TTL X V.11 V.11 V.11 V.11 Z Z V.11 V.11 V.11 V.11 V.11 V.11 CMOS CMOS 9.3V –6V

RS530A 0 0 1 0 TTL X V.11 V.11 V.11 V.11 Z Z V.11 V.11 V.11 V.11 V.11 V.11 CMOS CMOS 9.3V –6V

RS530 0 1 0 0 TTL X V.11 V.11 V.11 V.11 Z Z V.11 V.11 V.11 V.11 V.11 V.11 CMOS CMOS 9.3V –6V

X.21 0 1 1 0 TTL X V.11 V.11 V.11 V.11 Z Z V.11 V.11 V.11 V.11 V.11 V.11 CMOS CMOS 9.3V –6V

V.35 1 0 0 0 TTL X V.35 V.35 V.35 V.35 Z Z V.35 V.35 V.35 V.35 V.35 V.35 CMOS CMOS 8V –6.5V

RS449/V.36 1 0 1 0 TTL X V.11 V.11 V.11 V.11 Z Z V.11 V.11 V.11 V.11 V.11 V.11 CMOS CMOS 9.3V –6V

V.28/RS232 1 1 0 0 TTL X V.28 Z V.28 Z Z Z V.28 30k V.28 30k V.28 30k CMOS CMOS 8.7V –8.5V

No Cable 1 1 1 0 X X Z Z Z Z Z Z 30k 30k 30k 30k 30k 30k Z Z 4.7V 0.3V

Not Used(Default V.11) 0 0 0 1 TTL TTL V.11 V.11 V.11 V.11 V.11 V.11 30k 30k V.11 V.11 V.11 V.11 Z CMOS 9.3V –6V

RS530A 0 0 1 1 TTL TTL V.11 V.11 V.11 V.11 V.11 V.11 30k 30k V.11 V.11 V.11 V.11 Z CMOS 9.3V –6V

RS530 0 1 0 1 TTL TTL V.11 V.11 V.11 V.11 V.11 V.11 30k 30k V.11 V.11 V.11 V.11 Z CMOS 9.3V –6V

X.21 0 1 1 1 TTL TTL V.11 V.11 V.11 V.11 V.11 V.11 30k 30k V.11 V.11 V.11 V.11 Z CMOS 9.3V –6V

V.35 1 0 0 1 TTL TTL V.35 V.35 V.35 V.35 V.35 V.35 30k 30k V.35 V.35 V.35 V.35 Z CMOS 8V –6.5V

RS449/V.36 1 0 1 1 TTL TTL V.11 V.11 V.11 V.11 V.11 V.11 30k 30k V.11 V.11 V.11 V.11 Z CMOS 9.3V –6V

V.28/RS232 1 1 0 1 TTL TTL V.28 Z V.28 Z V.28 Z 30k 30k V.28 30k V.28 30k Z CMOS 8.7V –8.5V

No Cable 1 1 1 1 X X Z Z Z Z Z Z 30k 30k 30k 30k 30k 30k Z Z 4.7V 0.3V

SWITCHI G TI E WAVEFOR S U WW

Figure 14. V.11, V.35 Receiver Propagation Delays

Figure 13. V.11, V.35 Driver Propagation Delays

ODE SELECTIOW U

Table 1

3V1.5V 1.5V

50%10%

90%

tPLH

tr

0V

VO

VO

–VO

D

B – A

A

B

tPHL

tSKEW tSKEW 2846 F13

1/2 VO

f = 1MHz : tr ≤ 10ns : t f ≤ 10ns

50%10%

90%

tf

VOD2

–VOD2

0V

1.65V

0V

1.65V

tPLH

VOH

VOL

B – A

R

tPHL

2846 F14

f = 1MHz : tr ≤ 10ns : t f ≤ 10ns INPUT

OUTPUT

Note 1: Driver inputs are TTL level compatible.Note 2: Unused receiver inputs are terminated with 30k to ground. In addition, R2 and R3 are alwaysterminated by a 103Ω differential impedence (see Block Diagram on page 8).Note 3: Receiver Outputs are CMOS level compatible and have a weak pull up to VIN when Z.

Note 4: VDD values shown are typical values for VCC = 5V, VIN = 3.3V and TA = 25°C with LTC2846under full load for each mode.Note 5: VEE values shown are typical values for VCC = 5V, VIN = 3.3V and TA = 25°C with LTC2846under full load for each mode.

(Not

e 1)

(Not

e 1)

11

LTC2846

sn2846 2846fs

Figure 15. V.28 Driver Propagation Delays

Figure 16. V.28 Receiver Propagation Delays

SWITCHI G TI E WAVEFOR S U WW

APPLICATIO S I FOR ATIOWU UU

3V

0V1.5V

0V–3V

3V

1.5V

0V3V

–3V

tPHL

tf

VO

–VO

D

A

tPLH

tr

2846 F15

SR = 6Vtf

SR = 6Vtr

VIH

VIL

1.5V

1.65V

1.5V

1.65V

tPHL

VOH

VOL

A

R

tPLH

2846 F16

Overview

The LTC2846 consists of a boost switching regulator, acharge pump and a 3-driver/3-receiver transceiver. Theboost switching regulator generates a 5V VCC from the3.3V input at VIN to power the charge pump and trans-ceiver. The charge pump generates the VDD and VEEsupplies. The LTC2846’s VCC, VDD and VEE supplies canbe used to power a companion chip like the LTC2844 orLTC2845. The receiver outputs are driven between 0V andVIN to interface with 3.3V logic.

The LTC2846 and LTC2844 form a complete software-selectable DTE or DCE interface port that supports theRS232, RS449, EIA530, EIA530-A, V.35, V.36 and X.21protocols. Cable termination is provided on-chip, elimi-nating the need for discrete termination designs.

A complete DCE-to-DTE interface operating in EIA530mode is shown in Figure 17. The LTC2846 half of each portis used to generate and appropriately terminate the clockand data signals. The LTC2844 is used to generate thecontrol signals along with LL (Local Loopback).

Mode Selection

The interface protocol is selected using the mode selectpins M0, M1 and M2 (see Table 1).

For example, if the port is configured as a V.35 interface,the mode selection pins should be M2 = 1, M1 = 0, M0 = 0.For the control signals, the drivers and receivers willoperate in V.28 (RS232) electrical mode. For the clock anddata signals, the drivers and receivers will operate in V.35electrical mode. The DCE/DTE pin will configure the portfor DCE mode when high, and DTE when low.

The interface protocol may be selected simply by pluggingthe appropriate interface cable into the connector. Themode pins are routed to the connector and are left uncon-nected (1) or wired to ground (0) in the cable as shown inFigure 18. The internal pull-up current sources will ensurea binary 1 when a pin is left unconnected.

The mode selection may also be accomplished by usingjumpers to connect the mode pins to ground or VIN.

12

LTC2846

sn2846 2846fs

Figure 17. Complete Multiprotocol Interface in EIA530 Mode

APPLICATIO S I FOR ATIO

WU UU

When the cable is removed, leaving all mode pins uncon-nected, the LTC2846/LTC2844 will enter no-cable mode.In this mode the LTC2846/LTC2844 supply current dropsto less than 900µA and the LTC2846/LTC2844 driver out-puts are forced into a high impedance state. At the sametime, the R2 and R3 receivers of the LTC2846 are differ-entially terminated with 103Ω and the other receivers on

the LTC2846 and LTC2844 are terminated with 30kΩ toground.

Cable Termination

Traditional implementations used expensive relays toswitch resistors or required the user to change termina-tion modules every time a new interface standard was

LTC2846

DCEDTE

LTC2846

2846 F17

D3

R1 103Ω

103Ω

103ΩR3

LTC2844

D3

D4 R4

D2

R1

R4

R2

R3

LL

TXC

RXC

RXD

TXD

SCTE

TXC

RXC

RXD

SERIALCONTROLLER

D2 103ΩSCTE R2

D1 103ΩTXD R3

R1

D2

D1

LTC2844

D3

R2

R1

D1 R3

D2

D1

D4

TXD

SCTE

TXC

RXC

RXD

RTS

DTR

DCD

DSR

CTS

LL

RTS

DTR

DCD

DSR

CTS

RTS

DTR

DCD

DSR

CTS

LL

SERIALCONTROLLER

R2

D3

13

LTC2846

sn2846 2846fs

Figure 18. Single Port DCE V.35 Mode Selection in the Cable

Figure 20. V.10 Receiver Input Impedance

Figure 19. Typical V.10 Interface


WU UU

selected. Switching the terminations with FETs is difficultbecause the FETs must remain off when the signal voltageis beyond the supply voltage. Alternatively, custom cablesmay contain termination in the cable head or route signalsto various terminations on the board.

The LTC2846/LTC2844 chip set solves the cable termina-tion switching problem by automatically providing theappropriate termination and switching on-chip for theV.10 (RS423), V.11 (RS422), V.28 (RS232) and V.35electrical protocols.

V.10 (RS423) Interface

All V.10 drivers and receivers necessary for the RS449,EIA530, EIA530-A, V.36 and X.21 protocols are imple-mented on the LTC2844 or LTC2845.

A typical V.10 unbalanced interface is shown in Figure 19.A V.10 single-ended generator with output A and groundC is connected to a differential receiver with input A' con-nected to A, and ground C' connected via the signal returnto ground C. Usually, no cable termination is required forV.10 interfaces, but the receiver inputs must be compliantwith the impedance curve shown in Figure 20.

The V.10 receiver configuration in the LTC2844 andLTC2845 is shown in Figure 21. In V.10 mode, switch S3inside the LTC2844 and LTC2845 is turned off. Thenoninverting input is disconnected inside the LTC2844

NC

NC

CABLE

2846 F18

15

16

18

19

LTC2846

LTC2844

CONNECTOR

14

13

12

11

(DATA)

M0

M1

M2

DCE/DTE

DCE/DTE

M2

M1

M0

(DATA)

A A'

C C'

GENERATOR

BALANCEDINTERCONNECTING

CABLE LOAD

CABLETERMINATION RECEIVER

2846 F19

IZ

VZ

–10V

–3.25mA

3.25mA

–3V

3V 10V

2846 F20

14

LTC2846

sn2846 2846fs


Figure 21. V.10 Receiver Configuration




1Actually, there is no switch S1 in receivers R2 and R3. However, for simplicity, all terminationnetworks on the LTC2846 can be treated identically if it is assumed that an S1 switch exists and isalways closed on the R2 and R3 receivers.


WU UU

and LTC2845 receivers and connected to ground. Thecable termination is then the 30k input impedance toground of the LTC2844 and LTC2845 V.10 receiver.


A typical V.11 balanced interface is shown in Figure 22. AV.11 differential generator with outputs A and B andground C is connected to a differential receiver with inputA' connected to A, input B' connected to B, and ground C'connected via the signal return to ground C. The V.11interface has a differential termination at the receiver endthat has a minimum value of 100Ω. The terminationresistor is optional in the V.11 specification, but for thehigh speed clock and data lines, the termination is essen-tial to prevent reflections from corrupting the data. Thereceiver inputs must also be compliant with the imped-ance curve shown in Figure 20.

In V.11 mode, all switches are off except S1 of theLTC2846’s receivers which connects a 103Ω differential

termination impedance to the cable as shown in Figure231. The LTC2844 and LTC2845 only handle controlsignals, so no termination other than their V.11 receivers’30k input impedance is necessary.


A typical V.28 unbalanced interface is shown in Figure 24.A V.28 single-ended generator with output A and groundC is connected to a single-ended receiver with input A'connected to A and ground C' connected via the signalreturn to ground C.

R520k

LTC2844

RECEIVER

2846 F21

A

B

A'

B'

C'

R86k

S3

R610k

R710k

GND

R420k

A A'

B

C

B'

C'

GENERATOR


CABLE LOAD


100ΩMIN

2846 F22

R3124Ω

R520k

LTC2846

RECEIVER

2846 F23

A'

B'

C'

R151.5Ω

R86k

S2S3

R251.5Ω

R610k

R710k

GND

R420k

S1

A A'

C C'

GENERATOR


CABLE LOAD


2846 F24

R3124Ω

R520k

LTC2846

RECEIVER

2846 F25

A'

B'

C'

R151.5Ω

R86k

S2

S3

R251.5Ω

R610k

R710k

GND

R420k

S1

15

LTC2846

sn2846 2846fs

Figure 28. Charge PumpFigure 27. V.35 Receiver Configuration



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In V.28 mode, S3 is closed inside the LTC2846/LTC2844which connects a 6k (R8) impedance to ground in parallelwith 20k (R5) plus 10k (R6) for a combined impedance of5k as shown in Figure 25. Proper termination is only pro-vided when the B input of the receivers is floating, since S1of the LTC2846’s R2 and R3 receivers remains on in V.28mode1. The noninverting input is disconnected inside theLTC2846/LTC2844 receiver and connected to a TTL levelreference voltage to give a 1.4V receiver trip point.

V.35 Interface

A typical V.35 balanced interface is shown in Figure 26. AV.35 differential generator with outputs A and B andground C is connected to a differential receiver with inputA' connected to A, input B' connected to B, and ground C'connected via the signal return to ground C. The V.35interface requires a T or delta network termination at thereceiver end and the generator end. The receiver differen-tial impedance measured at the connector must be

A A'

B

C

B'

C'

GENERATOR


CABLE LOAD


2846 F26

50Ω125Ω

50Ω

50Ω125Ω

50Ω

R3124Ω

R520k

LTC2846

RECEIVER

2846 F27

A'

B'

C'

R151.5Ω

R86k

S2S3

R251.5Ω

R610k

R710k

GND

R420k

S1

100Ω ±10Ω, and the impedance between shorted termi-nals (A' and B') and ground (C') must be 150Ω ±15Ω.

In V.35 mode, both switches S1 and S2 inside the LTC2846are on, connecting a T network impedance as shown inFigure 27. The 30k input impedance of the receiver isplaced in parallel with the T network termination, but doesnot affect the overall input impedance significantly.

The generator differential impedance must be 50Ω to150Ω and the impedance between shorted terminals (Aand B) and ground (C) must be 150Ω ±15Ω.

No-Cable Mode

The no-cable mode (M0 = M1 = M2 = 1) is intended forthe case when the cable is disconnected from the con-nector. The charge pump, bias circuitry, drivers andreceivers are turned off, the driver outputs are forced intoa high impedance state, and the VCC supply current to thetransceiver drops to less than 300µA while its VIN supplycurrent drops to less than 10µA. Note that the LTC2846’sR2 and R3 receivers continue to be terminated by a 103Ωdifferential impedance.

Charge Pump

The LTC2846 uses an internal capacitive charge pump togenerate VDD and VEE as shown in Figure 28. A voltagedoubler generates about 8V on VDD and a voltage invertergenerates about –7.5V on VEE. Three 1µF surface mountedtantalum or ceramic capacitors are required for C1, C2 andC3. The VEE capacitor C4 should be a minimum of 3.3µF.All capacitors are 16V and should be placed as close aspossible to the LTC2846 to reduce EMI.

33

32

31

30

2846 F28

7

6

5

8

C31µF

C510µF

5V

C11µF

C21µF

C43.3µF

LTC2846

VDD

C1+

C1–

VCC

C2+

C2–

VEE

GND+

16

LTC2846

sn2846 2846fs


WU UU

Switching Regulator

The circuit as shown in Figure 29 can provide up to 480mAat 5V to drive the LTC2846’s transceiver as well as itscompanion chip in the DTE-DCE interface. In its shut downmode with the SHDN pin at 0V, the boost switchingregulator draws less than 10µA.

Ferrite core inductors should be used to obtain the bestefficiency, as core losses at 1.2MHz are much lower forferrite cores than for cheaper powdered-iron types. Choosean inductor that can handle at least 1A without saturating,and ensure that the inductor has a low DCR (copper wireresistance) to minimize I2R power losses.

Use low ESR capacitors for the output to minimize outputripple voltage. Multilayer ceramic capacitors are an excel-lent choice, as they have extremely low ESR and areavailable in very small packages. Ceramic capacitors alsomake a good choice for the input decoupling capacitor,and should be placed as close as possible to the switchingregulator. Solid tantalum or OS-CON capacitors can beused but they will occupy more board area than a ceramicand will have a higher ESR.

A Schottky diode is recommended for use with the switch-ing regulator. The ON Semiconductor MBR0520 is a verygood choice.

To set the output voltage, select the values of R1 and R2according to the following equation.

R1 = R2[(5V/1.255V) – 1]

A good value for R2 is 4.3k which sets the current in theresistor divider chain to 1.255V/4.3k = 292µA.

The switching regulator has a switch current limit of 1A.This current limit protects the switch as well as the exter-nal components connected to the switching regulator.

The high speed operation of the boost switching regulatordemands careful attention to board layout. Figure 30shows the recommended component placement.

Receiver Fail-Safe

All LTC2846/LTC2844 receivers feature fail-safe opera-tion in all modes. If the receiver inputs are left floating orare shorted together by a termination resistor, the receiveroutput will always be forced to a logic high.

DTE vs DCE Operation

The DCE/DTE pin acts as an enable for Driver 3/Receiver 1in the LTC2846, and Driver 3/Receiver 1 and Receiver 4/Driver 4 in the LTC2844.

The LTC2846/LTC2844 can be configured for either DTEor DCE operation in one of two ways: a dedicated DTE orDCE port with a connector of appropriate gender or a portwith one connector that can be configured for DTE or DCEoperation by rerouting the signals to the LTC2846/LTC2844using a dedicated DTE cable or dedicated DCE cable.

A dedicated DTE port using a DB-25 male connector isshown in Figure 31. The interface mode is selected by logicoutputs from the controller or from jumpers to either VINor GND on the mode select pins. A dedicated DCE portusing a DB-25 female connector is shown in Figure 32.

GND

VIN SW

SHDN FB

VIN3.3V

4 35

2846 F29

D1L1

5.6µH

2, 34

R113kBOOST

SWITCHINGREGULATOR

C510µF

C610µF

R24.3k

VCC5V480mA

C5,C6: TAIYO YUDEN X5R JMK316BJ106MLD1: ON SEMICONDUCTOR MBR0520L1: SUMIDA CR43-5R6

SHDN

3 36 R1

R2

2846 F30

GND

L1

VCC

VIN

SHUTDOWN

+C6

D1

+

C5

Figure 29. Boost Switching Regulator Figure 30. Suggested Layout

17

LTC2846

sn2846 2846fs

A port with one DB-25 connector, that can be configuredfor either DTE or DCE operation is shown in Figure 33. Theconfiguration requires separate cables for proper signalrouting in DTE or DCE operation. For example, in DTEmode, the TXD signal is routed to Pins 2 and 14 via theLTC2846’s Driver 1. In DCE mode, Driver 1 now routes theRXD signal to Pins 2 and 14.

Multiprotocol Interface with RL, LL, TMand a DB-25 Connector

If the RL, LL and TM signals are implemented, there are notenough drivers and receivers available in the LTC2846/LTC2844. In Figure 34, the required control signals arehandled by the LTC2845. The LTC2845 has an additionalsingle-ended driver/receiver pair that can handle two moreoptional control signals such as TM and RL.

Cable-Selectable Multiprotocol Interface

A cable-selectable multiprotocol DTE/DCE interface isshown in Figure 35. The select lines M0, M1 and DCE/DTEare brought out to the connector. The mode is selected bythe cable by wiring M0 (connector Pin 18) and M1 (con-nector Pin 21) and DCE/DTE (connector Pin 25) to ground(connector Pin 7) or letting them float. If M0, M1 orDCE/DTE is floating, internal pull-up current sources willpull the signals to VIN. The select bit M2 is floating, andtherefore, internally pulled high. When the cable is pulledout, the interface will go into the no-cable mode.

Power Dissipation Calculations

The LTC2846 takes in a 3.3V supply and produces a 5V VCCwith an internal switcher at approximately 80% efficiency.VDD and VEE are in turn produced from VCC with an internalcharge pump at approximately 80% and 70% efficiencyrespectively. Current drawn internally from VDD or VEEtranslates directly into a higher ICC. The LTC2846 dissi-pates power according to the equation:

PDISS(2846) = 125% • (VCC • ICC)– ND • PRT + NR • PRT (1)

TYPICAL APPLICATIO S

U

PRT refers to the power dissipated by each driver in areceiver termination on the far end of the cable while ND isthe number of drivers. Conversely, current from the farend drivers dissipate power NR • PRT in the internalreceiver termination where NR is the number of receivers.

LTC2846 Power Dissipation

Consider an LTC2846 in X.21, DCE mode (three V.11drivers and two V.11 receivers). From the Electrical Char-acteristics Table, ICC at no load = 14mA, ICC at full load =100mA. Each receiver termination is 100Ω (RRT) andcurrent going into each receiver termination = (100mA –14mA)/3 = 28.7mA (IRT).

PRT = (IRT)2 • RRT (2)

From Equation (2), PRT = 82.4mW and from Equation (1),DC power dissipation PDISS(2846) = 125% • (5V • 100mA)– 3 • 82.4mW + 2 • 82.4mW = 543mW.

Consider the above example running at a baud rate of10MBd. From the Typical Characteristic for “V.11 ModeICC vs Data Rate,” the ICC at 10MBd is 160mA. ICCincreases with baud rate due to driver transient dissipa-tion. From Equation (1), AC power dissipation PDISS(2846)= 125% • (5V • 160mA) –3 • 82.4mW + 2 • 82.4mW =918mW.

LTC2845 Power Dissipation

If a LTC2845 is used to form a complete DCE port with theLTC2846, it will be running in the X.21 mode (three V.11drivers and two V.10 drivers, two V.11 receivers and twoV.10 receivers, all with internal 30k termination). In addi-tion to VCC, it uses the VDD and VEE outputs from theLTC2846. Negligible power is dissipated in the largeinternal receiver termination of the LTC2845 so the NR •PRT term of Equation (1) can be omitted. Thus Equation (1)is modified as follows:

PDISS(2845) = (VCC • ICC) + (VDD • IDD)

18

LTC2846

sn2846 2846fs

+ (VEE • IEE) – ND • PRT (3)

Since power is drawn from the supplies of the LTC2846(VCC, VDD and VEE) at less than 100% efficiency, theLTC2846 dissipates extra power to source PDISS(2845) andPRT :

PDISS1(2846) = 125% • (VCC • ICC) + 125% • 125%• (VDD • IDD) + 125% • 143% • (VEE • IEE)– PDISS(2845) – ND • PRT= 25% • (VCC • ICC) + 56% • (VDD • IDD)+ 79% • (VEE • IEE) (4)

From the LTC2845 Electrical Characteristics Table, forVCC = 5V, VDD = 8V and VEE = – 5.5V:

ICC at no load 2.7mA

ICC at full load with all drivers high 110mA

IEE at no load 2mA

IEE at full load with both V.10 drivers low 23mA

IDD at no load 0.3mA

IDD at full load 0.3mA

The V.11 drivers are driven between VCC and GND whilethe V.10 drivers are driven between VCC and VEE. Assumethat the V.11 driver outputs are high and V.10 driveroutputs low. Current going into each 100Ω V.11 receivertermination = (110mA – 2.7mA) – 23mA/3 = 28.1mA.Current going into each 450Ω V.10 receiver termination =23mA – 2mA/2 = 10.5mA. From Equation (2), V.11 PRT =

79mW and V.10 PRT = 49.6mW.

From Equation (3), PDISS(2845) = 5V • (110mA – 23mA) +(8V • 0.3mA) + 5.5V • 23mA – 3 • 79mW – 2 • 49.6mW =228mW. Since the LTC2845 runs slow control signals, theAC power dissipation can be assumed to be equal to the DCpower dissipation.

The extra power dissipated in the LTC2846 due to LTC2845is given by Equation(4), PDISS1(2846) = 25% • (5V • 87mA)+ 56% • (8V • 0.3mA) + 79% • (5.5V • 23mA) = 210mW.So for an X.21 DCE port running at 10MBd, the LTC2846dissipates approximately 918mW + 210mW = 1128mWwhile the LTC2845 dissipates 228mW.

Compliance Testing

The LTC2846/LTC2844 and LTC2846/LTC2845 chipsetshave been tested by TUV Rheinland of North America Inc.and passed the NET1, NET2 and TBR2 requirements.Copies of the test reports are available from LTC or TUVRheinland of North America Inc.

The title of the reports are Test Report No.: TBR2/051501/02 and TBR2/050101/02

The address of TUV Rheinland of North America Inc. is:

TUV Rheinland of North America Inc.1775, Old Highway 8 NW, Suite 107St. Paul, MN 55112Tel. (651) 639-0775Fax (651) 639-0873


U

19

LTC2846

sn2846 2846fs

Figure 31. Controller-Selectable Multiprotocol DTE Port with DB-25 Connector

D2

D1

LTC2844

RTS

DTR

DSR

DCD

CTS

D3

R2

R1

R4

R3

LTC2846

LL

TXD

SCTE

TXC

RXC

RXD

M0

M1

M2

DCE/DTE

VCC

VDD

VCC

VEE

GND

2

14

24

11

15

12

17

9

3

1

4

19

20

8

23

10

6

22

5

13

18

7

16

2846 F31

C21µF

R113k

C11µF

C610µF

C31µF

C43.3µF

SCTE B

RTS A (105)

RTS B

DTR A (108)

DTR B

CTS A (106)

CTS B

LL A (141)

SG

SHIELD

DB-25 MALECONNECTOR

DCD A (109)

DCD B

DSR A (107)

DSR B

D4

VCC5V

SHDN

VIN3.3V

CHARGEPUMP


L15.6µH

+

337

354

36

D1MBR0520

3

5

6

8

9

10

11

12

13

14

15

1618

19

12

3

4

5

6

7

8

10

9

VIN15 VIN

3.3V

16

17

18

19

20

21

22

23

24

25

3231

30

29

28

27

26

25

24

23

22

21

20

17 VIN3.3V

26

27

28

C510µF

C91µF

C71µF

C81µF

M0

M1

M2

DCE/DTE

M0

M1

M2

11

12

13

14

D1

D2

D3

R1

R2

R3

TXD A (103)

TXD B

TXC A (114)

RXC A (115)

RXD A (104)

TXC B

RXC B

RXD B

SCTE A (113)

T

T

T

T

T

C101µF

R24.3k

VCC5V


U

20

LTC2846

sn2846 2846fs

Figure 32. Controller-Selectable DCE Port with DB-25 Connector


U

D2

D1

LTC2844

CTS

DSR

DTR

DCD

RTS

D3

R2

R1

R4

R3

LTC2846

LL

RXD

RXC

TXC

SCTE

TXD

M0

M1

M2

DCE/DTE

VCC

VDD

VCC

VEE

GND

3

16

17

9

15

12

24

11

2

1

5

13

6

8

22

10

20

23

4

19

18

7

14

2846 F32

C21µF

R113k

C11µF

C610µF

C31µF

C43.3µF

RXC B

CTS A (106)

CTS B

DSR A (107)

DSR B

RTS A (105)

RTS B

LL A (141)

SGND (102)

SHIELD (101)

DB-25 FEMALECONNECTOR

DCD A (109)

DCD B

DTR A (108)

DTR B

D4

VCC5V

SHDN

VIN3.3V

CHARGEPUMP


L15.6µH

+

337

354

36

D1MBR0520

3

5

6

8

9

10

11

12

13

14

15

1618

19NC

12

3

4

5

6

7

8

10

9

NC

VIN15 VIN

3.3V

16

17

18

19

20

21

22

23

24

25

3231

30

29

28

27

26

25

24

23

22

21

20

26

27

28

C510µF

C91µF

C71µF

C81µF

M0

M1

M2

DCE/DTE

M0

M1

M2

11

12

13

14

D1

D2

D3

R1

R2

R3

RXD A (104)

RXD B

SCTE A (113)

TXD A (103)

TXC B

SCTE B

TXD B

RXC A (115)

T

T

T

T

T

C101µF

R24.3k

VCC5V

17 VIN3.3V

TXC A (114)

21

LTC2846

sn2846 2846fs

Figure 33. Controller-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector


U

D2

D1

LTC2844

D3

R2

R1

R4

R3

LTC2846

M0

M1

M2

DCE/DTE

VCC

VDD

VCC

VEE

GND

2846 F33

C21µF

R113k

C11µF

C610µF

C31µF

C43.3µF

D4

VCC5V

SHDN

VIN3.3V

CHARGEPUMP


L15.6µH

+

337

354

36

D1MBR0520

3

5

6

8

9

10

11

12

13

14

15

1618

19

12

3

4

5

6

7

8

10

9

DCE/DTE

VIN15 VIN

3.3V

16

17

18

19

20

21

22

23

24

25

3231

30

29

28

27

26

25

24

23

22

21

20

26

27

28

C510µF

C91µF

C71µF

C81µF

M0

M1

M2

DCE/DTE

M0

M1

M2

11

12

13

14

D1

D2

D3

R1

R2

R3

T

T

T

T

T

C101µF

R24.3k

VCC5V

DTE_TXD/DCE_RXD

DTE_SCTE/DCE_RXC

DTE_TXC/DCE_TXC

DTE_RXC/DCE_SCTE

DTE_RXD/DCE_TXD

DTE_RTS/DCE_CTS

DTE_DTR/DCE_DSR

DTE_DCD/DCE_DCD

DTE_DSR/DCE_DTR

DTE_CTS/DCE_RTS

DTE_LL/DCE_LL

2

14

24

11

15

12

17

9

3

1

4

19

20

8

23

10

6

22

5

13

18

7

16

SCTE B

RTS A

RTS B

DTR A

DTR B

CTS A

CTS B

DSR A

DSR B

CTS A

CTS B

LL A

SG

SHIELD

DB-25CONNECTOR

DCD A

DCD B

DSR A

DSR B

RTS A

RTS B

LL A

DCD A

DCD B

DTR A

DTR B

TXD A

TXD B

TXC A

RXC A

RXD A

TXC B

RXC B

RXD B

TXC A

SCTE A

TXD A

TXC B

SCTE B

TXD B

SCTE A

RXC B

RXD A

DTE DCE

RXD B

RXC A

17 VIN3.3V

22

LTC2846

sn2846 2846fs

Figure 34. Controller-Selectable Multiprotocol DTE/DCE Port with RL, LL, TM and DB-25 Connector


U

D2

D1

LTC2845

DTE_RTS/DCE_CTS

DTE_DTR/DCE_DSR

DTE_DSR/DCE_DTR

DTE_DCD/DCE_DCD

DTE_CTS/DCE_RTS

D3

R2

R1

R4

R3

LTC2846

DTE_LL/DCE_RI

DTE_RI/DCE_LL

DTE_TM/DCE_RL

DTE_RL/DCE_TM

DTE_TXD/DCE_RXD

DTE_SCTE/DCE_RXC

DTE_TXC/DCE_TXC

DTE_RXC/DCE_SCTE

DTE_RXD/DCE_TXD

M0

M1

M2

DCE/DTE

VCC

VDD

VEE

GND

2846 F34

C21µF

R113k

C11µF

C610µF

C31µF

C43.3µF

D4

VCC5V

SHDN

VIN3.3V

CHARGEPUMP


L15.6µH

+

337

354

36

D1MBR0520

3

5

6

8

9

10

11

12

13

14

15

1618

19

1, 192

3

4

5

6

7

8

10

9

D518

DCE/DTE

VIND4ENB

R4EN

2015

16NC

VIN3.3V

23

R517 22

21

2524

26

27

28

29

30

31

32

33

3231

30

29

28

27

26

25

24

23

22

21

20

34

35

36

C510µF

C91µF

C71µF

VCC5V C8

1µF

M0

M1

M2

DCE/DTE

M0

M1

M2

11

12

13

14

D1

D2

D3

R1

R2

R3

T

T

T

T

T

C101µF

R24.3k

VCC5V

18

*

*OPTIONAL

21

25

LL

LL

RL

RLTM

TM

RI

RI

2

14

24

11

15

12

17

9

3

1

4

19

20

8

23

10

6

22

5

13

7

16

TXD A

TXD B

SCTE A

SCTE B

RXD A

RXD B

RXC A

RXC B

RXC A

RXC B

RXD A

RXD B

RTS A

RTS B

DTR A

DTR B

CTS A

CTS B

DSR A

DSR B

CTS A

CTS B

SG

SHIELD

DB-25 CONNECTOR

TXC A

TXC B

SCTE A

SCTE B

TXD A

TXD B

TXC A

TXC B

DCD A

DCD B

DSR A

DSR B

RTS A

RTS B

DCD A

DCD B

DTR A

DTR B

DTE DCE

17 VIN3.3V

23

LTC2846

sn2846 2846fs

Figure 35. Cable-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector


U

D2

D1

LTC2844

DTE_RTS/DCE_CTS

DTE_DTR/DCE_DSR

DTE_DSR/DCE_DTR

DTE_DCD/DCE_DCD

DTE_CTS/DCE_RTS

D3

R2

R1

R4

R3

LTC2846

DTE_TXD/DCE_RXD

DTE_SCTE/DCE_RXC

DTE_TXC/DCE_TXC

DTE_RXC/DCE_SCTE

DTE_RXD/DCE_TXD

M0

M1

M2

DCE/DTE

VCC

VDD

VCC

VEE

GND

2846 F35

C21µF

R113k

C11µF

C610µF

C31µF

C43.3µF

D4

VCC5V

SHDN

VIN3.3V

CHARGEPUMP


L15.6µH

+

337

354

36

D1MBR0520

3

5

6

8

9

10

11

12

13

14

15

1618

19NC

12

3

4

5

6

7

8

10

9

NC

VIN15 VIN

3.3V

16

17

18

19

20

21

22

23

24

25

3231

30

29

28

27

26

25

24

23

22

21

20

26

27

28

C510µF

C9 1µF

C71µF

C81µF

M0

M1

M2

DCE/DTE

11

12

13

14

D1

D2

D3

R1

R2

R3

T

T

T

T

T

C101µF

R24.3k

VCC5V

2

14

24

11

15

12

17

9

3

1

2521

18

4

19

20

8

23

10

6

22

5

13

7

16

RXD A

RXD B

RXC A

RXC B

RXC A

RXC B

RXD A

RXD B

RTS A

RTS B

DTR A

DTR B

CTS A

CTS B

DSR A

DSR B

CTS A

CTS B

SG

SHIELD

DCE/DTEM1M0

DB-25 CONNECTOR

TXC A

TXC B

SCTE A

SCTE B

TXD A

TXD B

TXC A

TXC B

DCD A

DCD B

DSR A

DSR B

RTS A

RTS B

DCD A

DCD B

DTR A

DTR B

DTE DCE

MODE V.35

RS449, V.36RS232

PIN 18PIN 7

NCPIN 7

PIN 21PIN 7PIN 7

NC

CABLE WIRING FOR MODE SELECTION

MODE PIN 25DTE PIN 7DCE NC

CABLE WIRING FORDTE/DCE SELECTION

TXD A

TXD B

SCTE A

SCTE B

17 VIN3.3V

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

24

LTC2846

sn2846 2846fs

LT/TP 0503 1K • PRINTED IN USA

LINEAR TECHNOLOGY CORPORATION 2002

RELATED PARTSPART NUMBER DESCRIPTION COMMENTSLTC1321 Dual RS232/RS485 Transceiver Two RS232 Driver/Receiver Pairs or Two RS485 Driver/Receiver Pairs

LTC1334 Single 5V RS232/RS485 Multiprotocol Transceiver Two RS232 Driver/Receiver or Four RS232 Driver/Receiver Pairs

LTC1343 Software-Selectable Multiprotocol Transceiver 4-Driver/4-Receiver for Data and Clock Signals

LTC1344A Software-Selectable Cable Terminator Perfect for Terminating the LTC1543 (Not Needed with LTC1546)

LTC1345 Single Supply V.35 Transceiver 3-Driver/3-Receiver for Data and Clock Signals

LTC1346A Dual Supply V.35 Transceiver 3-Driver/3-Receiver for Data and Clock Signals

LTC1543 Software-Selectable Multiprotocol Transceiver Terminated with LTC1344A for Data and Clock Signals, Companion toLTC1544 or LTC1545 for Control Signals

LTC1544 Software-Selectable Multiprotocol Transceiver Companion to LTC1546 or LTC1543 for Control Signals Including LL

LTC1545 Software-Selectable Multiprotocol Transceiver 5-Driver/5-Receiver Companion to LTC1546 or LTC1543for Control Signals Including LL, TM and RL

LTC1546 Software-Selectable Multiprotocol Transceiver 3-Driver/3-Receiver with Termination for Data and Clock Signals

LTC2844 3.3V Software-Selectable Multiprotocol Transceiver Companion to LTC2846 for Control Signals Including LL

LTC2845 3.3V Software-Selectable Multiprotocol Transceiver 5-Driver/5-Receiver Companion to LTC2846 for Control SignalsIncluding LL, TM and RL

Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 FAX: (408) 434-0507 www.linear.com

U

PACKAGE DESCRIPTIO

G36 SSOP 0802

0.09 – 0.25(.0035 – .010)

0° – 8°

0.55 – 0.95(.022 – .037)

5.00 – 5.60**(.197 – .221)

7.40 – 8.20(.291 – .323)

1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 1813

12.50 – 13.10*(.492 – .516)

2526 22 21 20 19232427282930313233343536

2.0(.079)

0.05(.002)

0.65(.0256)

BSC0.22 – 0.38

(.009 – .015)

MILLIMETERS(INCHES)

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDEDIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

*

**

NOTE:1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

0.42 ±0.03 0.65 BSC

5.3 – 5.77.8 – 8.2

RECOMMENDED SOLDER PAD LAYOUT

1.25 ±0.12

G Package36-Lead Plastic SSOP (5.3mm)(Reference LTC DWG # 05-08-1640)

features descriptio u - analog devices · 2020. 2. 1. · tbr2/050101/02, tbr2/051501/02 1.2mhz...

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