~ ANALOGW DEVICES

LowCostDualSlopeAID Converter

FEATURES3% BCD Digits or 11 Bits Plus SignAccepts Bipolar or Unipolar Input SignalsRequires Only +5V Power4OdBNormal Mode Noise RejectionAnalog Input Overvoltage ProtectedAutomatic Zero CorrectionCan Drive Display and/or Feed ComputerUser Choice of Three Triggering MethodsCapable of Ratiometric Operation

GENERAL DESCRIPTION

The ADC1100 is a dual slope integrating analog-to-digital con-verter with 3Y2BCD digit or 11 binary bit resolution. It acceptsan analog input signal within the nominal range of :t200mV,and converts the average value during the input integrationtime period to parallel output sign-magnitude BCD or sign-magnitude binary data. The unit is packaged in a small 2" x4" x 0.4" module, and requires only +5V power.

EXCELLENT NOISE REJECTIONBecause the ADCIIOO's output is based on the average valueof the input signal during the input integration time period, in-accuracies due to noise spikes are greatly suppressed. In addi-tion, with the input integration time period set equal to onecycle of the power line, the integral of any power line noise isequal to zero. This results in a normal mode power line noiserejection ratio of at least 40dB. By locking the input integra-tion time precisely to one period of the power line using anexternal phase locked loop, this ratio can be increased to overBOdB. Since the excellent noise rejection is achieved withoutany input filtering, the analog input settling time requiredprior to the commencement of a conversion is zero.

APPLICATIONS

With the only power required being +5V, and with its excellentnoise rejection, the ADC1100 is an ideal choice for installationat transducer locations. The BCD coded version is also well

suited for many behind-the-panel applications because it allowsthe instrument designer complete freedom in choosing a dis-play. For example, it may be desirable to share a single displaywith more than one digital output device, or to display a digitaloutput scaled quite differently from the ADCllOO/BCD's:tI99.9mV input range.

TIMING INFORMATION

As shown in Figure 1, each conversion begins with an auto-matic zero correction cycle. Polarity data is valid anytimeafter the completion of the input signal integration timeperiod, and it remains latched in one polarity until such timeas a conversion is performed with an input signal of theopposite polarity. The digital output data is valid no laterthan SOns prior to the READY output's "0" to "I" transi-tion. This "set up" time is sufficient to allow the output datato be strobed into a following register or latch on the READYoutput's "0" to "1" edge. In the event of an overrange inputsignal, the OVERLOAD output will go from "0" to "1" at theend of the conversion. It will remain latched in the "1" stateuntil a normal conversion has been performed.

TRIGGER f '-' III'",: S\G~~,\\o~ '1I1'f'cf'lIf"1I: ZERO \~'\I'-GI' =t: 1I"11'lgf'

INTEGRATOR 1 :CORRECT '11

.-833ms-t--'667ms t - H' 16 67ms

READY l ~~~~ I I

OVERLOAD !----

'Reference ;ntegration tome t? 20~~V x 16.67ms. In the event of an overloaded ;nput. tm" " Sams. IThe tim., shown are thme obt"ned when theun;!;s set for 60Hz noise re,ection.1

Figure 1. Timing Diagram

AID CONVERTERS 431~- ~-- --

OBSOLETE

SPECIFICATIUNS(typical @+25°Cand+5.0V dc unlessotherwisenoted)

MODEL

RESOLUTION

ACCURACYRelative to Full ScaleAbsolute

TEMPERATURE COEFFICIENTSGain TCOffset TC

INPUT CHARACTERISTICS

Input RangeInput ResolutionInput ImpedanceInput Bias CurrentOvervoltage ProtectionNormal Mode Rejection

CONVERSION TIMENormal ConversionOverload Conversion

ADC 11 OO/BCD ADCIIOO/BIN

3~ BCD digits plus sign 11 Bits Plus Sign

:to.05%:to.l %

**

:t50ppm/ C max:t2ppm/C max

**

:t199.9mVO.ImV/LSB101'1ohms min1.5nA max:t20V140dB min @ 60Hz2

:t204.7mV*****

42ms max370ms max

**

CONVERSION RATE

Internal TriggerExternal TriggerAutomatic

DIGITAL OUTPUTS4

Data OutputPolarity

Ready

Overload

4/sec0 to 20/sec20 to 40/sec

***

Positive True Logic *Logic "0" = Positive Signal *Logic "I" = Negative Signal *Logic "0" = Busy *Logic "1" = Ready *Logic "0" = Normal *Logic "1" = Overload *

*LOGIC INPUTSs

Trigger InputHold Input

POWER SUPPLY REQUIREMENTS

POWER SUPPLY SENSITIVITY

TEMPERATURE RANGE

OperatingStorage

2 TTL Unit Loads2 TTL Unit Loads

+5.00V de :t5%

@ 200mA typ,250mA max

0.01 %/%f::" V S

*

*

*

0 to +70oC

-25°C to +85°C

**

I Maximum voltage that can be applied to the input continuously without risking damage tothe unit. Up to :!:50V can be applied momentarily.

2Normal mode rejection at 50Hz is also 40dB minimum when unit is calibrated for 50Hznormal mode noise rejection.

3A normal conversion will take 42ms max when the unit is calibrated for 60Hz noise rejection.WheILset for 50Hz noise rejection, a normal conversion will take 50ms max.

4All digital outputs are rated at 6 TTL unit loads each, with a Logic "1";;' +2.4V @ 240/.LAmax,and a Logic "0".;; +0.4V @ -9.6mA max.

3The trigger and hold inputs are internally tied to pull-up resistors. It is thus assured thatthese inputs are maintained in the high state with no connections to them. For both in-puts, a Logic "1" ;;. +2.0V, and a Logic "0" .;; +0.8V @-3.2mA max.

Specifications subject to change without notice.

22

DATA

1

23

DUTPUTS 24

ISEE TABLE) 25

DATA OUTPUT PIN DESIGNATIONS

432 AID CONVERTERS--~--

OUTLINE DIMENSIONS ANDPIN DESIGNATIONS

Dimensionsshown in inches and (rom).

I 2.02 (51.3) MAX

~

-1

~:L(10.7)

+MAX.0.2 (5.1)

---L MIN.

80TTOM VIEW --11- GRID 0.1" (2.5)

NOTE:

Terminal pins installed only in shaded holelocations. Pins 33 and 34 installed in ADC1100/

BCD only. All pins are gold plated half-hardbrass, (MIL-G-45 2041,0.019 (0.48) dia0.2 (5.1) min. length.

For plug-in mounting card order Board No.AC1550

BLOCK DIAGRAMAND PIN DESIGNATIONS

HOLD 8

POLARITY 9READY 10

TRIGGER n

43 RAMP DOWN42 FREO. ADJ

n INPUT

67 ANALOG GRD

66 OFFSET

85 OVERLOAD

64 REF IN

1415'617

61 REF OUT

f' ~~,,=~

3132333435

40 DIGITAL GRD

39 CLOCK IN

38 CLOCK OUT

--.0 I 37 "VDC

~- --

PIN 14 15 16 17 22 23 24 25 31 32 33 34 35

ADCllOO/BCD 1 2 4 8 10 20 40 80 100 200 400 800 1000

ADC 11OO/BIN LSB Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 - - MSB

6 7

X<0::;

19 5N

18 55 gN0-i

1 f

OBSOLETE

CLOCK CONNECTIONS

The ADC1100 is normally connected to its own internal clock.This is accomplished by jumpering CLOCK OUT (pin 38) toCLOCK IN (pin 39). The internal clock is factory set to operateat a nominal frequency of 120kHz, which results in an inputsignal integration time period of 16 2I3ms. Since 16 2I3ms isequal to one cycle of a 60Hz power line, any 60Hz noiseappearing on the input will have an integral of zero, and thuswill not affect the digital output.

Under certain circumstances, it may be desirable to be able toadjust the internal clock's frequency. Figure 2 shows how thismay be accomplished with suitable connections to pin 42(which otherwise would have nothing connected to it).

20 Turn1000 ohms

R1 ADC1100

--'VV\r--O Pin 42

R2

-

Figure 2. Clock Frequency Adjustment

With R1 = 2200 ohms and R2 =470 ohms, this circuit can be

used to optimize the rejection of 60Hz normal mode noise.The potentiometer is used to adjust the input integration timeperiod to be exactly equal to one cycle of a power line that hasa nominal frequency of 60Hz. With R1 =470 ohms and R2 =2700 ohms, the clock will operate at a nominal frequency of100kHz. This gives an input integration time of 20ms, which isequal to one cycle of a 50Hz power line. The potentiometer isthen used to optimize the rejection of 50Hz noise.

GAIN ADJUSTMENTThe gain of the ADC11O0 is set with a 50 ohm, 20 turn poten-tiometer whose wiper is connected to pin 64. One end of thepotentiometer is connected to pin 60, and the other end topin 61. BCD coded units are calibrated by applying an inputsignal of 199.85mV and then adjusting the gain adjustmentpotentiometer until the converter's output is just on the vergeof switching between output codes 1998 and 1999. Binarycoded units are calibrated by applying a 204.65mV input andadjusting the gain potentiometer until the converter's outputis just on the verge of switching from 11111111110 to11111111111. If exact gain calibration is not required, the gainadjustment potentiometer can be deleted, and pins 60, 61, and64 are then jumpered together.

OFFSET ADJUSTMENT

The ADC1100 goes into an automatic zero correction cycle atthe beginning of each conversion. It does not, therefore, requireany external zero or offset adjustment. However, in the event

the input signal contains an externally generated offset of upto :t1mV, it could be cancelled out with the circuit shown inFigure 3 (pin 66 normally has nothing connected to it).

--

20 Turn10k ohms

+15V

47k ohms

'VVvADC1100

0 Pin 66-

-15V

Figure3. Offset Adjustment

TRIGGERING CONVERSIONS

The ADC1100 may be triggered in any of three ways. Thefirst is the easiest to implement. With no connections toTRIGGER (pin 11) or HOLD (pin 8), the unit will continuouslyperform conversions at the rate of about 4 conversions/second.With no connections to TRIGGER (pin 11), and with HOLD(pin 8) jumpered to READY (pin 10), the ADC1100 will per-form contInUOUSconversions, with a new conversion beginningas soon as the conversion in progress is completed. The READYoutput (pin 10) remains at a Logical "1" for approximatelylOOns between conversions. The conversion rate depends uponthe magnitude of the input signal. With the clock operating at120kHz (for optimum rejection of 60Hz noise), and with anonoverloaded input, that rate will vary from about 23/sec. toabout 40/sec.

Finally, the ADC1100 can be commanded to make a conversionupon receipt of an externally generated pulse. Figure 4A showshow the unit is triggered with a positive-going pulse, and Figure4B describes triggering with a negative-going pulse.

"1" n"O"--.J L.

200ns to 100115

ADC1100

~"1"

"0" -U ADC1100

200ns to£o - 8ms - 11

B.

A.

Figure 4. Externa/ Triggering

When using a positive-going trigger pulse the conversion com-mences (and the READY output goes from "I" to "0") ap-proximately lOOns after the leading edge ("0" to "1" transi-tion) of the trigger pulse. When using a negative-going pulse,the conversion begins about lOOns following the pulse'strailing edge ("0" to "I" transition). Should a trigger pulse bereceived while a conversion is in progress, it will be ignored,and the conversion in progress will continue to completion.

POWER AND GROUND CONNECTIONS

Digital ground (pin 40) and analog ground (pin 67) should betied together externally with a good ground bus connection.Care should be taken to ensure that no digital ground returnsignals are carried in the analog input's ground return lead.The +5V power input is internally bypassed with a 10JIFcapacitor, but additional bypass capacitance can be added ex-ternally if desired. Analog Devices' model 906 modular powersupply is an ideal power source for the ADC1100. It supplies+5V at up to 250mA.

AID CONVERTERS 433---

OBSOLETE

LATCHED DATA OUTPUTSWhen the digital outputs of the ADCI1O0/BCD are used todrive a display, it may be desirable to have the data latched tokeep the display from blinking. This can be easily accomplishedusing only two external digitallCs, as shown in Figure 5.Note that no latching circuitry is shown for the overload, sign,and "1000" outputs. None is required. These outputs arelatched, and, therefore, do not require eXternal latching. Thelatched data is updated on the "0" to "1" transition of theREADY output (pin 10), which occurs at the completion ofeach conversion.

ADCll00/BCD9

LATCHEDDATA

1014

1516

1722

23

I2

4B10

20

242531323334

40

BO

100200400BOO

Figure 5. External Data Latches

MAXIMUM POWER LINE NOISE REJECTIONWhen maximum rejection of power line originated noise isneeded, the circuitry shown in Figure 6 may be used to givethe ADCI1O0 a power line noise rejection ratio of over 80dB.This circuit is a phase locked loop that locks the input signalintegration time period to be exactly equal to one cycle of theline voltage applied to the primary of the 115V ac to 6. 3V actransformer.

It can be used with either 50Hz or 60Hz power lines. Becauseof the long time constant in the phase locked loop, it maytake as long as three minutes for the loop to lock onto thepower line frequency following initial power tUrn-on.

eo."eoN,.

CO",""ON VO<TAGE

Figure 6a. Phase Locked Clock Circuitry ForADC1100IBCD

eoN 38

eoN"

ceOCK

CORRECTOONVOUAGE

Figure 6b. Phase Locked Clock Circuitry ForADC1100lBIN

434 AID CONVERTERS

USING EXTERNAL COUNTERS

The ADCllOO can be used to produce an output pulse train,the number of pulses in which is proportional to the analoginput voltage. This pulse train output can be applied to exter-nal counters to implement nearly any counting scheme desired.For example, Figure 7 shows a circuit using the ADCl100/BCDwhich gives a full scale count of 9995, where the least signifi-cant digit has only two possible values, 0 or 5. The counterwould count in the following sequence: 1890, 1895, 1900,1905, etc.

L

BCD,INPUT DECODER/DRIVER/DISPLAYS

/'..:.'-,-,-,--1

/--,/ I--,

1

,-,/ I-, I

~I~~II

/-,L ...J

/--'

8141211 814121,

JUULOUTPUTPULSES ARE50 TO lOOn,WIDE

","

"o"JL

PULSE INITIATES CONVERSION

AND RESETS EXTERNAL

COUNTERS TO ZERO

V

PULSEGENERATING CIRCUIT

Figure 7. External Count-by-5 Counter

When designing external counter systems, it is only necessaryto remember that BCD coded units produce exactly 1999pulses and binary coded units produce exactly 2047 pulses forplus or minus full scale inputs. Smaller inputs yield propor-tionately smaller numbers of pulses. The "Pulse GeneratingCircuit" of Figure 7 can be used with either binary or BCDcoded units.

RA TIOMETRIC OPERATION

There may be instances where it would be desirable to measurethe ratio of two voltages, rather than the specific value of onevoltage. For example, the ratio of a strain gauge load cell'soutput to its excitation voltage may be highly accurate andrepeatable, but the excitation voltage itself may vary some-what. If the excitation voltage is applied to the reference input(pin 64) and the cell's output is applied to the analog input(pin 72), then the ADCllOO's digital output will be the ratioof the two: digital output =VIN/VREF x (Full Scale DigitalOutput). Thus, variations in the excitation voltage will notaffect the digital output. The voltage source driving the refer-ence input should have a source impedance of 10000hms orless. For best operation, the reference input voltage should bekept within the range of +100mV to +300mV, but in any casecannot exceed II V without risking damage to the unit. Careshould be taken to ensure that the reference voltage is accuratelyreferred to analog ground (pin 67). The ADCII00 will exhibita gain TC of Il5ppm/C or better in this mode of operation.

-

OBSOLETE