feature-level compensation & control
DESCRIPTION
F LCC. Feature-level Compensation & Control. Process Integration April 5, 2006. A UC Discovery Project. Year 2 Milestones. Si/Ge-on-insulator and Strained Si-on-insulator Substrate Engineering (M28 YII.13) - PowerPoint PPT PresentationTRANSCRIPT
Feature-level Compensation & Control
FLCCProcess IntegrationApril 5, 2006
A UC Discovery Project
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Year 2 MilestonesSi/Ge-on-insulator and Strained Si-on-insulator Substrate Engineering (M28
YII.13) Increase thermal robustness of GeOI by using nitrogen and ammonia plasma
for bonding. Use of pseudo-MOSFET structure to evaluate transferred layer electronic properties. Develop a thermal-mechanical model to predict transferred layer thickness and structural stability. Work with industrial sponsors to initiate SOI research.
Diffusion of oxygen in germanium (M29 YII.14) Determine the diffusion coefficient for the diffusion of oxygen in germanium,
including the temperature dependence and the activation energy of the diffusion. Investigate the effect of an SiO2 cap on the diffusion of Si in Ge. Initial experiments on interaction of fine patterns with diffusion.
Transient enhanced diffusion of B in Ge (Milestone added) Investigate the effect of ion implantation damage on the diffusion of B in Ge. Intermixing of germanium in SOI films (YII.15) Develop a process for selectively forming strained Si1-xGex-in-SOI by
intermixing Ge & Si
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Year 3 MilestonesSi/Ge-on-insulator and Strained Si-on-insulator Substrate Engineering (DEV Y3.1)
Prototype GeOI MOSFET performance evaluation. Demonstrate GeSiOI layer transfer using GeSi epi wafers. Investigate interfacial quality with high-K dielectric as buried insulator.
Effect of surface on diffusion in germanium (DEV Y3.2)
Utilize the test mask for the growth of thermal oxide and thermal nitride on Ge to systematically study the effects of the surface layers on diffusion in Ge.
Effect of implantation damage on the diffusion of dopants in Ge (DEV Y3.3)
Study the effect of ion implantation, in particular, end of range damage on the diffusion of common dopants in Ge. Determine if ion implantation damages have any transient effect on diffusion in Ge.
Characterization of Si1-xGex formed with Ge/Si intermixing process (DEV Y3.4)
Characterize the resistance of boron-doped Si1-xGex-on-insulator formed by the Ge/Si intermixing process. Characterize metal-to-Si1-xGex-on-insulator contact resistance and explore ways of lowering this to below 10-8 -cm2.
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Advanced Source/Drain Technology
FLCC Research Theme:• Low-resistance source/drain technology for thin-body FETs
– Si1-xGex source/drain to lower parasitic resistances
– Impact of dopant pile-up and strain on contact resistance
Nano-scale CMOS devices & technology• Materials & processes to improve performance and/or scalability of logic & memory ICs
Pankaj KalraTsu-Jae King
Source/drain design & process technology for nano-scale CMOS• Joined FLCC program in Year 2
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Si1-xGex Si1-xGexSi1-xGex Si1-xGex
Silicon Substrate
Source Drain
SiO2
SOI
GateGate
Silicon Substrate
Source Drain
SiO2
SOI
GateGate
Si1-xGex in the S/D regions will be
needed for thin-body PMOSFETs to• enhance mobility via strain • lower parasitic resistance
– S/D series resistance– contact resistance
Motivation
compressive strain 30% Idsat increase
Intel’s 90nm CMOS TechnologySi1-xGex in PMOS S/D regions to enhance on-state drive current without increasing off-state leakage
T. Ghani et al., 2003 IEDM Technical Digest
Substrate
Gate
Source Drain
Substrate
Gate
Source DrainLeff
Nsub
Xj
LgTox
Planar Bulk-Si Structure Thin-Body Structure
So
urc
e
Dra
in
Gate 2Gate 2
Fin Width Wfin = TSi
Fin Height = Hfin = W
Gate Length = Lg
Current Flow
Gate 1Gate 1
So
urc
e
Dra
in
Gate 2Gate 2
Fin Width Wfin = TSi
Fin Height = Hfin = W
Gate Length = Lg
Current Flow
Gate 1Gate 1
MOSFETscaling to Lg < 10nm Double-Gate “FinFET”
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Impact of Process Variations
Bulk-Si SRAMBeta-ratio = 1.5Mean=135mVSigma=16mV
FinFET SRAM6-T DG – 1-Fin Mean=175mVSigma=5mV
FinFET SRAM4-T w/ FeedbackMean=285mVSigma=6mV FinFET SRAM
6-T w/ FeedbackMean=300mVSigma=6.6mV
0.1 0.15 0.2 0.25 0.3 0.35
SNM (V)
SN
M D
istr
ibu
tio
n D
en
sit
y
10
20
30
40
50
60
70
80
90
100
0
Mixed-mode & MC simulations:
FinFET variations are due to parameter variations 3Lg = 3TSi = 10%Lg
Bulk-Si MOSFET variations are due to random dopant fluctuations only
Comparison of SRAM SNM Distributions
Z. Guo et al., Int’l Symp. Low Power Electronics and Design, 2005
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The Problem
• Contact Scaling– Due to reductions in active
area, silicide-to-Si contact resistance is now an issue
CONTACT AREA
Si
WPlugMSix
• High Rseries in p-channel thin-body FETs limits performance
TSi=10nm
F.-L. Yang et al., 2004 Symp. VLSI Technology
CMOS FinFET I-V Characteristics
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Approaches to Lowering c
• Material engineering– Si1-xGex source/drain
• Fermi-level de-pinning by interface passivation
• Image-force barrier lowering
• Strain-induced B reduction
K. Uchida et al., 2004 IEDM
BendingApparatus:
metal pad
active area
metal pad
active area
Kelvin Test Structure(plan view)
N
m Bc
*4exp
4
aN
si
qB
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Formation of Epitaxial Si1-xGex
• The conventional approach (epitaxial growth in a UHV-CVD tool) is difficult for ultra-thin body FETs Thin Si is etched away during the hydrogen pre-bake step!
• An alternative approach is to selectively deposit Ge by conventional LPCVD, then diffuse it into Si– GeH4 gas, 340oC, 300mT
high process throughput
Ge Source Ge Drain
TSi = 3 nm
Gate
SiO2Si
XTEM of UTB MOSFET w/ raised Ge S/D
Ge Source Ge Drain
TSi = 3 nm
Gate
SiO2Si
XTEM of UTB MOSFET w/ raised Ge S/D
GeGe
Silicon Substrate
TBOX
TSiSiO2
SOIGeGeGeGe SiO2SiO2 GeGe
Silicon Substrate
TBOX
TSiSiO2
SOIGeGeGeGe SiO2SiO2
Test Structure to study the intermixing of Ge with Si
(cross-section view)
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Milestones
Y2: Formation of Si1-xGex by intermixing Ge with Si– Process variables: anneal temperature, time, Ge doping
Y3: Characterization of Si1-xGex formed by intermixing– Parameters: Ge and B profiles, resistivity, contact resistance
– Investigation of approaches to lower c to <10-8 -cm2.
Y4: Fabrication of ultra-thin-body SOI PMOSFETs with Si1-xGex source/drain– Impact on hole mobility and parasitic resistance– Impact on variability (in on-state and off-state currents)
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Diffusion Studies in Ge and SiGe
Chris Liao, Judy Liang, and Prof. Eugene E. Haller
University of California at Berkeley and Lawrence Berkeley National Laboratory, Berkeley, CA
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Motivation
Substrate
Gate
Source Drain
Substrate
Gate
Source DrainLeff
Nsub
Xj
LgTox
Courtesy of Pankaj Kalra and Prof. Tsu-Jae King
Planar Bulk-Si MOSFET Structure
• SiGe and Ge are utilized in current and new generations of electronic devices to enhance performance
• Due to aggressive scaling of MOSFET, precise dopants profile control is crucial– Xj < 10 nm by 2008*– Extension lateral abruptness < 3
nm/decade by 2008*
• Advanced modeling and control of diffusion requires an improved basic understanding of diffusion processes in SiGe and Ge
*International Technology Roadmap for Semiconductors (ITRS), 2005
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Current Milestones
• Year 3 Milestone (2006): Investigate transient enhanced diffusion (TED) effects in Ge
– Determine the temperature dependent equilibrium diffusivity of B in Ge (in progress)
– Study the effect of ion implantation damage on B diffusion in Ge (in progress)
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The Problems
• Equilibrium diffusion and non-equilibrium diffusion effects are not well understood in Ge and SiGe
• Large discrepancies of diffusivity values of common dopants in Ge exist in the literature
• Non-equilibrium defect concentrations have been shown to enhance (or retard) dopant diffusion in Si
• Non-equilibrium transient effects on diffusion in Ge and SiGe are in progress
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Equilibrium Diffusion in Ge
• Diffusion in Ge is believed to be mostly vacancy-mediated (contrary to Si, where both vacancies and interstitials are involved)
• Interstitials and their effects in Ge have not been observed experimentally
Vacancy mechanism
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Contribution of Interstitial-Assisted Mechanism
• According to theory, for diffusion via the vacancy mechanism, the activation energy for impurity diffusion should be smaller than that for self-diffusion*
• Experiments show for Boron in Ge:
• An interstitial-assisted mechanism may need to be considered***Hu. Phys. Status Solidi B 60, 595 (1973).**Uppal et al. JAP 96, 1376, (2004).***Fuchs et al. Phy. Rev. B. 51, 16817 (1995).
123 )3.065.4(exp1097.1
scm
Tk
eVD
BB
123 05.00.3exp102.1
scm
Tk
eVD
BGe
**
***
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MBE-grown Boron Doped Multilayer Structure
Ge Substrate
B-doped layers
•B-doped multilayer structure is used to study equilibrium and non-equilibrium transient effects of B diffusion in Ge•Alternating layers of 100 nm Ge spacer and 10 nm B-doped layer •Grown by Dr. Stefan Ahlers and Prof. G. Abstreiter at the Walter-Schottky Institut, Munich
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Preliminary SIMS Results
0 200 400 600 8001016
1017
1018
1019
1020
As grown SIMS: 900C 18 min with Ge imp SIMS: 900C 18 min without Ge imp
Con
cent
ratio
n (a
tom
s/cc
)
Depth (nm)
• Samples were annealed at 900°C for 18 min
• Sample with Ge implantation shows slightly enhanced diffusion
• However, effects of implantation damage are still inconclusive from the preliminary results
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Future Milestones
Year 4 Milestone:
Self-diffusion in strained and relaxed isotopically enriched SiGe layers
Si substrate
SiGe graded buffer layer
100 nm nat. Si1-yGey
100 nm nat. Si1-yGey
200 nm 28Si1-x70Gex
• By varying x and y, compressive and tensile strains can be introduced
• This structure will be used to study effect of strain on Si and Ge self-diffusion in SiGe
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GSR: Eric Liu
Faculty PI: Prof. Nathan Cheung
Department of EECSUC-Berkeley
Fabrication and characterization of GeOI
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Motivations
High channel carrier mobility
Low metal contactresistance
High channel carrier mobility
Low metal contactresistance
GeOI p-MOS shows 3x mobility improvementNakahari et al, SSDM 2005
Ge
Si
•Ultra-short channel ballistic transport: initial velocity (“low field mobility”) is important
•Advantageous for low supply voltage
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2005 milestones:• Increase thermal robustness of GeOI• Use of pseudo-MOSFET structure to evaluate
transferred layer electronic properties2006 milestones:• Prototype GeOI MOSFET performance evaluation• Demonstrate GeSiOI layer transfer using GeSi epi wafers• Investigate interfacial quality with high-k
dielectric as buried insulator
Achievements GeOI shows good thermal robustness at 550oC Model analysis of GeOI pseudo-MOSFET Forming gas annealing reduces fixed interface
charges Qf but generates interface traps Qit
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2005-2006 Accomplishments
Ge donor wafer
Si Substrate
ImplantedHydrogen
GeOI
Pseudo MOSFET Characterization
0
0.5
1
1.5
2
2.5a s - b on d ed
a nn e ale d
G e (1 0 0 ) f r a c tu r e e n e r g y 1 .8 4 J /m 2
N2/SiO
2,220°C
P la s m a -A s s is te d B o n d in g S tre n g th
0
0.5
1
1.5
2
2.5a s - b on d ed
a nn e ale d
G e (1 0 0 ) f r a c tu r e e n e r g y 1 .8 4 J /m 2
N2/SiO
2,220°C
P la s m a -A s s is te d B o n d in g S tre n g th
G e (1 0 0 ) f r a c tu r e e n e r g y 1 .8 4 J /m 2
N2/SiO
2,220°C
P la s m a -A s s is te d B o n d in g S tre n g th
Eric Liu, UCB
The bonding interface charge < Qf ~1011/cm2, positive
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GeOI after 550oC, 1 hr annealing
The imperfections found
( Density: <10/cm2 )After annealing at sequential T:360°C, 500°C, 550 °Cfor 1 hour, respectively. No color change, blistering,peeling, etc.
•GeOI shows good thermal robustness
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Chemical-Mechanical-Polishing Set-up
Slurry
Platen
Pad
Wafer Fixture
CMP Set-Up: Lapping machine
Pad: (SBT Company)Polishing cloth Rayon-Fine 8” Diameter PSA P/N PRF08A-10Slurry: 0.2µm SiO2 particle mixed with KOH
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GeOI surface smoothing with CMP
•GeOI surface can be smoothed down to RMS =0.3nm by CMP•GeOI substrates are ready for device fabrication
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Pseudo-MOSFET : 4-probe-configuration
Heavily doped Si substrate
SiO2
I interface
Depletion region
I bulk
I surface
1234
p-Ge
xd
tGe-xd
VG
V2,3
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Forming gas annealing effects
VFBext=-6V
VText=+1V
VFBext=0V
VText=+7V
•Forming gas improves hole accumulation at Ge/SiO2 interface
•Forming gas reduces electron inversion at Ge/SiO2 interface
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-30 -20 -10 0 10 20 30
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.05
3.10
GeOI sample#4: T~360C forming gas annealing for 5 hrs
VG(-30V to +30V), I1,4=10uA VG(+30V to -30V), I1,4=10uA VG(-30V to +30V), I1,4=20uA VG(+30V to -30V), I1,4=20uA
G, (
squa
re/O
hme)
VG,(V)
•Forming gas decreases Qit, 0 to 5x1011/cm2
Interface traps (Qit) behavior of forming gas anneal
ReducedMobile carriersDue to traps
Ideal VT=+20V
G
,(x1
0-4/�
)
VG, (V)
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2006 Goals
• Qit reduction with surface encapsulation and optimized Temperature-Time cycles
• GeOI using Epi Ge wafer as donor wafer (with Yihwan Kim , AMAT)
• Prototype GeOI MOSFET with high-K dielectric and evaluation