fe-i4 irradiated chip tests at low temperature m. menouni, p. breugnon, a. rozanov (cppm -...
DESCRIPTION
September 9, 2013irradiated FE-I4 tests at low temperature3 Analog Test Configuration parameters : Amp2Vbn=79 Amp2Vbp=85 Amp2VbpFoll=26 Amp2Vbpf=40 PrmpVbp=43 PrmpVbpf=100 Vthin_AltFine=120 TDACVbp =150 Power : Ivddd=219 mA and Ivdda= 422 mA Analog Test with Amp2Vbpf=40 and Vcal=400Analog Test with Amp2Vbpf=40 and Vcal=1000TRANSCRIPT
FE-I4 irradiated chip tests at low temperature
M. Menouni , P. Breugnon, A. Rozanov
(CPPM - Aix-Marseille Université)
irradiated FE-I4 tests at low temperature 2September 9, 2013
Introduction The FE-I4-B chip number 162 was irradiated in 2012 at CERN PS with
24 GeV protons close to the region of end of columns It received a total dose of 1200 Mrad (800 Mrad + 400 Mrad) Tests at room temperature
Analog Tests Threshold level measurement and adjustment Threshold Scan and difficulties to tune Partial Tune results
Tests at low temperature (-26 °C) Out1 DC levels measurements PrmpVbp I(V) measurements Conclusion
irradiated FE-I4 tests at low temperature 3September 9, 2013
Analog Test
Configuration parameters : Amp2Vbn=79 Amp2Vbp=85 Amp2VbpFoll=26 Amp2Vbpf=40 PrmpVbp=43 PrmpVbpf=100 Vthin_AltFine=120 TDACVbp =150
Power : Ivddd=219 mA and Ivdda= 422 mA
Analog Test with Amp2Vbpf=40 and Vcal=400 Analog Test with Amp2Vbpf=40 and Vcal=1000
irradiated FE-I4 tests at low temperature 4
Effective Threshold measurement DC levels measurements through OABUF The effective threshold value becomes high
because of irradiation For the default value of Vthin_Altfine (= 120)
Chip 162 : The mean value of measured VthEff is 0.85V
Measured VthEff around 1.15 V for the chip 165
Decreasing the Vthin_Altfine to the minimum value does not help well The threshold still high >30000 e- beam spot center region
In order to decrease the effective threshold: TDACVbp is set to the highest allowed value
255 instead of the standard value of 150 The Vtheff is increased to 0.933 V. The resultant threshold is ~6000 e- Drawback : increase the TDAC step
For TDACVbp=255, the Analog test is OK with VCAL=400
September 9, 2013
irradiated FE-I4 tests at low temperature 5September 9, 2013
Threshold Scan
Threshold histogram before tuning Mean value=6269 e- and Sigma =840 e-
The majority of pixels have a reasonable noise : 150 e- RMS This noise reaches 900 e- RMS in the beam spot center region (most irradiated region) Many pixels in 2 columns 15 and 16 are always at 1 (counting of 100%)
Broken Columns : 15 and 16
irradiated FE-I4 tests at low temperature 6September 9, 2013
TDAC Tune DAC TUNE launched with a target threshold of 6500 e- A strange resultant TDAC map. Only 2 values 16 and 24 are
used for tune Most of TDAC values are set to 16 TDAC = 24 in the beam spot center region
High disparity between thresholds in high and low irradiated regions makes the tuning failed
In order to make the TDAC Tune possible : Regions with a very high threshold are disabled
DC number 16 to 28 are disabled The 2 columns in the left-middle of the chip are also disabled
DC number 8 to 9 disabled
irradiated FE-I4 tests at low temperature 7September 9, 2013
TDAC Tune results
Threshold Scan at room temperature Threshold histogram after tuning : Mean value=5511 e- Sigma =143 e- The tuning resolution is high because of the high threshold difference before tuning (and TDACVbp = 255 ?) Noise : 143 e- RMS
irradiated FE-I4 tests at low temperature 8
TDAC Map TDAC value at 16 : disabled
pixels High TDAC values for pixels
near the beam spot center region
Values from 0 to 8 not used during tuning
Tuning could be re-optimized
September 9, 2013
irradiated FE-I4 tests at low temperature 9
Test at Low Temperature (-26°C) Same configuration file at -26 °C
as for room temperature Threshold Scan shows a global
mean value of 3612 e- Individual Scurves show a
threshold above 10000 e- in the beam center region
The noise value is similar to the value at room temperature (150 e- RMS).
It reaches 700-800 e- RMS near the center region
Columns 15 and 16: many pixels are always counting
100%. Level stuck to "1"
September 9, 2013
irradiated FE-I4 tests at low temperature 10
TDAC Tune at low temperature (-26°C)
Tune with 4000 e- as target value
TDAC Tune failed for the whole array
Partial Tune : DC 8-9 and DC 18->26
disabled After tuning
Threshold Mean value=3959 e- Sigma =237e-
The tuning resolution is high because of the high threshold disparity before tuning
September 9, 2013
irradiated FE-I4 tests at low temperature 11
TDAC Map TDAC value at 16 for disabled
pixels High TDAC values for pixels
near the beam center region
September 9, 2013
irradiated FE-I4 tests at low temperature 12
DC level of out1 DC levels measured for
out1, out2 and vtheff through the OABUF
The out1 DC values are higher for the chip 162 Lowest value for the chip
162 : 356 mV Lowest value for the chip
165 is 230 mV LBL measurements on the
chip Ch27 show a lower DC value (80mV to 120 mV)
The chip 162 and 165 can be partially tuned even for the PrmpVbp value of 43
September 9, 2013
LBL Ch27 chip
Chip 165
Chip 162
irradiated FE-I4 tests at low temperature 13September 9, 2013
PrmpVbp I(V)
We don’t observe the high gate leakage current behavior for both irradiated chips (165 and 162)
PrmpVbp I(V) measurements show an increase in the threshold voltage for the pmos transistors. This increase is especially high for the chip 162
irradiated FE-I4 tests at low temperature 14September 9, 2013
Conclusion The chip 162 irradiated to a dose level of 1200 Mrad can be tuned
partially at room and at low temperature The whole array tune is failed because of the high disparity on the
thresholds for high and low irradiated regions Configuration parameters to set in order to reduce this disparity ?
An optimal Bias for the preamplifier and amplifier The effective threshold voltage can not be set to a low values for
the irradiated chip 162 TDACVbp set to 255 Other parameters to change ?
High gate leakage current behavior is not observed for the irradiated chip 165 (400 Mard) or for the irradiated chip162(1200 Mrad)