fault simulation - yonsei

Fault Simulation

Sungho Kang

Yonsei University

2Computer Systems Lab. YONSEI UNIVERSITY

Outline

l Introductionl Parallel l Deductivel Concurrentl PPSFPl Critical Path Tracingl PROOFSl PARISl Fault Samplingl Statistical Fault Analysisl Hardware Accelerationl Hierarchical Fault Simulationl Conclusion


IntroductionFault Simulation

fault-free

circuit

faulty circuit

Detected Undetected

SummaryFault

dictionary

Simulation

Output

Test Program

POs

PIs

Test Set

Fault List

Fault insertion

Test Application

+01


IntroductionApplication

l Evaluating Test Vectors l Generating Tests l Constructing Fault Dictionariesl Analyzing Circuits under Presence of Faults


IntroductionApplication: Evaluating Test Vectors

l Fault Coverage§ Ratio of the number of faults detected by a test vectors to the

number of total faults§ Represents approximation of defect coverage which is the

probability that test vectors detect physical defects

Parts FromTest

ProcessManufacturingLine

Bad PartsWhich Fail Test (BF)

Good Parts WhichPass Test (GP)

Bad Parts WhichPass Test (BP)

Defect Level =BP

GP + BP


IntroductionApplication: Evaluating Test Vectors

l Quality of Test§ Y : Yield§ DL: Defect Level§ d : defect coverage§ DL = 1 - Y 1-d

§ Consider a 0.5 yield processÄTo achieve 0.01 defect level, 99% coverage is requiredÄTo achieve 80% coverage, 0.2 defect level

1.0

0.8

0.6

0.4

0.2

0.00 20 40 60 80 100

defect level (%)

fault coverage (%)

Y = 0.01

Y = 0.1Y = 0.25

Y = 0.5

Y = 0.75

Y = 0.9

Y = 0.99


IntroductionApplication : Generating Tests

l Use fault simulation first l For remaining faults, use deterministic algorithm

100%

Number of Test Patterns

I : Functional or Random Patterns

II : Deterministic Patterns

0

II

I

FaultCoverage


IntroductionApplication : Fault Dictionaries

l Fault Dictionary § Stores the output response of every faulty circuit corresponding

to a fault§ Stores the signature

l Computing response before testingl Post-test Diagnosis§ Isolating a reduced set of plausible fault§ Simulating only these faults to identify the actual fault


IntroductionApplication : Analyzing Circuits

l Important in high-reliability systems l A fault can induce races and hazards not present in the

fault-free circuit l A faulty circuit may oscillate or enter a deadlock statel A fault can inhibit the proper initialization of a sequential

circuitl A fault can transform a combinational circuit into a

sequential circuit or a synchronous into asynchronous


IntroductionBasic Fault Simulation

l Fault Specificationl Fault Insertionl Fault Propagationl Fault Detectionl Post Processing


IntroductionFault Specification

l This is the activity which determines which faults and fault types will be modeled during simulation

l Normally the total set of faults to be considered is determined before any simulation takes place and is the first fault-related activity to occur

l Later certain techniques or heuristics can be used to reduce this fault set but the resulting fault set is a subset of the one that is initially


IntroductionFault Insertion

l Fault insertion in a fault simulation system is very analogous to the process of physical fault insertion for a fabricated machine

l It can also be termed a fault transformation, where the fault free network is transformed into a network which contains a physical defect or fault

l This process can occur once for a given fault, before fault simulation begins, or it can occur numerous times during a fault simulation process, for each fault that is being modeled


IntroductionFault Propagation

l A fault simulation system obviously must have the ability to propagate the effects of a fault

a

bc

Stuck-at-0

b=1 fault propagation to c·

b=0 fault is not propagated


IntroductionFault Propagation

l (a)§ Fault is propagated

l (b)§ Fault is propagated

through multiple pathsl (c)§ Fault is blocked

G2

G1

G3

G41/0

0/1

1/1

1/0

(a)

a = 1/1

b = 1/1

c = 0/0

d = 0/0

stuck-at-0

G2

G1

G3

G41/0

0/1

0/1

1/0

(b)

a = 1/1

b = 1/1

c = 0/0

d = 1/1

s-a-0

G2

G1

G3

G41/0

0/1

1/0

(c)

a = 1/1

b = 1/1

c = 0/0

d = 1/1

s-a-0

0/1


IntroductionFault Detection

l A fault simulation system must have the ability to determine when a fault has become observable at some given point or primary output of the object network

l Whether this activity takes place concurrently with the actual simulation or at the end of a fault simulation pass depends on other attributes of the simulator


IntroductionPostprocessing

l The fault simulation of a given digital network can result in a large amount of data which the user must interpret and efficiently utilize

l In an attempt to aid the user in this process one of the last activities which a fault simulation system performs is to organize the resulting data in a way which makes it most amenable to the user

l This activity can actually take place as a stand alone process


IntroductionMethods

l General§ Serial§ Parallel§ Deductive§ Concurrent

l Combinational § PPSFP§ Trace-based§ Combined

l Synchronous Sequential§ PROOFS§ PARIS


Parallel SimulationSerial Fault Simulation

l Simplestl Consider fault one at a timel No special fault simulator is requiredl Can handle any types of faultsl Impractical§ Excessive amount of CPU time


Parallel SimulationParallel Fault Simulation

l A good circuit and w faulty circuits are simulated simultaneously passes are required§ w : number of bits of the host machine

W-1 0

Word 1

Bit 0 = Fault-Free ValueBit 1 ~ (W-1) = Faulty Value

cab

g f2f1 f3 f4 f6f5 f7

a 0 1 1 0 1 0 0 1b 1 0 1 1 0 1 1 1

a·b 0 0 1 0 0 0 0 1a 1 1 0 1 1 1 1 0



l One good machine Good Circuit

Circuit with Fault 1

Circuit with Fault 2

Circuit with Fault n

TestPattern

+

+

+


Parallel SimulationFault Insertion

l 2 input ANDa

b

c

a s-a-1

b s-a-1

c s-a-0

c s-a-1

Fault List

01234567

as-a-1

bs-a-1

cs-a-0

cs-a-1

Unused

012347 - 5

00000a

11111b

01001c

a=0, b=1 simulation

FaultDetection

Good

Fault Insertion


Parallel Simulation3 Valued Logic

l Encoding§ 1 = 10§ 0 = 00§ X = 01§ Not used = 11

l 2 input AND C=AB§ C1 = A1&B1§ C2 = A2&B2 | A1&B2 | A2&B1



l 2 input AND Evaluation

signal A 1 0 1 1 1 0

word 1 A1

1 1 0 1 0 0

word 2 A2

1 0 0 0 0 0

B2

signal B 1 1 1 0 0 0

word 1 B1

AB

signal C 1 0 1 0 0 0

C1

1 1 0 0 0 0

C2



l Encoding§ 0 = 01§ 1 = 10§ X = 00§ Not used = 11

l 2 input AND C=AB§ C1 = A1&B1§ C2 = A2|B2

l 2 input OR C=A+B§ C1 = A1|B1§ C2 = A2&B2

l NOT C=~A§ C1 = A2§ C2 = A1



l 3 Valued Logic : Mask§ MASK1 MASK2§ 0 0 No fault§ 0 1 Stuck-at-X§ 1 0 Stuck-at-0§ 1 1 Stuck-at-1

§ V1 = V1 MASK1’ + MASK2§ V2 = V2 MASK1’ + MASK2 MASK1’



l 3 Valued LogicAB

CJ

SA1(F1)

SA1(F2)

F3 : AND -> NAND

1 1 1 1F3 F2 F1 G

A

0 0 0 0B

1 1 1 0C



l Set appropriate bit to 0 to 1l Fault masks§ s-a-0: 111···10111···1: AND to value vector§ s-a-1: 00000···010···0: OR to value vector

Faults simulated:α,β,γ, a/1, b/1, c/0, c/1

A 0 1 0 0 0 0 1 0B 1 1 1 0 0 1 1 1

m1(a/1)0 1 0 0 1 0 1 01 1 1 0 0 1 1 1

C 0 1 0 0 0 0 1 01 1 1 1 1 1 0 10 1 0 0 0 0 0 00 0 0 0 0 0 0 1

A1

0 0 0 0 1 0 0 0 Insert a/1

B1A + m1(a/1)

A1· B1

m0(c/0)

C1

m1(c/1)

0 1 0 0 0 0 0 1C2 C + m1(c/1)Insert c/1C · m0(c/0)

α β γ a/1 b/1 c/0 c/1


Parallel Simulation3 Values

l Coding

0b b1 b0

0 11 1 0U 0 0

l Other logic operations:c = a + b: c0 = a0· b0 , c1 = a1 + b1

c = a : c0 = a1 , c1 = a0

l Vector-pairs for logic values

l Logic operations: c = a·b

c0 = a0 + b0 , c1 = a1 · b1

0a a1 a0

0 11 1 0U 0 0

0c 0 1

0 01 0 1U 0 U

U0UU

100 1 0

c0 1 01 11 0

0100

010 0 0

c1 0 10 00 1

0000


Parallel SimulationExample

c = a · b

C1 = A0 + B0 = 1 1 1 0C0 = A1 · B1 = 0 0 0 0

c/0 c/1 αA = 1 U 0 UB = 0 0 0 U

A1 = 1 0 0 00 0 1 0A0 =

B1 = 0 0 0 01 1 1 0B0 =



l Two masks per fault

l m1(c/0) = 1 0 1 1; m0(c/0) = 0 1 0 0

l m1(c/1) = 0 0 1 0; m0(c/1) = 1 1 0 1

l Inserting c/0

c1 = c1 · m1(c/0), c0 = c0 + m0(c/0)

l Inserting c/1

c1 = c1 + m1(c/1), c0 = c0 · m0(c/1)



l Apply all vectors against one group of faults

generate a fault listfor all faults which are not detected

for all patternsinitialize the circuitchoose a pattern which is not simulatedselect 31 faults which are not detectedfault simulation with fault insertionfault detection

endend



l Apply one vector against all faults

generate a fault listfor all patterns

choose a pattern which is not simulatedinitialize the circuitfor all faults which are not detected

select 31 faults which are not detectedfault simulation with fault insertionfault detection

endend



l Possible to reduce the number of passes by simulating several independent faults simultaneously§ Independent faults can be simulated in the same bit§ Least upper bound is p number of POs

l F/(Wp) passes are requiredl Limitations§ Requires Boolean equation models ÄLogical operations only

§ Complex for multi-valued logic § Cannot use selective traceÄFault dropping is not effective


DeductiveDeductive Fault Simulation

l Simulates a good circuit and deduce all faulty circuitsl Only a few faults may produce values different from fault-

free valuesl Keep fault-free values and differences

l Parallel§ 0 1 2 3 4 5 6 7§ 1 1 1 1 0 1 0 1

l Deductive§ {4,6}



l AND§ (a) a=b=1

§ (b) a=0, b=1

§ (c) a=b=0

a = 1

b = 1c = 1

Fc = ( Fa U Fb ) U { c stuck-at-0 }

(a)

a = 0

b = 1c = 0

Fc = ( Fa - Fb ) U { c stuck-at-1 }

(b)

a = 0

b = 0c = 0

Fc = ( Fa Fb ) U { c stuck-at-1 }

(c)

U



l N input AND

a1 = 0

am = 0am+1= 1

an = 0

c = 0

Fc = ((Fa1 Fa2 --- Fam ) - ( Fam+1 U Fam+2 U --- U Fan ))U { c stuck-at-1 }

U U

37C o m p u t e r S y s t e m s L a b . YONSEI UNIVERSITY

DeductiveFault List

l Set of single faults that will complement the fault-free(true) value at a line

l Example:

let A,B,C be fault lists at a,b,c, respectivelya=0, A={1,3,4,6}b=1, B={3,6}

What is C?C= A – B ={1,4}

a

b

0

1c 0


DeductiveFault List

l Set of single faults that will complement the fault-free value at a line

l Example§ 2 input AND C=AB where A=0 and B=1§ fault list of A = {1,3,4,6}§ fault list of B = {4,6}§ fault list of C= A-B = {1,3}


DeductiveGate Evaluation

l Determine good value at the gate outputl Determine fault list on the gate output§ Fault effect that propagate through gate§ Local fault to be inserted

l Notation§ Lower case letters : lines§ Upper case letters : fault lists on corresponding lines


DeductiveFault Propagation

l Deduce output fault list of a gate from input true values and fault list

B=A

a=1,b=0,c=0;d=0D=B∩C – A

a=1,b=0,c=0;d=0

D=A – B – C

a b

abc

d

abc

d


DeductiveFault Propagation

Fault Propagation Through Primitive Gates

c = controlling logic value of gate

I = set of gate inputs

C = set of gate inputs with true value = c

z = gate output

Lj = fault list on j

If C = φ, then Lz = ∪j∈I Lj

Else Lz = {∩j ∈C Lj} – {∪i ∈ ( I – C ) Li}


DeductiveComputed Fault List

Correction of Computed Fault List

l Let a=0, A={α,β,c/1}b=1, B = φ

l But, c/1 can’t be detected. So c/1 must be deletedl After computing this fault list propagating to a line j, it

must be checked for consistencyl If j =vj, = Lj – { j/vj }

where is the corrected fault list, and Lj is the propagated fault list

Lc

j

Lc

j

ab

c



l When a fault list is computed, new one should be compared to old one

l More complex for feedbacksl More complex for memory elements§ Repeat until stabilization§ Consider as a primitive

S

R

10

10

11y1

01y2

(b)

S

R

LS

11

LR

10

~L1,L1

00y1

11

~L2,L2y2

(a)



l Fault Storage § Linked List§ Sequential Table§ Characteristic Vector


DeductiveExample

l Example§ V1 = <a,b,d> = <0,1,0>§ V2 = <a,b,d> = <0,1,1>

Vector 1a=0, { a/1 }; b=1, { b/0 }; d=0, { d/1 }c=1, { b/0, c/0 }; h=1,{ b/0, h/0 }e=1; E = ( A–H ) ∪ { e/0 }={ a/1, e/0 }f=0; F=(D–C) ∪ {f/1}={ d/1, f/1 }

g=1; G=(E-F) ∪ {g/0}={ a/1, e/0, g/0 }

a

b

d

c

e

f g

h


DeductiveExample

l Vector 2d=1, { d/0 }f=1; F=(C∪D) ∪ { f/0 }

={ b/0, c/0, d/0, f/0 }g=1; G=(E ∩ F) ∪ { g/0 }={ g/0 }

a

b

d

c

e

f g

h


DeductiveExample

`

`

ab

1

1 c

d

i

e0

0

h

1

1k

0

l1j

f

g

1

m

n

0

0

p00


DeductiveUnknown Values

l Fault-free values : { 0,1,U }

l Faulty values : { 0,1,U }

l Cannot represent with one fault list

l Approximation : Star faults§ Example

Äa=1, A={ α,β * }

ÄWith fault α, a = 0

ÄWith fault β, a = U

§ β * ∈ A : not known whether β ∈ A or β ∉ A


DeductiveInformation Loss with Star Faults

l Fault-free / faulty values - true value, fault listl Assume a single fault α

0/0 0,{}0/1 0,{α}0/U 0,{α*}1/0 1,{α}1/1 1,{}1/U 1,{α*}U/0 U,{}U/1 U,{}U/U U,{}

l Unable to distinguish U/0,U/1,U/U: potential loss of information



l Advantages§ Fast§ Large number of faults

l Limitations§ Compatible only in part with functional level modeling§ Cannot take full advantage of selective trace § Inaccuracy in some cases : unknown values§ Large memory requirements


ConcurrentConcurrent Fault Simulation

l Simulates good circuit and simulates only faulty circuits that are different from the one in good circuit

l Concurrent Fault List

l Directly applicable to functional level modelingl Requires lots of memory



l Explicit simulation of fault-free and faulty circuits as in serial

l Keep differences between faulty and fault-free as in deductive

0α0 1

0β0 0

1r

1 0

a 0,{r}0,{r}

b

a c1

0

b

0

ConcurrentDeductive

1,{α,β}


ConcurrentAlgorithm Features

l Separate fault-free and faulty eventsl Independent evaluationsl Keep only faulty states that are different from fault free

states: delete others (convergence)(convergence)l Create faulty states when they become different from

fault-free (divergence)(divergence)


ConcurrentFault Insertion

l Faults in each gate inserted in its CFL(Concurrent Fault List) at the beginning of simulation

l Local faults not deleted during convergence operationl Special evaluation of faulty gatesl Initialization§ Simulate after fault insertion


ConcurrentFault List Changes

l 1/0 good event propagated

to a

l 0/1 good event on a(0) also

updates the input a(α) to 0

l Once evaluating the output

c(0), 0/1 good event on c(0)

occurs

a

α

a1

d

cb

c1

d1

β

α

e

1/0 good event

11

1

10

1

1

00

0

0

0

0

0

0

1

1

1

1

1

1

1

11



l Update c(0) to 1

l Fanout processing :

§ Propagate the changed value

1 on c(0) and the newly visible

value 0 on c(a1) to fanout

l Updates the input c(0) to 1

a

α

a1

d

c

c1

d1

β

α

e

1/0 good event a1 newly visible

10

1

10

0

1

01

0

0

0

0

0

0

1

1

1

1

1

1

1

11

b



l a1 becomes newly visible on the fanout gate : Divergence

§ Copy all values from the good state of the corresponding gate

§ Change the input c(a1) to 0 obtained by fanout processing

l Don’t converge the faulty state(c1) because c1 is a local

fault



l Updates the input c(d1) to 1§ Once evaluating the output

e(d1), 1/0 faulty event on e(d1) occurs

l Updates input c(β) to 1§ Once evaluating the output

e(β), 1/0 faulty event on e(β) occurs

a

α

a1

d

c

a1

c1

β

e

1/0 event in circuit d11/0 event in circuit β

10

1

10

0

1

01

0

1

1

1

1

0

1

1

0

0

0

1

1

10

d1

b


ConcurrentConvergence

l When state of faulty gate = state of good gate,

delete state of faulty gate

l When gate output is updated

§ If good state changed

ÄCompare all faulty with good ( after faulty update )

§ If only faulty states changed

ÄCompare changed faulty with good


ConcurrentDivergence

l Create a faulty gate when its state becomes different from

good state

l Done at fanout propagation

l Copy good state : change fan-ins that are different


ConcurrentFanout Processing

l Propagate changed values

l Propagate newly visible values

l If good value changed, propagate it to gates in CFL of

fanout gate(s) that are not in CFL of source gate


ConcurrentFanout Processing

A

B

C A

B

C

α α

β β

α

β

β

1

1

11

11

0

00

0

0

00

0

0

0

0

0

000

0

0

00

1

1

1

0 10 10 1

0 10 1

0 1

a

b

c

b(0): 0/1 Good event c(0): 0/1 Good event

b( α ): newly visible: 0 c(α ): α newly visible: 0


ConcurrentExample

l a(0) : The good event 0/1

arrived on a(0)

l a(β) : Newly visible: 0

l Update the output of G1 to 0

l Now what happen ?

0/11/0

1

11

11

1

1

0

0

0

010

0

10

01

11

00

11

00

11

1

a

b

c

d

e

a/1

f

a/1

α

γ

δ

α

βγ

G1G2

G3

1


ConcurrentExample

l Fanout processing : fanout

data preparation

§ e(0): Good event 1/0

§ e(β): Newly visible: 1

0/11/0

1

11

11

1

1

0

0

0

010

0

10

01

11

00

11

00

11

1

c

d

e

a/1

f

a/1

α

γ

δ

α

βγ

G1G2

G3

g

Convergence

Newly visible

Nothing to do

a

b


ConcurrentExample

l Fanout processing :

Fanout data propagation

§ Propagate the good event 1/0 to

the input e(0) of G1

§ Propagate the good event 1/0 to the faulty inputs of G1: e(α), e(γ), e(a/1)

§ Divergence G2(β)

§ Update the output g(0) to 1§ Convergence G2(α)§ Convergence G2(a/1)

0/11/0

1

1/01

11

0

1

1

0

0

1

10

0

11

00

11

1

c

d

e

f α

γ

δ

11

00

a/1

β

10

01/0

a/1

β

γ

G1G2

G3

g

Divergence

Need to update

a

b

1

1



g = 1

f = 0

c2

e = 1 e1

e2

c = 1 c1

d = 0

a = 0

b = 0A

BC

A

a s-a-1

b s-a-1

c s-a-1

a b c

1 0 1

0 0 1

0 1 1

0 0 0

a, b, c : FO

B

Fault-free

d s-a-1

c1 s-a-1

e s-a-0

c1 d e

1 1 1

1 0 1

0 0 0

1 0 0

c1, d, e : FO

c s-a-0 0 0 0

c : FE

C

Fault-free

e1 s-a-0

f s-a-1

g s-a-1

e1 f g

0 0 1

1 0 1

1 1 0

1 0 0

e1, f, g : FO

c s-a-0

c1 s-a-0

e s-a-0

0 0 1

0 0 1

0 0 1

c, c1, e : FE

Fault-free



g = 0

c2

e = 1 e1

e2

c = 1 c1

d = 0

b = 0A

BC

A

Fault-free

a s-a-0

b s-a-1

c s-a-0

a b c

0 0 1

1 0 1

1 1 0

1 0 0

a, b, c : FO

B

Fault-free

d s-a-1

c1 s-a-1

e s-a-0

c1 d e

1 1 1

1 0 1

0 0 0

1 0 0

d, c1, e : FO

b s-a-1

b, c : FE

c s-a-0 0 0 00 0 0

C

Fault-free

e1 s-a-0

f s-a-0

g s-a-1

e1 f g

0 1 1

1 1 0

1 0 1

1 1 1

e1, f, g : FO

c s-a-0c1 s-a-1

e s-a-0

0 1 1

0 1 1

0 1 1

b, e, c, c1 : FE

b s-a-1

0 1 1

a = 0 1

f = 0 1


ComparisonFeatures of Three Methods

l Parallel and deductive§ Logic expression only

ÄOther expression → BooleanÄValues → binary encodingÄCHDL statements → Boolean expressions

l Concurrent§ No restrictions on :

Äelement typesÄvaluesÄdelay models


ComparisonComparison of Three Methods

Values

Elements

Storage

Delays

Fault-dropping

Par

binary

logic

min / fixed

restricted

not useful

Conc

any

any

max / variable

any

yes

Ded

binary

logic

med / variable

restricted

yes


PPSFPPPSFP

l Parallel Pattern Single Fault Propagation§ Single fault propagation§ Parallel pattern evaluation

l Advantage§ Simple and efficient.§ Selective trace: Single fault propagation§ Signals whose values are identical in the fault free circuit and the

faulty circuit are not recalculated.l Limitation§ Fails to consider the timing environment.§ Since it does not work like event driven simulation, it is limited to

devices which are combinational.§ Faults which can produce races or hazards, which can make a

circuit oscillate, and which can change a combinational circuit into a sequential one, require additional considerations.


PPSFPPPSFP

l Example § Fault Free Circuit Evaluation

§ Consider C s-a-0 fault

l Pattern 001 or 011 can detect the fault


PPSFPPPSFP

l Example § Consider B s-a-0 fault

§ After D evaluation, simulation stops since the result is the same as the fault free evaluation

§ Try other patterns


PPSFPPPSFP Algorithm

l for all patternsl choose 32 patterns which are not simulatedl simulate a good circuitl record the valuesl for all faults which are not detectedl select a faultl simulate a circuit under this faultl if the value is the same as the value in the previous

fault-free simulation after fault insertionl stop simulationl else continuel detect a fault at primary outputsl if the fault is detectedl delete the fault from the fault listl endl end


Crithical PathTrace Based Simulation

l Restrict explicit fault simulation to stemsl Backtracking inside FFRs(fanout free regions)l If no fault in an FFR propagates to its stem, the stem fault

need not be simulatedl If all faults in an FFR have been detected, the FFR is

dropped


Crithical PathCritical Path Tracing

l A line L has a critical value v in the test T iff T detects the fault L s-a-v

l A line with a critical value in T is said to be critical in T l A gate input is sensitive if complementing its value

changes the value of the gate outputl If only one input j has the controlling value (c) of the gate

then j is sensitivel If all inputs have c’ then all inputs are sensitive l Otherwise no input is sensitivel If a gate output is critical then its sensitive inputs, if any,

are also critical



l Let T be a test that activates fault f in a single outputcombinational circuit

l Let y be a line with level ly, sensitized to f by T l If every path sensitized to f either goes through y or does

not reach any line with level greater than ly, then y is a capture line (surrogate line) of f in the test T


Crithical PathSurrogate Lines

l The stem or PO at the output of an FFR :

the surrogate line of the FFR

A

B

C

D

E

F

f1

f2

f3

f4

f5

f6


Crithical PathFanout Free Regions

l Surrogate Lines : L, N, T, S, CO

CO

UT

N

T3

Y

X

L

L3

C1

X1

Y1

Q

RL2

Y2

X2

L1 T1

C11

N1

C12

N2

T2 V

S



l Surrogate Lines : L, N, T, S

UT

N

Y

X

L

C1

X1

Y1

Q

RL2

Y2

X2

L1 T1

C11

N1

C12

N2

T2

VS



l Surrogate Lines : L, CO

QL

Y

XC12

TN

R

L1

X2

Y1

X1

N1

Y2

L2

L3

T3

C1

CO


Crithical PathCriticality

l If test t detects a fault on l, line l is said to be critical in t

t

Pls POs

Xl


Crithical PathStem Criticality

l A line l is stem-critical in a test t, if t propagates a fault on l to its surrogate line

•Xl



l A gate i propagates fault effects iff§ either fault effects arrive only on sensitive inputs of i§ or fault effects arrive on all the nonsensitive inputs of I with

controlling value and only on these inputs

l Propagation through AND

111

• 1••

011

• 0 00

0

1


Crithical PathBacktrace

Determine Criticality & Stem-Criticality

l Example of backtracing in a fanout free circuit

1

1

11

1

1

0

1

0

00

1

0

0 0

1

B

A

C

0 ••

•

•

•

•

•

••

•

(a)

1

1

11

1

1

0

1

0

00

1

0

0 0

1

B

A

C

0 ••

•

•

•

•

•

••

•

(b)



Examples: Stem-Criticality

CO

UT

N

T3

Y

XL

L3

C1

X1

Y1

Q

RL2

Y2

X2

L1 T1

C11

N1

C12

N2

T2V

1

1

0

1

1

0

1

1 1

S

1

0

1



UT

N

Y

XL

C1

X1

Y1

Q

RL2

Y2

X2

L1 T1

C11

N1

C12

N2

T2V

1

1

0

1

1

0

1

1 1

S0

1



1

Q

L

Y

XC12

TN

R

L1

X2

Y1

X1

N1

Y2

L2

L3

T3

C1

CO

1

1

1

1

0

1

1

0



l A test T detects the fault f iff all the capture lines of f in T are critical in T

l It is sufficient to propagate the fault effects only to the first capture line of the stem fault

l Then the stem is critical iff the capture line is critical


Crithical PathCriticality of Surrogate Lines

• Critical Surrogate Lines: L, N, T, S, CO

CO

UT

N

T3

Y

XL

L3

C1

X1

Y1

Q

RL2

Y2

X2

L1 T1

C11

N1

C12

N2

T2V•

1

1

0

1

1

0•

1

•1 1

S •

1•

0

1



UT

N

Y

XL

C1

X1

Y1

Q

RL2

Y2

X2

L1 T1

C11

N1

C12

N2

T2V•

1

1

0

1

1

0•

1

•1 1

S •0

1

• Critical Surrogate Lines: L, N, T, S



1

Q

L

Y

XC12

TN

R

L1

X2

Y1

X1

N1

Y2

L2

L3

T3

C1

CO•1

1

1

1

0

1

1

0

• Critical Surrogate Lines: CO


Crithical PathCriticality and Stem Criticality

l A line l is critical in a test t, iff the line l is stem-critical and its stem is critical in the test t

t

Pls POs

xl


Crithical PathCriticality of Lines

CO

UT

N

T3

Y

XL

L3

C1

X1

Y1

Q

RL2

Y2

X2

L1 T1

C11

N1

C12

N2

T2V•

1

1

0

1

1

0•

1

•1 1

S •

1•

0

1



UT

N

Y

XL

C1

X1

Y1

Q

RL2

Y2

X2

L1 T1

C11

N1

C12

N2

T2V•

1

1

0

1

1

0•

1

•1 1

S •0

1



1

Q

L

Y

XC12

TN

R

L1

X2

Y1

X1

N1

Y2

L2

L3

T3

C1

CO•1

1

1

1

0

1

1

0



l Sometimes critical path tracing may not identify all the faults detected by a test

l This may occur in a test that propagates the effect of a fault on multiple paths that reconverge at a gate without sensitive inputs in T

l It is likely detected in other tests l Example§ Effects of J/0


Crithical PathTrace Based Algorithm

1. True Value Simulation2. Backtrace through FFRs (Identify stem-critical lines)3. Simulate stem faults (Identify critical stems)4. Backtrace through FFRs with critical stems (Identify

critical lines)

f4

f5

f6

f2

f3

f1A

B

C

D

E

F


Crithical PathParallel Pattern Trace Based

1. True Value Simulation2. Backtrace through FFRs (Identify stem-critical lines)3. Simulate stem faults (Identify critical stems)4. Backtrace through FFRs with critical stems (Identity

critical lines)

*All steps done in parallel pattern

f4

f5

f6

f2

f3

f1A

B

C

D

E

F



l Algorithm

for every primary output zstems_to_check = NULLextend(z)while stem_to_check != NULL

j = the highest level stem in stems_to_checkremove j from stems_to_checkif critical(j)

extend(j)end

end



l FFR§ stops at FFR inputs and collects all the stems reached in the set

stems_to_check

extend(j)mark j as criticalif j is fanout branch

add stem(j) to stems_to_checkelse

critical(j)for every input k of j

if sensitive(k)extend(k)



l Stem Analysis§ determine whether stem j is critical by a breadth-first propagation

critical(j)frontier = { fanout of j }repeat

k = lowest level gate in frontierremove k from frontierif frontier != NULL

if propagates(k)add fanouts of k to frontier

else critical(j)if propagates(k) and k is critical

return TRUEelse

return FALSE



l Directly identifies the fault detected by a test l Deals with faults only implicitlyl Based on a path tracing algorithml Approximate methodl Faster l Less memory


PROOFSPROOFS

l Only good for synchronous sequential circuitsl Use iterative array for synchronous sequential circuit

X(1)

Y(2)

Z(1)

Y(1)

X(2)

Z(2)

X(0)

Z(0)

Y(0) Y(n+1)

X(n)

Z(n)

Y(n)

X

Z

D

C.L.YY


PROOFSPROOFS

l Modified parallel fault simulation§ Fault-dropping is more effective than parallel fault simulation§ Parallel fault simulationÄFor (n-1) faults, continue through time frames until all faults are

detected or the max time frame is reachedÄF(i): Fault set of faults reaching y(i) but not yet detected

X(1)

Y(2)

Z(1)

Y(1)

X(2)

Z(2)

X(0)

Z(0)

Y(0) Y(n+1)

X(n)

Z(n)

Y(n)Fault

Set

F(0)

Fault

Set

F(n+1)


PROOFSPROOFS

l At the time frame i§ Perform the fault free simulation§ For every N faults in F(i)ÄPerform parallel fault simulationÄPut faults reaching y(i+1) but not reaching z(i) into F(i+1)

Y(i+1)

X(i)

Z(i)

Y(i)Fault

Set

F(i)

Fault

Set

F(i+1)C.L.


PARISPARIS

l All primary inputs belong to part Al A components with all predecessors in A is also in part Al All primary outputs belong to part Cl A component with all successors in C is also in part Cl All components not included in either A or C belong to

part B


PARISPARIS

l Simulate part Al Iterate simulation of part B until no more changes occurl Simulate part C


PARISPARIS


PARISPARIS

l A reasonable choice for the status words is to simply let them remain unchanged when a new step begins

l Advantages§ We spare the overhead to reinitialize all status words at the

beginning of each step§ The number of iterations is often greatly reduced because in

general the old status word is a better estimation of the resulting final word than the unknown word

l Inefficiency§ Unnecessary multiple evaluations of components during

simulation step


Fault SamplingFault Sampling

l Reduces the cost of fault simulation by simulating only a random sample of m<M faults

l Tradeoffs between the cost and accuracy§ M : number of faults§ K : number of faults detected by test sequence § Fault coverage F=K/M § m : number of sample faults§ k : number of sample faults detected by test sequence § Estimated fault coverage f=k/m § Determine m such that f belongs to the interval [F-emax, F+emax]

with a probability c



l Probability that T will detect k from m given that it detects K from M

§

l Hypergeometric mean and variance

l For large M, this distribution can be approximated by a normal distribution

−−

=

m

Mkm

KM

k

K

kMmpk

),,(

mFM

Km

K==µ

)1)(1(1

2

22

M

mFF

mmk

f−−== σσ

)1)(1(1

)1(2

Mm

FmFM

mMMK

MK

mK

−−=−−−=σ

Fm

K

f==

µµ



l Maximum error

l To reduce the cost significantly, l Then error becomes independent of M

l Provides an accurate estimate with low costl No information is available about the detection status of

faults not included in the samplel Difficult to improve fault coverage

Mm<<

3max

1)1)(1(

mM

mFFe −−=


Fault SamplingStatistical Fault Analysis

l STAFAN§ Low cost alternative to exact fault simulation§ Processes the results of fault free simulation to estimate its

probability of being detectedl Overall fault coverage is estimated based on the detection

probabilities of individual faultsl Consider T as a set of n independent random vectors§ Probability that a vector of T detects f is df

§ Probability that n vectors detects f is dnf = 1 - (1-df)n

§ Let F be the set of faults interest§ Expected number of faults detected by n vectors is Dn = ∑dn

f

§ Expected fault coverage is Dn/F


Fault SamplingSTAFAN

l Controllability and Observability§ C1(l) : probability that a vector sets l to value 1 § C0(l) : probability that a vector sets l to value 0§ B1(l) : probability that a vector propagates a fault effect from l to

PO§ B0(l) : probability that a vector propagates a fault effect from l to

POl Estimates after simulating vectors§ 0-count : number of 0s that occur during fault free simulation§ 1-count : number of 1s that occur during fault free simulation§ C0(l) = 0-count / n§ C1(l) = 1-count / n§ S(l) = sensitization-count / nÄ When a value is propagated to the gate output



l m = AND(i, j, k, l)§ C1(m) = Prob(i=1, j=1, k=1, l=1)

= Prob(i=1, j=1, k=1 | l=1) C1(l)§ Prob(i=1, j=1, k=1 | l=1) = C1(m)/C1(l)§ B1(l) = B1(m) Prob(i=1, j=1, k=1 | l=1)

= B1(m) C1(m) / C1(l)§ S(l) = Prob(i=1, j=1, k=1 )

= Prob(i=1, j=1, k=1, l=1 ) + Prob(i=1, j=1, k=1, l=0)= C1(m) + Prob(i=1, j=1, k=1 | l=0)C0(l)

§ Prob(i=1, j=1, k=1 | l=0 ) = ( S(l) - C1(m) ) / CO(l)§ B0(l) = BO(m) Prob(i=1, j=1, k=1 | l=0)

= BO(m) ( S(l) - C1(m) ) / CO(l)



l OR gate§ B1(l) = B1(m) (S(l) - C0(m))/C1(l)§ B0(l) = B0(m) C0(m) / C0(l)

l NAND gate§ B1(l) = B0(m) C0(m) / C1(l)§ B0(l) = B1(m) (S(l) - C1(m))/C0(l)

l NOR gate§ B1(l) = B0(m) (S(l) - C1(m))/C1(l)§ B0(l) = B1(m) C1(m) / C0(l)

l NOT gate§ B1(l) = B0(m) § B0(l) = B1(m)



l Stem and Reconvergent Fanout§ Let s be a stem and i, j be fanout branches§ B1(s) ≥ B1(i) and B1(s) ≥ B1(j) or B1(s) ≥ max[B1(i), B1(j)]§ If paths through i and j are independentÄB1(s) = B1(i) ∪ B1(j) = B1(i)+B1(j)-B1(i)B1(j)ÄUpperbound

§ max[B1(i), B1(j)] ≤ B1(s) ≤ B1(i) ∪ B1(j)Ämax[B1(i), B1(j)] depends on circuit topology

§ Let s be a stem and 1, ... , k be fanout branches§ max [B1(1), ... , B1(k)] ≤ B1(s) ≤ P( ∪k

i=1 B1(i))§ B1(s) = (1-a) max [B1(1), ... , B1(k)] + a (∪k

i=1 B1(i))Ä a is an arbitrary constant in the range of [0,1]



l s stuck at 1§ D1(l) = Prob( s set to 0 and observed )

= Prob( s set to 0 ) Prob( s is observed | s is 0 )= B0(s) C0(s)

l s stuck at 0§ D0(s) = B1(s) C1(s)

l Same computation rules for sequential circuits§ Results in more approximation

l Faults are grouped in 3 ranges§ Faults in a high range is regarded as detected § Faults in a low range is regarded as undetected § No prediction for faults in a middle range



l STAFAN requires§ 0-count and 1-count of every gate output and sensitization count

of every gate input must be updated in every vector§ Controllabilities, Observabilities, and detection probabilities are

computed after simulating a group of n vectors§ Since n is large, first operation dominates the complexity


Fault SamplingSwitch Level Fault Simulation

l Complexity§ Logic values : 0, 1, X, Z§ Signal strength : Strong, Weak, Charge§ Wired device§ Precharge switch



l Precharge§ f=0 : precharge§ f=1 : inverter

prechargetransistor

evaluatetransistor

OUT

IN

VSS

VDD

f

OUTprecharged to 1

evaluation

precharge

f



l Precharge§ To simulate the precharge switch, the precharge node and its logic

values are known§ Put 0 to the precharge clock and all PIs to XÄDecide the output to 1

VDD

OUT = ( 1, CHANGE )

VSS

0 X

Z Z

1



l IN=0 and f=1§ Faulty : N2=0§ Faulty : N2=Z

OUT

IN

VSS

VDD

f

s-a-1

P1

N2

N1

P1 = Z

N2 = 0/Z

OUT = 0/Z -> 0/1


Fault SamplingHierarchical Fault Simulation

l Use Hardware

fault simulation - yonsei

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