fault current limiter gurjeet singh malhi master of engineering (me) massey university, new zealand

Fault Current Limiter

Gurjeet Singh MalhiMaster of Engineering (ME)

Massey University, New Zealand

Outline of Presentation

• Introduction• Operation of Fault Current Limiter (FCL)• Experimental Results• Flux distribution & Thermal Model of FCL• High Temperature Superconductor(HTS) FCL

in Power System.• Optimum Location of HTSFCL• Conclusion

Introduction• Electronic & Electrical devices have wide applications in

Industry

• Electronic & Electrical circuits are sensitive

• Most important concern about an device is its safe mode of operation

• Protection from fault or short circuit is needed

.........contd

• Consequences of faulty operation1. Can permanently damage the device, which need to

be replaced

2. Need to change the circuit configuration

3. Effects the integrity of system

And the Solution ?

• To limit fault current using Fault current limiter (FCL)

Introduction

Current Limiter Approaches• Resonant Circuit Limiters

• Switched Devices

Tuned impedance Current Limiter (fig.1)

• In line fuse devices

• Superconducting devices

Silver Sand fuse FCL (fig.2)

...contd Superconducting Devices

Fig(3)Fig(4)

Fig(5)

Fault Current Limiter

Based on

Passive Devices

Basic structure of FCL

• Consists of two cores

• Permanent Magnet

• Ferrite is used as

core material

Operating Principle of FCL• Under Normal Operation

1. Both cores operate in saturation

2. Low effective impedance of system

3. Low voltage drop

• The direction of current and MMF in cores

Operating Principle of FCL

• During fault operation

1. Cores comes out of saturation in alternative half cycle

2. Effective Impedance of the system increases

3. Limits the fault currentBelow Ilinek ： Low impedance →Small voltage drop

Over Ilinek ： High Impedance → Large Voltage Drop → Current Limit

- I Characteristics of FCL

Design Parameter of FCL

maxc mH l NI

To avoid loss of current limiting action and demagnetization of PM

Where Hc is coercive force of PMlm is length of PMIMax is maximum current allowed during faultUnder normal operation the voltage drop across the FCL is given by

•The voltage across the FCL during fault is given by

2(2 ) 4NOR s s sV X I fL I fL I

Contd..2 ( )FAULT u s uV X I f L L I

Design Parameter of FCL• Ratio of normal drop to supply voltage is given by.

• k = Ifault/Inor

1801u

s rs

L

L

10 15 20 25 30 35 40 45 504

6

8

10

12

14

16

18

20

Saturated permeability (relative)

Lu/L

s

For higher value of Lu/Ls, low value ofSaturated permeability, rs

System voltage up to 600v and current up to few hundreds of amperes.

supply

21 1 2 1

1

NOR s NOR s s

uu FAULT u s u

s

V X I X LLV X I k X k L L kL

Fabricated FCL

Experimental Results

Circuit with FCL

Under shorted diode condition

Output at load under shorted condition.

Flux distribution of FCL using Finite element modelling

FEMLAB model of FCL with no current

Model of FCL with low current corresponding to positive half of the cycle

Contd..


Model of FCL with large current corresponding to positive half of the cycle

Model of FCL with low current corresponding to negative half of the cycle

Contd..


FCL with high negative current

FEM. Model of FCL during Fault

Thermal Model of FCL

Variation of Temperature with Time (Transient)

Variation of temperature with current (Steady State)

280

290

300

310

320

330

340

350

0 20 40 60 80 100Current(A)

Tem

pera

ture

(K)

Feature of FCL

• Easy to design as its a simple structure• Passive device current limiter for AC

usage using Inductive Method• Relatively low cost as it composes of

core, magnet and winding• Maintenance free as its a simple

structure• Quick recovery time due to the usage of

magnetic characteristics only

High Temperature Superconductor FCL In Power System

• Depends on T, B and J

• Jc critical Current density

• Tc critical temperature

• Normal operation

• J < Jc, T < Tc

• Fault

• J > Jc, T >Tc

• Regime 1

E (j,T) = Ec*( j / jc(T))^(T)

where (T) = max[ , ’(T) ], with ’(T) = log( Eo/Ec) / log[( jc (77K) / jc

(T))^(1-1/)* ( Eo / Ec)^1/(77K)]

• Regime 2

• E (j,T) = Eo*( Ec/Eo)^ /(77K)*jc(77K)/jc(T)*( j / jc(77K))^

• Regime 3

• E (j,T) = p(Tc)*T/Tc*j

Superconductor used for HTSFCL

• Bi2223

• YBCO

Layout of HTSFCL

V =11KV

I = 1KA

Results Normal Under Fault

Results

Time vs Resistance

Results with different lengths of HTSFCL

• Length =12m

Results

• Length=14m

Modelling In PSAT

Normal OperationPower at Buses

Bus2_P

• BusP_3• BusQ_4

0 1 2 3 4 51.63

1.63

1.63

1.63

1.63

1.63

1.63

1.63

1.63

1.63

time (s)

0 1 2 3 4 50.85

0.85

0.85

0.85

0.85

0.85

time (s)

0 1 2 3 4 50.0647

0.0647

0.0647

0.0647

0.0647

0.0647

0.0647

0.0647

0.0647

0.0647

time (s)

Normal OperationPower flow• P7-P8

P5-P7

• P2-P7

• Q7-Q80 1 2 3 4 50.8863

0.8863

0.8863

0.8863

0.8863

0.8863

0.8863

time (s)

0 1 2 3 4 5-0.727

-0.727

-0.727

-0.727

-0.727

-0.727

-0.727

-0.727

-0.727

-0.727

-0.727

time (s)

0 1 2 3 4 51.63

1.63

1.63

1.63

1.63

1.63

1.63

1.63

1.63

1.63

time (s)

0 1 2 3 4 50.0286

0.0286

0.0286

0.0286

0.0286

0.0286

0.0286

0.0286

0.0286

time (s)

Q7-Q5

0 1 2 3 4 5-0.2287

-0.2287

-0.2287

-0.2287

-0.2287

-0.2287

-0.2287

-0.2287

time (s)

Q7-Q2

0 1 2 3 4 50.2001

0.2001

0.2001

0.2001

0.2001

0.2001

0.2001

time (s)

During Fault» BusP_1 • BusP_3

• BusP_2 • BusQ_4

0 2 4 6 8 100.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

time (s)

0 2 4 6 8 10

0.8

1

1.2

1.4

1.6

1.8

2

2.2

time (s)

0 2 4 6 8 100.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

time (s)

0 2 4 6 8 10-0.5

0

0.5

1

1.5

2

2.5

time (s)

During fault• P_5,7,8 Q_5,7,8

0 1 2 3 4 5 6 7 8 9 10-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0

0 1 2 3 4 5 6 7 8 9 100

0.2

0.4

0.6

0.8

1

1.2

1.4

Investigating the Optimum location of HTSFCL

• Current During Fault at different Buses

00.5

11.5

22.5

33.5

44.5

0.75 1

1.25 1.5

1.75 2

2.25 2.5

2.75 3

3.25 3.5

3.75 4

Cu

rren

t(p

u)

Time(s)

Current at Different Buses

Bus1

Bus2

Bus3

Bus4

Bus5

Bus7

Bus8


Increase in impedance

0

0.5

1

1.5

2

2.5

0.5…

0.8…

1.0…

1.3…

1.5…

1.8…

2.0…

2.3…

2.5…

2.8…

3.0…

3.3…

3.5…

3.8…

Currentat different buses

Bus1

Bus2

Bus5

bus7

Bus8

Bus4

Conclusions• Circuit analysis of FCL was performed using the magnetic circuit

method

• Flux distribution of FCL has been analyzed in FEMLAB

• Expected current limit characteristics were obtained experimentally

• Thermal model of the FCL is obtained and analyzed

• Experimental results are close to the ideal characteristics.

Future work• Performance improvement and optimum design procedure.

• Application to high voltage system in NZ.

Thank you

fault current limiter gurjeet singh malhi master of engineering (me) massey university, new zealand

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