Fast & Furious: Taming the Challenges of Advanced-Node Design

Anirudh Devgan, Senior Vice President, Digital & Signoff Group

2 © 2013 Anirudh Devgan. All rights reserved.

By 2020 there will be over 10 billion mobile internet devices, and the core of each is a specialized semiconductor- Tablets- Smartphones- MP3 players- Gaming devices- Car electronics- Mobile video- Home entertainment- Wireless appliances

Source: Morgan Stanley

SemiconductorsAt the heart of the next technology wave

Chassis

Gateways

Powertrain

Instruments

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• Low power important across markets – from smartphones to datacenters

• Time to market remains critical

• Feature-rich devices growing design size– Average number of

IP blocks per design*– 65nm: 48 IP Blocks– 45/40nm: 73 IP Blocks– 32/28nm 97 IP Blocks

* Source: IBS

Design Complexity is Increasing

Complexity is growing exponentially – and signoff is the bottleneck

Complexity = design size ● # views ● power ● performance ● time-to-market

Mobile Computing

Cloud/

DatacentersConnectivity

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• Over 50% of first tape outs in a new process slip the schedule

• What’s major cause?

Customers Have Real ChallengesHow to avoid schedule delays

Timing Closure

Multi-Corner

Multi-Mode

RC Extraction

Signal Integrity

OCV

LDE

Multi Voltage

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Challenges in Signoff and Design Closure

• More Timing Modes And Corners

• Multiple Clock Domains

• More Electrical Design Rules

• Timing Variation Modeling

• More Power Domains

• More Extraction Corners

• New Device Types

• More Voltage Domains

• Lower VDD

Electrical Design Challenges

Analog Effects

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Challenges in Signoff and Design Closure

• More Parasitic Devices

• More Physical Design Rules

• More Complex PV Design Rules

• Layout Dependent Effects

• Multi-patterning

• New Device Types

• Device Variation

• More Complex Litho / OPC Rules

• More Time Spent In Signoff & Design Closure At Advanced Nodes

Physical Design Challenges

CMP

Litho

3D Devices

7 © 2013 Anirudh Devgan. All rights reserved.

What is the solution ?

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Cadence Silicon Signoff & Verification SolutionsBringing Innovation To Signoff

Better Solvers For Better Scalable Performance

Productivity Through Integration with Fast Accurate Built-Engines

Improved Accuracy – Both For Tools And Models

9 © 2013 Anirudh Devgan. All rights reserved.

SSV Technology Pillars

SSV Signoff Key Priorities

• Efficient Scalability With Multiple CPU’s and Machines

Performance

• “In-Design” Integration – Critical for both analog & digital below 28nm

Integration with Implementation

• Significantly faster timing, power Closure, not just analysis• Improved Multi-Mode/Corner Solvers

Productivity with built-in Design Closure

• New Solvers with Improved Accuracy Algorithms• Higher Accuracy Engines Needed For 20nm and Below

Accuracy

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Tempus Timing Signoff Solution New technology accelerates timing analysis and closure by weeks

Introduced: May 2013

TSMC certifies Tempus Timing Signoff Solution

Endorsed by Texas Instruments for advanced giga-scale, giga-performance ICs

PerformanceMassively parallelized

Scalable to 100s of CPUs

Up to 10X speed up over competition

Accuracy10X faster path-based analysis

Advanced process modeling

Closure10X reduction in closure time

Unlimited MMMC capacity

Incremental Design Closure

11 © 2013 Anirudh Devgan. All rights reserved.

Voltus IC Power Integrity SolutionMassively parallel execution delivers high performance for up to one billion instances

“IDT produces industry-leading products across a wide range of nodes and applications, and we were pleased to see the Voltus technology delivers up to a 10X performance improvement across various test cases ranging from 180nm to 28nm designs.”

- Alan Coady, senior director, IDT

“We are teaming early on with Cadence to validate the Voltus technology and we are impressed by its performance gains. This type of enhanced productivity is invaluable to help us meet our time-to-market goals.”

- Ken Hansen, vice president and chief technology officer at Freescale Semiconductor

Introduced: Nov. 2013

Voltus™: Breakthrough technology in power integrity analysis and signoff

Up to 10X faster performance over existing solutions

Certified for TSMC 16nm FinFET process

Integrated with key Cadence technology for fast design signoff and closure

12 © 2013 Anirudh Devgan. All rights reserved.

Voltus: Tilera Press Release – 11/19/2013

Without any loss of accuracy, Tilera cut power signoff runtime for this highly integrated 72 core system-on-a-chip design from 65 hours to 8 hours for dynamic analysis and from 12 hours to 2.5 hours for static analysis.

achieved an 8X run-time performance improvement for power signoff of its largest design to date, the TILE-Gx72 processor

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Key Differentiation

Tempus•Up To10x Speed Up•Massively Parallel Execution•Signoff ECO

Voltus / VPS•Up To 10X Speed Up•Massively Parallel Execution•In-design Productivity

QRC•QRC 2X-3X Performance Gain•QRC-Field Solver ~25X Average Speed Up•In-design Productivity

PVS / IPVS•2X Soc DRC Speed Up•In-design Productivity

DFM•2X Better Performance Over Competing Products•In-design Productivity•Strong Advanced Node Foundry Support

SSV Current Product Performance Status

Significant Increase In Productivity

14 © 2013 Anirudh Devgan. All rights reserved.

Cadence Silicon Signoff & Verification SolutionsBringing Innovation To Signoff

• Establish Cadence as a technology leader in signoff

• Develop Best-in-class products

Our Goal:

Enable faster design tape-outs by reducing time spent in design closure and signoff by fixing problems, not just analyzing them

15 © 2013 Anirudh Devgan. All rights reserved.