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Fast Communication Fast Communication for Multi – Core SOPC for Multi – Core SOPC

Technion – Israel Institute of TechnologyDepartment of Electrical EngineeringHigh Speed Digital Systems Lab

Supervisor: Evgeny Fiksman Performed by:Moshe BinoAlex Tikh

Spring 2007

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Table of ContentsTable of ContentsGeneral p.3

Project goals p.4

Software p.5

Hardware p.6-8

Block diagram p.9

Test & debug p.10-11

Time table p.12-14

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GeneralGeneral

• Programmable hardware chips present a wide base for developing SOPC systems.

• SOPC systems include generic soft-core processor called Microblaze and basic programmable elements.

• MPI – Message Passing Interface enable working with fast communication.

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• Implementation of mini distributed core system using MPI router .

• Build an infrastructure for fast communication in multi-core system.

• Build a designated C/C++ application to show the advantages of working with parallel system.

Project goalsProject goals

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SoftwareSoftware

• Embedded Development Kit (EDK) is a suite of tools and IP* that enables to design a complete embedded processor system.

• Integrated Software Environment (ISE) - software development tools that allow to circumvent some of designing complexity.

Development environmentDevelopment environment

* IP = Intellectual property

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HardwareHardware

• The Virtex-II Pro FPGA contain platform for designs that are based on IP cores and customized modules.

• The MicroBlaze core is a 32-bit RISC* Harvard architecture soft processor core with 32 general purpose registers, ALU, and a rich instruction set optimized for embedded applications.

Development environmentDevelopment environment

*RISC = Register Instruction Set Computer

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HardwareHardware

• The top design will include 4 MicroBlaze processors connected by direct point to point Fast Simplex Links (FSLs) for interprocessor communication.

• FSL Bus is a uni-directional point-to-point communication channel bus used to perform fast communication between any two design elements on the FPGA when implementing an interface to the FSL bus.

ConfigurationConfiguration

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HardwareHardwareKit used – XUP Virtex - II Pro BoardKit used – XUP Virtex - II Pro Board

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Block diagramBlock diagram

#3

#1

#4#2

MEMORY

FSL BUS FSL BUS

FSL

BU

SFS

L B

US

MPIROUTER

OP

B B

US

OP

B B

US

MEMORY

I/O

MEMORY

OPB BUS

MEMORY

OP

B B

US

· OPB – On Chip Peripheral Bus· FSL – Fast Simplex Link

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Test & DebbugTest & Debbug

• ModelSim is a simulation and debug environment, combining high performance with powerful and intuitive GUI.

Unit testUnit test

• ChipScope Pro inserts logic analyzer, bus analyzer, and Virtual I/O low-profile software cores directly into your design, allowing to view any internal signal or node, including embedded hard or soft processors.

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Test & DebugTest & Debug

Chip scope pro system block diagramChip scope pro system block diagram

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• Run a test application - create small application and look for expected results. If expectations are not met, debug with Xilinx Microprocessor Debugger tool (XMD) which is a software debugger for a multi-processor system.

System testSystem test

Test & DebbugTest & Debbug

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Time TableTime Table – – Mid TermMid Term

Studying EDK environment.

1 Week ~ 6.5.07

Studying FSL interface. 1 Week ~ 13.5.07

Define Simple MPI / MPP 1 Week ~ 20.5.07

Build a dual core system (without FSL connectivity)

1 Week ~ 27.5.07

High level design 1 Week ~ 3.6.07

Midterm presentation tentative

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Time TableTime Table – – first semesterfirst semester

Continue design to low level

3 Week

Implementing FSL connectivity

2 Week

Preparing report 2 Week

End semester presentation 1 Week

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Time TableTime Table – – second semestersecond semester

• Build a quad core system

• Implementing router for 4 processors

• Test and debug

• Run a test application

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QUESTIONS ?