IRE TRANSACTIONS-ELECTRONIC COMPUTERS 133

Fast Carry Logic for Digital Computers*BRUCE GILCHRISTt, J. H. POMERENEt, A:ND S. Y. WONG$

Summary-Existing large scale binary computers typically must cally provided by a separate timing device such as aallow for the maximum full length carry time in each addition. It has multivibrator. The actual time provided must be NCbeen shown that average carry sequences are significantly shorterthan this maximum, on the average only five stages for a 40 digit ad- plus a safety margin to allow for tolerances in both thedition. A method is described to realize the implied 8 to 1 time sav- carry circuit and the timing device.ing by deriving an actual "carry completion" signal. Experimental In practice this safety margin may be an appreciableresults verify this saving. fraction of NC. Every designer of an asynchronous

machine has probably considered using the carry circuitINTRODUCTION to time its own full length carry time NC. One such

ANEED HAS been shown' for significantly higher method is given by Richards' and a similar method iscomputational speeds than are afforded by also embodied in the logic to be described. These meth-existing machines. Although the term speed as ods certainly increase the timing reliability of the carry

here used should perhaps be viewed in the most general system and also save above mentioned safety margin.sense, that is, a speedup of the whole process inter- A more significant speedup can be made if time isvening between the statement of a problem and its allowed only for the actual carries arising in the par-final solution, at least some speedup should be expected ticular additions. In an early discussion of the logicalto come from a decrease in the execution time of the design of a computer,4 it was shown that on the averageelementary machine operations, combinations of which the maximum length of a l's carry sequence in a 40form the basic arithmetic and logical processes. The digit addition is only 4.6 stages. If fully exploited, thiscarry process arising in the parallel addition of numbers, result could lead to an 8-fold saving in average carrywhich is essentially serial, is one such elementary opera- time. Such a saving, resulting from logic alone, has thetion. A method is given for significantly decreasing the important property of being additional to that resultingtime required for the carry process by using the average from faster components. The logic to be described givesproperties of carry sequences. Such a method is of par- almost this 8-fold saving. It differs from the optimumticular interest not just for the addition operation itself, because carry sequences of 0's as well as l's must bebut also for the possibility of speeding up the ordinary considered and in this case the average maximum carryrepeated addition type of multiplication. It would be sequence is shown to be 5.6 stages.of great value if this simple type of multiplication couldbe performed in a time comparable with simultaneous Ci. A Bmultiplication, which is potentially fast, but costly in -

0 1

eqimet2 0 0 1 0equipment.' O 1 0 0 carry out is determinedWe distinguish the carry propagation, which is serial, 1 0 1 1 by carry in

from the formation of the sum digit, which is parallel, 1 1 0 1given the carries. Thus assuming the addends to be 0 0 0 0applied simultaneously to the N parallel stages of the 00 0 0 carry out is determinedo i 1 1 solely by the addendsadder at time to, we observe the carry into the most 1 I 1 1 A, Bsignificant stage of the adder and call the time ti when .

it recognizably assumes its final value. We define theN stage carry time to be NC =t- to when the carry Fig. 1 shows the truth table for determining the out-arises at the least significant stage and progressesthrough to the most significant. At least a majority of put carry, o t, for one stage of a bnary adder, theexisting machines employ carry circuits in which the ifull length carry time NC must necessarily be allowed input carry C.. The eight input combinations are

divided into two groups of four each, according toin eac-h addition. The required time allowance iS tVDI- V t-Iin achaddtio.Te rquied imeallwane i tyi-whether or not the output carry can be stated inde-

* Original manuscript received by the PGEC, July 6, 1955. The pendently of the input carry. We establish our nomen-research reported in this paper was supported jointly by the Army, clature by considering first the simple carry determina-Navy, Air Force, and AEC under contract No. DA-36-034-ORD-1646, .. .-Project TB3-0538 with the Institute for Advanced Study. 'tion logic given in Fig. 2. Here the symbol (00) means

t Institute forAdvanced Study, Princeton, N. 1. that Aand Bare not both zero, while (11)means thatt Formerly with the Institute for Advanced Study, now with the bt n r n'.C niae ar foe

Philco Corp., Philadelphia, Pa.bohAadBaeoes iictsaaryfor.1 The numerical weather prediction problem is an example of this;

e.g., B. Gilchrist, "Computers and weather prediction," Cornp. & R. K. Richards, op cit.Autom., vol. 4, pp. 8, 9; March, 1955. 4A. W9. Burks, H. H. Goldstine, and J. von Neumann, Prelimi-

2 R. K. Richards, "Arithmetic Operations in Digital Computers," nary discussion of the logical design of avn electronic computing in-D. Van Nostrand & Co., New York, pp. 138-140; 1955. strument, 1947.

134 IRE TRANSACTIONS-ELECTRONIC COMPUTERS December

00 11I I o o o I o 1 1-' 1 o

C AND O IInou

Fig. 2-Simple carry logic.

This simple carry circuit is incapable of providing itsown timing because of the carry initerruptions (caused -by 00) anid carry starts (caused by It) which may occur I ovariously throughout the N stages. A symmetricalmrctreatment involving also 0 carries (C°) as in Fig. 3 Fig. 4-Carry sequiences in ten conisecutive adder stages with ad-results in a circuit which can provide its own timing. dends A and B. Upper sequence is for logic of Fig. 3 and lowerEssentially a separate carry chain is provided for the sequence is for logic of Fig. 5.

l's and for the 0's. The state of the carry lines shouldn1ow be viewed as "off" or "onie" for C1 and "off" or carry, while in the latter four cases the output carry is"zero" for CO. At the beginining of an addition, both indepeniden-t of the inlput. This result is used in thecarry lines are "off." This coniditioni will be met if both logic shown in Fig. 5. The dual carry chains of thecarry inputs to the least significanit stage are held "off." previous circuit have been retained but the Ci,. restric-

tions on (11) and (00), that is, the cross connections,670 have beeni deleted. AIn N input "and" gate has been

added to signial the presence of a carry (1 or 0) at eachA D iOR- of the 40 stages. As before, both carry linies are off at

the start of an addition, this beinig eniforced for theoo ) iinterior stages by an explicit parallel inhibitioni on the

linies or by operating on the 11 and 00 inlputs. Carriesare begun by releasinig the inhibitionis on all stages,including the selected carry inlto the least significanltstage. At this moment carry sequenices will arise fromthe selected iniput carry, and from every interior stagehaving (00) or (11). Thus the serial aspect of the carryis restricted to sequenices of stages for which A sB.

---C. AN OR ---Gin °n 1 Goutstage a" state-2 1 Stte*2"

I oo 11 oo 11 1 0o

Fig. .3-Logic for self-timiniiig full lenigth carry . A O A O A O

The carry sequence is begun by settinig one of theseinputs, say CO, to the "on" state. This carry will then C,,A Cttproceed down the "0" chain until it reaches a stage 00 00having (11), where the carry switches over to the "1" C C achain. Similarly, it will then proceed down the 1 chain (40 inpetAnd'gate) Sign|aluntil it reaches a stage having (00), where it will switchback to the zero chain. Finally it will emerge from themost significant stage as either a C0 or a C' to signal theend of the N stage carry. This zig-zag process is indi- The lower half of Fig. 4 shows the carry chainis re-cated schematically in the upper part of Fig. 4 which sultinig for this final circuit using the same addends astraces the carry chains through ten stages of an adder previously. Six carry sequences are started simultanie-with the given addends A and B. It should be empha- ously as marked by the asterisks. Sinice for these markedsized that the carry will always pass serially through stages the input carry is irrelevant to the output carry,ten stages although the route will be determinled by the inlcominlg carry sequences stop at the stage just prior.addends. Now it is seen that for this example the longest carry

sequence is three stages instead of the full ten. For theTHE LOGICAL CIRCUIT more practical case of 40 digit numbers, it is shown be-

A re-examination of Fig. 1 in the light of this circuit low that the average longest carry sequence will be 5.6leads to the logic for deriving a completion signal for stages. Thus after anl average time delay of only 5.6the actual carries. The first four cases are seen to be the C each of the 40 inputs to the carry completion gate willones for which the output carry depenlds on the input be enabled, signalling the end of the carry process.

1955 Gilchrist, Pomerene and Wong: Fast Carry Logic for Digital Computers 135

000\

0.25

0.27'

0.15

% 50o0.I

0.05

0 5 10 IS 20 25 30 35 40

Imaw

Fig. 6-Probability distribution of the maxinml In lenigth carry se- 0 5 0 5 20 25 3035 44quence (nfma,c) arising in a forty digit addition.

Fig. 7-Percentage of additions having a maximumlength carry sequence greater than n.

PROPERTIES OF CARRY SEQUENCESThe analytic approach of Burks et al5 to the problem too 411

of determining the properties of l's carry sequences is *unable to give more than the value of the average maxi- -Ilmum carry sequence and gives no information as to the invariance of this maximum carry. Thus, while in princi-ple we could have extended this analytic approach toinclude the present case of both 0 and l's carry se-quences, it was decided to obtain the results by actualnumerical experiment so as to gain some knowledgeas to the variance. EsA code was therefore written for the IAS computer A

to examine the properties of carry sequences. This codegenerates pairs of random 40 digit numbers and adds completion busthem digit by digit to obtain for each pair of numbers +the maximum carry sequence (n max) of l's or O's aris-ing. The distribution of n max found from 4,000 random Eadditions is shown in Fig. 6. The distribution was un-changed by increasing the sample size. From theseresults the average maximum carry length, defined as CoEnmax P(nmax). nmax was found to be 5.6. It is of inter- outest to note the small deviation of the individual maxi- inmum carry length from this average. This is broughtout by Fig. 7 which shows the percentage of additionswhich have a maximum carry sequence greater than n. *

It seemed desirable also to check the carry sequence tooproperties of the interior additions involved in the *Eaale carrvoturn-offAlArsoala arya eddsimple~~~~~~~~~~~~~~ -5tpictovolts.sTubesneA&A'erretUsriinaryasneddsimplemultipicatio proces mentoned erlier.UsingFig. 8-Per-stage carry circuit of experimental adder.a similar code to that for examining addition it wasfound that the average maximumn carry length wasagain 5.6. Thus inl a typical multiplication of two forty- EPRMNA EUTdigit numbers the average sum of the individual maxi- An1 eight stage experimental accumulator was con-mum carries will be 20X5.6-=112. structed embodying the carry logic described above.

The per-stage circuit for the carry portion is shown in6 A. W. Burks, H. H. Goldstine, and J. von Neumann, loc. cit. Fig. 8. It should be noted that the circuits providing

136 IRE TRANSACTIONS-ELECTRONIC COMPUTERS December

the digit inputs to the carry circuit, and those forming quences of lengths 0, 2, 4, 6, and 8, respectively, com-the new sum from it, were connected in order to present pletion being represente(l by a negative going signal.the loads which woould obtain in actual use. Fig. 9 shows We define the moment of completion as the time at

which the signal passes below -5 volts. Of particuilarinterest are the times re(quired for the carries of length4 and 6, which are 0.18 jis andl 0.22 us, respectively.Hence the average carry time per addition will lie be-tween 0.18 ancl 0.22 us, or approximately 0.21 1us.

CONCLUSIONSA method has been shown for accomplishing the

carries of a 40 digit adldition in an average time of0.21 )us by using a self-timed carry logic. Preliminaryresults indicate that the remaininig essentially parallelportion of the adldition can be performed in about 0.15us. If this figure can be maintained, the average totaltime, exclusive of memory access, required for an addi-

Fig. 9---Completion signals for several carry lengths in tion coulcl be 0.36 As andl that for a multiplication couildeight stage experimental adder. be 40X0.15+20X0.21 = 10.2 us. The carry circuit used

requires more componenits than carry circuits generallythe response of this circuit to carry seqluenices of several used, but the significant increase in speed offsets the(lifferent lengths. In each case carries were started by iicreased complexity. In addition, the inclusioni of theenablinig the carry lines and( the carry input CO to the 40 stage "and" gate permits a carry-less determiniationileast significanit stage and observations were made at of the equality of two addends, this mode being obtainedthe outpult of the 8 input "and" gate. The leftmost by not releasing the parallel carry inhibitions showni incurve shows the carry start signal and successive curves Fig. 8. In this case an output is obtained from carry coin-to the right show the completion signals for carry se- pletion gate if, ald only if, two addends are eqIual.

Bit Storage via Electro-optical Feedback*ALFRED MILCHt

Summary-An electro-optical binary storage device has been veniently transferred from one place to another. Pho-built which consists of a vacuum diode containing a photocathode tonls enijoy the same advantage and, in some ways, areand a phosphoranode. The device is capable of storing both optical . ' . .and electrical information pulses. The present paper comprises a de- easier to transport than electrons. In addition, an opticalscription of the behavior and construction of the prototype diode, an iniformationi pulse may readily be converted to an elec-empirical derivation of a criterion for the conditions of stable feed- trical informationi pulse, and vice versa. 'I'here is thusback, and a numerical calculation for the case of two electrode pairs. the possibility that optical and( electrical informationBriefly mentioned are the possibility of high speed storage of digital pulses, used cooperatively, mav lead to importanitinformation, the problem of self-triggering, the applicability of thecriterion to solid state devices, and the analogous bistable behavior advances in digital data processing. One way in whichof a radio frequency triggered neon diode. this may be done would be to incorporate a photosensi-

tive cathode and a cathodolumiiiescent anode in a singleINTRODUCTION vacuum envelope. 'I'his idea is of rather recenit concep-

T11 XHE FACT which makes contemporary high speed tion, and to this writer's knowledge, it originated as andigital computinig machinies possible is that elec- "image tranisformer"l in 1934. Its contemporary de-trons are low-iniertia entities which may be con- scelndeit, the image converter tube, is finding wide

* Original manuiiscript received by the l'GEC, May 4, 1955; re-application as an electro-optical transducer.vised manuscript received July 14, 1955. 'Multiple Fellowship onComputer Components sustained by the Electronics Directorate ofthe USAF, Cambridge Res. Center, Res. D)ept. Command, tinder G. Hoist, J. H. D)eBoer, im. C. Teves, and C. F. \'enemaiis,Contract AF 19/604/-943. "I'ransformation of light of Iong wavelength into light of short wave-

f Mellon Instituite, Pittsburgh, Pa. length," Physica, vol. 1, pp. 297-305; 1934.