fall 2006 1 ee 333 lillevik 333f06-l14 university of portland school of engineering computer...
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Fall 2006
Lillevik 333f06-l14 1University of Portland School of Engineering
EE 333
Computer OrganizationLecture 14
Memory hierarchy, locality
Memory design
Fall 2006
Lillevik 333f06-l14 2University of Portland School of Engineering
EE 333
Correction: machine instructionInstruction Type Op rs rt rd immed
/adrfunct Machine
(hex)add $0, $0, $1 R 0x1 0 1 0 na 0x0 0x1400
andi $0, $1, 10f I 0xc 0 1 na 0x10f na 0xa90f
sll $0, $1 I 0x2 0 1 na na na 0x2400
lw $0, 323 ($1) I 0x4 1 0 na 0x323 na 0x4b23
beq $0, $1, 17a I 0x6 0 1 na 0x17a na 0x657a
j a64 J 0x7 na na na 0xa64 na 0x7a64
Correction
Fall 2006
Lillevik 333f06-l14 3University of Portland School of Engineering
EE 333
Any questions on Project 4?
• Two, 16-bit registers ($0, $1)
• Two read ports
• One write port
• Equal output
• Due: Nov. 3
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Lillevik 333f06-l14 4University of Portland School of Engineering
EE 333
Major computer components
Five classic computer components
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Lillevik 333f06-l14 5University of Portland School of Engineering
EE 333
Computer components
• Input: receives information from external world
• Output: transmits information to external world
• Memory: holds programs and data
• Data path: physical route that carries info
• Control: coordinates overall flow of info
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Lillevik 333f06-l14 6University of Portland School of Engineering
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Memory design goals
• Unlimited memory size– No upper bound on memory addresses– Not practical or possible: cost, implementation
• Infinite memory bandwidth– Zero latency memory accesses– Not practical or possible: cost, laws of physics
• Memory hierarchy can approximate goals
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Memory hierarchy
Memory closest to CPU is most expensive (fast) but smallest
On-chip
On-board
In-system
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EE 333
Main and cache memory
Each memory may contain a subset of the others
Processor
Data are transferred
Cache
Main
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EE 333
Storage hierarchy
Information flows between layers
Less costly Faster
Directly accessed
Indirectly accessed
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EE 333
Principle of locality
Programs access a relatively small portion of their address space at any instant of time
• Temporal locality: once memory is accessed, its likely to be accessed again (locality in time)
• Spatial locality: once a memory address is selected, its neighbors are likely to be selected (locality in space)
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EE 333
Memory devices
• RAM: random access memory– Random access memory (versus sequential)– Read and write– Usually loose contents with power (volatile)
• ROM: read-only memory– Read only memory– Also random access– Usually non-volatile, or OS protects it
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Lillevik 333f06-l14 12University of Portland School of Engineering
EE 333
• Inputs– Address– Data in (RAM only)– Read/write control (RAM only)– Enable
• Outputs– Data out– Usually tri-state drivers (on & off, pull-ups)
Memory components
A
DQ
E
R/W
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Lillevik 333f06-l14 13University of Portland School of Engineering
EE 333
Tri-state drivers
• You may connect tri-state outputs together
• Must assure only one driver enabled at-a-time
• Common in memory designs, results in MUX function
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EE 333
General memory design
A
DQ
E
R/W
A
DQ
E
R/W
In 0
E
1
n
AddressData
R/W
Qout(lower bits)
(upper bits)
decoder
memory
memory
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EE 333
Memory design guide
• Bus lower addresses to all devices• Use upper addresses and decoder for device
enables (only one active component)
• Data bus and other control signals sent to all devices
• No read-write signal for ROM• Bus outputs together because they are tri-
stated
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EE 333
ROM design: 64 x 8Use 32x8
First ROM
Second ROM
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EE 333
ROM 64x8 trace
First ROM selected Second ROM selected Float
ROM file data is the address
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EE 333
ROM design: 64 x 16 ?Use 32x8
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EE 333
ROM 64x16 trace
First ROMs selected Second ROMs selected Float
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EE 333
Memory capacity and components
c00c0n c01
c10c1n c11
c20c2n c21
c30c3n c31
cm0cmn cm1
Greater length (bytes)
Greater width (bits)
m rows, n columns
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EE 333
Find the array of components?
Memory Component Length Width4K x 8 2K x 4
16M x 32 1M x 8
4G x 64 500M x16
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EE 333
General memory design
A
DQ
E
R/W
A
DQ
E
R/W
In 0
E
1
n
AddressData
R/W
Qout(lower bits)
(upper bits)
decoder
memory
memory
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EE 333
RAM design: 16x8Use 16x4
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EE 333
RAM 16x8 trace
Writing Reading
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EE 333
RAM design: 32x8 ?Use 16x4
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EE 333
RAM 32x8 trace
Writing
Reading
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EE 333
Fall 2006
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EE 333
ROM design: 64 x 16 ?Use 32x8