fabrication and characterization of n- and p-type a-si:h thin film transistors

8/13/2019 Fabrication and Characterization of N- and P-Type a-Si:H Thin Film Transistors

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Fabrication andCharacterization of N and

P Type a Si:H Thin FilmTransistors

ngineering Practical

Jeffrey Frederick GoldFitzwilliam oll ege

Universi ty of ambridge

L e nt 997


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FABRICATION ANDCHARACTERIZATION OF

n AND p TYPE a Si:H THINFILM TRANSISTORS

Jeffrey Frederick Gold

UNIVERSITY OF CAMBRIDGE

CAVENDISH LABORATORY

CAMBRIDGE C B OHE

Introduction

Herein we describe the fabrication and characterization of n- and p-type amorphous sil

icon thin film transistors TFTs ). The planar, inverted-staggered, type A ( unpassivated)TFTs described were fabricated as part of thelaboratory practicals of the 1996 MPhil program in Microelectronic Engineering and emi-

conductor Physics

Fabrication

The fabrication procedures consisted of the fol

lowing :

1 Substrate preparation in clean-room conditions.

2. Deposition of silicon dioxide (Si 0 2 passivation layer in PECVD system.

3. Annealing step was not performed andul t imately affected device quality).

4. Deposition of a-Si: H layer.

Figure 1: Geometry and composition of nchanne l keyhole a-Si :H TFT. illustrationadapted from [3].

5 . Depos ition of doped n + ) a-Si:H layer.

6 . D eposition of chromium and aluminumon ly aluminum in the case of p- type

TFT) .

7. Photolithogra p hy of a-Si:H TFT channelreg ion .

8. P h ot o li t hography of a-Si:H island region(see Figure 3) .

9. D evices were never annealed becausefabrication processes failed bonding ofphoto-resist to exposed surfaces) near endof fab ri cation procedure. All devicesdescribed henceforth are from previousye a r s.

Cross -sectional view of TFTs is shown in Table 1 be low . The fina l geometrical configuration and stratigraphy is given in Figures 1 and2.


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mGlass Substrate0 a Si:H

Gate Insulator

Electrodes

n type a Si:H

Figure 2: Stratigraphy of inverted-staggered n-channel type-A (unpass ivated) TFT. illustration adapted from [3]

Figure 3: Talystep SLOAN DECTAC II measurement showing lengthwise cross-section ofn-type keyhole structure.

Layer I Thickness

Aluminum1000

Chromium 1000n-type Si 500

a-Si:H 3000Si02 5000 Ac-Si 0.5 mm

Table 1: Cross-sectional view of TFTs. In thep-channel TFT, the chromium layer is missing.Here, the bottom layer is the substrate.

2

haracter izat ion

The bias stressing of the transistors consistedof the following procedures:

1 Measurement of TFT as is .

2 0 Volt bias anneal.

3 Measurement of annealed TFT.

4 . Bias stress TFT at +20 Volts at 75 for1000 sec.

5. Measurement of stressed TFT.

6. 0 Volt bias anneal.

7 Measurement of annealed TFT.

8 Bias stress TFT at -20 Volts at 75 for1000 sec.

9. Measurement of stressed TFT.

10. 0 Volt bias anneal.

11. Measurement of annealed TFT.

Discuss ion

P-channel devices were created by allowingaluminum to diffuse into the amorphous silicon. In n-channel devices, a chromium barrierlayer was deposited before the deposition ofaluminum.

The physics of MOS (metal-oxide-silicon)devices is relevant to our discussion of the electrical characteristics of these devices [1][4] Interface traps and oxide charges affected the device performances, although for hydrogenatedamorphous silicon, the defect density is greatlyreduced. These defects tend to control manyof the electrical characteristics of the materialand are responsible for the characteristic meta-stability


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Bias Stressing of TFTs

In the bias stressing test, in which weak Si-Si

bonds were broken with resulting defect formation by the injection of charge carriers atthe a-Si:H/insulator interface, we found thatdevice characteristics, such as electron O-bilities, threshold voltages, and pre-thresholdslopes PTS), for example, were altered. Thephysics behind these device characteristics proposes that the defect state density moves upward past the Fermi level for the negative biasstress and moves down for the positive bias

stress, according to the defect model [2]. Eventhough the devices were bias annealed, therewas evidence of migration of device characteristi cs, especially in the case of p-channel TFTs.That is to say, the formation and destruction ofdefect states was not as reversible in p-channeldevices as in the case of n-channel devices. Inthe case of the positive bias stress test for thep-channel devices, the drain current increasedaft er the test , indicating a higher thresholdvoltage at the gate.

We extracted the following TFT parameters:

Bias State Mobility Vt PTS0 V Anneal 0.156678 30.2026 0.243092

+20 v 0.174701 31.7757 0.2295280 V Anneal 0.153862 30.1007 0.244402

-20 v 0.025447 33.0822 0.0798960 V Anneal 0.154425 30.3751 0.237142

Tabl e 2: The effects of annealing and biasst r essing on n-chann el device mobility, threshold voltage V t), a nd pre -thr eshold slop e

PTS).

The sub-threshold volta ge is of interest b e-caus e it giv es an indication of the density ofstate s in th e bandgap. As the voltage increases, the den sity of state s m ove higher intothe bandgap region toward the conductionband, first through a lin ear region, and then

3

Bias State Mobility Vt PTS0 V Anneal -0.04121 -11.0199 -0.42323

+20 v -0.05310 -19.6468 -0.352330 V Anneal -0.04309 -11.4161 -0.37966-20 v -0.05792 -24.7844 -0.54844

0 V Anneal -0.04428 -11.7321 -0.40778

Table 3: The effects of annealing and bi a sstressing on p-channel device mobility, threshold voltage (Vt), and pre-threshold slope

PTS).

later, as the voltage increases, into a saturationregion. Amorphous silicon ( a-Si) is slightl y ntype by its very nature because of the highernumber of defects and higher dangling bonddensity [2].

Threshold Voltages and PreThreshold Slopes

Both n- and p-type devices, when subjected toth e +20 V and -20 V bias te sts, demonstratedthat the threshold voltages increased (see Tables 2 and 3). This means that higher voltages are required to activate the device, a fac etalso realized from the rather shallow prethreshold slopes. The plots for pr e-thr es holdslopes are given in Figures 4 and 5.

C Characteristics

We obs erved the shifting of t he C -V characteristic curves as a result of t he resident o xi dechar ge . The p-chann el devic es displa ye d mor ehysteresis than n-channel devices.

Electron Mobility

Note that p-channel devic e mobili t y i s off b ya fa ctor of 3 from n -chann el d evic e mobilit y.This is in keeping with the retard ed mobilitie sof holes with respect to elect ron s . How eve r ,


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.26 r . r . . r ...... r - - r - . - -

: ~ ~ - r - - ,

t i l .2 --+--t- +,-+ 1 t i

~__ 7 - _ =r=r=

. . . 4 I-5

z 1 ; N ~ t a nel PH.08 1-- - - -+- - -+-- t - -+- - t - - - - 1- - t - -+- - t.06 L-....1... . . . . .--1---- --- --- ----L----< --.. .___.____,

25 20 15 10 5 0 5 10 15 20 25Bias

Figure 4: N-channel Pre- Threshold Slope(PTS) vs. Bias.

.325

.35

.375.4

t i l.... .425~

1l .45= .475=..5c:

u.525

.55

--: ;?, - -

/

1 --/ .

vr--- -- -

/ I P-c anrtel TS.575

25 20 15 10 5 0 5 10 15 20 25Bias

Figure 5: P-channel Pre- Threshold Slope(PTS) vs. Bias . P-channel devices displayedmore meta stability than n-channel devices,that is to say, device characteristic values in p-channel devices did not readily return to initialvalues after 0 V bias annealing as did n-channeldevices after stress testing.

4

.18

.16

.14; ~ 12

.11l

.08

-5 .06

z .04.02

Iv

JP

II

I&N - har

-- -

ne M bil ty

25 20 15 10 5 0 5 10 15 20 25

Bias

Figure 6: N-channel Mobility vs. Bias. Here

the 0 Volt data imply annealing was carriedout with no bias prior to measurement, as inTable 2.

the mobilities exhibited in our n-channel devices were approximately one order of magnitude less than expected values. The mobilitiesfor the bias stressing tests are plotted in Figures 6 and 7.

Conclusion

Device and fabrication failure made it difficultto extract any meaningful data for analysis;however, we characterized the devices and extracted such information as electron mobilities,threshold voltages, and pre-threshold slopesfrom the data obtained.

cknowledgements

I would like to thank our lab assistants for theirlively discussions and enthusiasm throughoutthe practicals. I would also like to expressmy gratitude to my teammates, Jason Lin TanDowning) and Steven Keller Churchill).


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-.042 ~ ~ ~ ~ f - - - ' : l l ' < : , \ . - + - + - + - + - - 1

e. -.044 1 - -1 - - - 1 - t - - A / ) < : ' \ ' . : l \ . - t - - + --

::s - . 0 4 6 1 - - 1 - - + - - + - - w - + - ~ ~ ~ - - + - - 1 - - 1.g - . 0 4 8 1 - - - t - - + - t . ~ + - - 1 - ~ - t - - + - - 1~ -.05 ~ ~ - - - 4 1 f f - +- - l - - -~ - - - l] -.052 A I'.; -054 - ---.11 -- - -+ - - - + - - - - 1 ~ .

~ -.056 V 1-ch nnel ob lil]-.058 ---- ....... --- ...... .. ..... ---- ........ ......... ....... ........

-.06 L..-.L.........L-...1.-....J...-..J...-...J..-....1..-....1.-....L...-J-25 -20 -15 -10 -5 0 5 10 15 20 25

Bias

Figure 7: P-channel Mobility vs. Bias. Here

the 0 Volt data imply annealing was carried outwith no bias prior to measurement as in Table 3. P--channel devices displayed more metastability than n-channel devices, that is to say,device characteristic values in p-channel devices did not readily return to initial valuesafter 0 V bias annealing as did n-channel devices after stress testing.

References

[1] Sze, S. M. Physics of SemiconductorDevices, 2nd Edition. John Wiley SonsLtd. , New York, 1981.

[2] Street R. A. Hydrogenerated AmorphousSilicon. Cambridge University Press, Cambridge, 1991.

[ ] The Fabrication and Characterisation ofHydrogenated Amorphous Silicon Thin FilmTransistors a-Si:H TFTs . EngineeringDepartment/ MESP Handout. CambridgeUniversity, 1996.

[4] Sze, S . M. Semiconductor Devices: Physicsand T echnology. John Wiley Sons Ltd. NewYork, 1985.

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fabrication and characterization of n- and p-type a-si:h thin film transistors

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