fa techniques for ic_ lakshim34

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34 w w w . r f d e s i g n . c o m February

Today’s electronic system s a re becoming morecomplex and compact. Concepts of quality and

reliability are increasingly applied to products andye t syste m c om pone nt f a ilur e s a r e sti l l c om m on.Failure of a system causes disruption in the serviceand costly down-time for repair, which affects thee conom y of ope r a tion. F a ilur e a na lysis ( F A) c a ngive valuable insight into th e causes of failure an d

provide inputs for product improvement. It is a tool f or syste m r e lia bili ty e va lua tion. S e vtechniques are used to carry out the FA of electic components, some of which are described inart icle. Examples based on FA case studies are

presented to illustrate the various techniques usFailure analysis identifies the causes of fai

by analyzing stresses and other mechanisms ci n g f a i l u r e . I t a l s o a d d r e s s e s t h e p e r f o r m adegradation of components and develops correcmeasures. A failure mechanism u sually leads tidentifiable change in a component. Semicondudevice failures can be explained u sing a physicfailure approach. The bath-tub curve (see Figuris a commonly used model for describing t he faiof components - electronic or mechanical.

The infant mortality failures are due to defduring manufacture, improper design or implemtation of the component, or freak failures that hnot failed during screening. The normal operaregion of the curve, which is the useful life phas

the component, is long when comparing electrc o m p o n e n t s t o m e c h a n i c a l p a r t s . M o s t p r o ddesigns get revised before this phase of the etronic components is passed. Usually, failures ing this phase are caused by stresses such as htemperature (thermal overstress), high voltage/r e nt ( e le c tr ic a l ove r str e ss) , hum idity, vibr a tmechanical or ther mal shock.

Wear-out failures occur after the useful life pof the component has passed. Examples of wearfailure are: corrosion, electrical leakage, insulabreakdown, migrat ion of metallic ions in the direc

of current flow, cracking of the ensulating material due to deterioraof the material, and cracks in the bwires due to repeated stresses.

Failure analysis as a toolFA is used to evaluate the relia

ity of a product under actual option. A failed component can proi m p o r t a n t i n f o r m a t i o n t o e n h athe reliability of a device or prodDepending on the type of compofailure, t he failure m ode, mechana nd f a c tor s suc h a s str e sse s c a nidentified, inducing the failure i n i t i a t i n g a p p r o p r i a t e c or r e cm e a sur e s. F A pr ovide s f e e dba cthe product designers for improd e s i g n o r e v e n c or r e c t i n g m ide sign f a ults tha t m ight ha ve b

overlooked in t he in itial design.The objective of FA is to identhe cause of failure and initiate r e c t i v e a c t i o n . F e e d b a c k f r o mcan implement improvements ind e s i gn a n d / or c on s t r u c t i on o fc om pone nt, or im pr ove m e nt ind e s i gn o f t h e p r o d u c t w h e r e component is used. Such action

s e m ic o n d u c t o r s

Knowing why devices fail is am ust wh en d esigning

next-generation products.

B y V. La k s h m i n a r a y a n a n

Failure analysis

techniques forsemiconductorsand other devices




ally modifies the design by incorporat-ing additional components or by m odi-f ying the a pplic a tion c ir c uit . S e ve r a ltechniques are u sed in F A work to findout the c a use of fa ilur e . The m e thoduse d in the F A inve stiga tion de pe ndson the severity an d t ype of problem.

The te c hnique s use d in the c a se of e le c tr onic de vic e s r a nge f r om sim plee le c tr ic a l m e a sur e m e nts to e xa m ina -tion of de c a psula te d sa m ple s unde r am i c r o s co p e . M a x i m u m i n f or m a t i o nshould be gathered from the failed sam-p l e s u s i n g n o n -d e s t r u c t i ve m e t h o d s

before the devices are opened.

Investigative proceduresTo initiate a proper corrective action,

the f a ilur e m e c ha nism of the c om po-n e n t m u s t b e c o r r e l a t e d t o t h e f i e l dobservations of the operat ing conditionsthat caused th e failure.

The first step is to collect data on then u m b e r o f f a i l u r e s o b s e r v e d a n d t h esa m ple size . This infor m a tion, whe ncollected over a large number of loca-tions where t he system is deployed, willhe lp the a na lyst de c ide a bout the sta -t i s t i c a l s i g n i f i c a n c e o f t h e f a i l u r e .Information should be collected on the

obse r ve d pr oble m a nd the c onditionsu n d e r w h i ch t h e f a i lu r e o ccu r r e d . I f the f a ilur e oc c ur s dur ing a pa r tic ula rtest condition or operation, the possiblestresses likely to be encountered by thecomponent can give a clue to the possi-ble cause of failure. Sometimes, equip-m e n t t h a t fu n c t ion s w e ll i n on e a r e aw i l l d e v e l o p p r o b l e m s a t o t h e r g e o -

graphical locations because of environ-menta l or E MI/RFI conditions.

Furthermore, situations could existin which the problem may not be withthe f a ile d c om pone nt a t a ll , but withthe wrong application of the componento r l a c k o f p r o p e r c i r c u i t p r o t e c t i o n .These issues may cause the failure of the component by exposing it to higher-t h a n - n or m a l s t r e s s l e ve ls t h a t t h edevice is rated to withstand.

Based on the data collected, a proce-dure is chosen. As a preliminary step, arough flow-chart of the FA procedure to

be used is drawn up based on t he type of problem. Informa tion is collected aboutthe de sign i .e ., c ir c uit dia gr a m of thecard where the component is used, datasheet of the component that has failed,m a ke a nd ba tch num be r de ta ils, num -ber of failures, and the conditions underwhich failures occur. Based on this pre-liminary study, a hypothesis is drawnabout the cause and type of failure.

In the next step, fresh samples of thedevices from the same batch are soughtfor further testing. This helps identifycomponent-level fault s, inherent deviceproblems, application problems, batch-related problems and any other related

c a u s e o f f a i l u r e . T h e c o m p o n e n t s ,unle ss the y a r e de str oye d by the f a il-ure, are tested electrically in a compo-nent tester th at checks t he functionali-ty of the device, or in a curve tracer, tostudy the V-I characteristics. A similartest is carried out on a good sample toverify d ifferences in the electrical char -acteristics between the good and failed

devices. Once th e failure is verifiedmode of failure is identified by anthe FA techniques described furtherAnd, depending on circumstancesanalyst may decide to analyze the cponent’s syst ems a s well.

Components do not generally faitheir own. The cause of failure is raidentified as an infant mortality casa ba tc h pr oble m . F a ilur e s a r e usudue to extern al forces — electrical ostress (EOS), thermal overstress, ha n dling ( e . g. e le c tr osta tic disc ha(ESD) damage, or problems createcomponents in the vicinity or assoce d c ir c uits. S om e tim e s othe r c omnents in the circuit can cause the ure of a device (e.g. transformer lage inductance, caused by a defectr a nsf or m e r ) . High- te m pe r a tur e hs i n k s m o u n t e d c l o s e t o e l e c t r o lcapacitors can a lso cause failure of

c a p a ci t or s . F a i lu r e ca n b e c a u s e ddefective PCB const ruction or operaenvironment, or similar factors a s w

A f t e r a n F A i n v e s t i g a t i o n i s cplete, a report should be made detaithe analysis. The report should incd e t a i l s a b o u t t h e p r o bl e m r e p o ranalysis carried out, test results, ri n g s o f p a r a m e t e r s ( if t a k e n ) , t en i q u e s u s e d f o r t h e i n v e s t i g a t i obatch number and make of the comne nt involve d, e xa c t c a use of f a iidentified, an d corrective action recmended to address the failure.

Ove r the ye a r s, se ve r a l te c hniqhave been developed for ana lyzing v

ous component s. Some of the commuse d te c hnique s f or the a na lysis semiconductor component are listeTable 1.

T h e d e c i s i o n i n e a c h c a s e o nmethod to be used for failure analdepends on the extent and type of ure observed.

FA analysis techniquesWhen a device failure is identifie

is necessary to proceed systematicFirst, th e faulty card or module shbe examined thoroughly to see if thare any visible a nd obvious ma nifet i o n s o f f a i l u r e o r d a m a g e , s u c h

charring of device.Try to collect as much data as po

b l e a b o u t t h e e x t e n t o f t h e f a i lAna lyz e f r e que nc y, c onditions unw h i c h t h e f a i l u r e o c c u r s , w h e t h eo cc u r s d u r i n g a n y p a r t i c u l a r l o atest condition, number of failures t h e c or r e s p o n d i n g s a m p l e s i z e , whether any correlation can be dr

Figure 1. Failure types over time.




between related failures of the cards orcomponents. Go about the analysis in astep-by-step fashion using non-destruc-

tive techniques initially and graduallyprogressing to destructive methods of ana lysis. The objective of this approachis to avoid destroying evidence and toe n s u r e t h a t t h e ch e m i ca l a c t i on s o f

d e s t r u ct i v e m e t h o ds d o n o t l e a d t o afaulty analysis.

F o r e x a m p l e , t h e u s e o f a c id s fo retching a plastic package could lead tocorrosion of metallic parts in the device.Conditions such as metalization in thep r e s e n c e o f c or r o s i v e c h e m i ca l s a n dmoisture may make it difficult to deter-mine whether the corrosion was existed

b e fo r e t h e d e vi ce w a s op e n e d o roccurred due to chemical action afterthe device was opened.

E n v i r o n m e n t a l c o n d i t i o n s s u c h a shum idity, te m pe r a tur e , dust , sa linity,and presence of chemical contaminantsi n t h e a r e a o f o p er a t i on s h o u l d b enoted. Any drift in the component oper-ation parameters should be examined,as well as any associated fault in someot h e r co m pon e n t t h a t m a y h a v e t r i g -gered the failure.

Functional and parametricelectrical tests

In the case of semiconductor an d pas-sive components, the failed sample ise l ec t r i ca l l y t e s t e d i n a n a u t o m a t i ct e s t e r , or b y u s i n g l a b o r a t or y i n s t r u -

ments (oscilloscope, test pattern genera-

tor, curve tracer), to verify the failurea n d o b s e r v e t h e c r i t i c a l p a r a m e t e r s .Device malfunction and any deviationfrom standard device characteristics canb e o b s er v e d b y t h i s m e t h o d . A c u r v etracer is used to study the input/outputcharacteristics of the device. Faults suchas open/short circuit and degradation of device characteristics can be detected by

this method as well. X-ray examinam a y be done a t this sta ge to f indinternal defects in the component.

Microscopy techniques• Low-magnification microscopy —component is initially examined una low-power optical microscope hav

a magnification from 10 to 100 X. i s u s e d t o o bs e r ve a n y e x t e r n a l dage, verify the logo on the packagev e r i fy d i e l ot s a n d d e t e ct s p u r idevices), and handle damage and hline fractures in th e component’s leor pins. These observations shoulrecorded as part of the analysis.

Photograph 1 shows a typical fa

Step Method Description

1 External visual examination Failed samples are examined, microscopically if required,and observations are noted.

2 Electrical measurement and testing The component is tested to check functionality. Measurementof critical parameters is made to identify failure mode.

3 IR or X-ray examination This is used to non-destructively view the internal connections

and structure prior to decapsulation.

4 Decapsulation The internal structure is exposed for examination. This isdone either by mechanical or chemical methods.

5 Optical or electron microscopy The die is examined under high magnification for evidence ortype of failure.

6 Destructive analysis Selective etching of layers. Bond pull, die shear and internalcircuit probing are useful techniques.

Table 1. Commonly used techniques for semiconductor component failure analysis.

Photograph 1. A hairline crack in the plasticencapsulation.

Photograph 2. The internal view of an IC.

Photograph 3. Internal view of a bipolar junctiontransistor.

Photograph 4. Solder bridge short.

Photograph 5. Bondpad and wire failure.




which can be observed by t his m ethod.Notice the hair-line crack in the plasticencapsulation of the IC due to internal-ly generated thermal overstress.• High-magnification optical microscopy— After a device is decapsulated, theinne r str uc tur e c a n be e xa m ine d by ah i g h e r m a g n i f i c a t i o n ( u p t o 2 0 0 0 X )

optic a l m ic r osc ope . S uc h a de vic e isuse d to r e ve a l da m a ge to the inte r na ls t r u c t u r e . B e for e e x a m in a t i o n , t h esample sh ould be ultra sonically cleanedt o r e m o v e fi n e p a r t i cl e s o f d u s t t h a tm a y a d h e r e t o t h e d e vi ce s t r u ct u r ea f t e r t h e d e ca p s u l a t i on p r o ce s s .Damage due to EOS, corrosion of met-

a l i za t i on p a t t e r n s , d a m a g e t o b owires, oxide layer damage a nd spifaults can be ident ified by this met h

Photographs 2, 3 and 4 show exples of such an observation.• I n f r a - r e d ( I R ) m i c r o s c op y – Tm e thod r e lie s on the tr a nspa r e ncsilicon-to-IR wavelengths. Using

Semiconductor devices• Penetration of moisture, flux contaminants during solder-

ing, washing of boards, storage under humid conditions.Due t o seal integrity problems.

• M e c h a n i c a l s t r e s s c r a c k s d u e t o d i f f e r e n t i a l t h e r m a lexpansion of plastic encapsulant , metal leads, die.

• Chip-to-substrate atta chment failure leading to voids a ndthermal stress problems.

• Bond wire snapping due to EOS• Deformation of bond wires due t o improper bonding.• Cracks at the bonding pad-bond wire junction• Metalization da mage du e to EOS, ESD, corrosion.• Electromigration of metal along the direction of current

flow.• Hillock formation by meta l ions.• Degradation of metalization at high temperature.• Oxide la yer fa ults due to im pur ities, ES D da m a ge, pin-

hole due to etching pr ocesses.• Defects in the bulk semiconductor material, such as crys-

tal defects.• Design a nd fabrication faults, misalignment of layers, geo-

metric defects.• Leakage at p-n junction.• Deviation from the n ormal chara cteristics of the device.

• Changes in threshold voltage/current characteristics.

Resistors• Ope n c ir c uit c a use d by the r m a l ove r str e ss due to EOS

(high current flow leading to increased I2R loss).• Cracks at the lead-body inter face leading to open-circuit.• Degradation in value due to application of high levels of

stress, exposure to high humidity conditions, high temper-ature operating environment.

Capacitors• R uptur e of oxide f i lm in e le c tr olytic c a pa c itor s due to

application of high electric field.• Le a ka ge of e le ctr olyte in e lec tr olytic ca pa c itor s due to

high temperature, faulty seal.• Moisture ingress due to voids between the leads a nd body

leading to a sh ort circuit.• Leakage current.• D e gr a d a t i on o f d ie l ect r i c m a t e r i a l d u e t o e x p os u r e t o

humidity, high temperature, aging.• A unique property of Aluminum electrolytic capacitors is

that they get set to the voltage at which t hey are operatede v e n t h o u g h t h e r a t e d v o l t a g e m a y b e h i g h e r . H e n c eexcessive derating of applied voltage should n ot be done inthe case of such capacitors.

• Shift in parameters.• Lowering of insulat ion resista nce.• Open circuit failure.• Short circuit failure.• Corrosion of the electrodes due to chemical action caused

by contam inants and moisture.

• Polarity reversal in electrolytic capacitors can cause daage.

• Disconnection of lead wires from the termin ations.• Drying up of electrolyte due to operation at high temper

tur e .• Dielectric breakdown due to application of high volta

beyond the rating.

Coils• Open circuit of coil wire due to th ermal overstress caused

shorting of adjacent turns where insulation has been daa ge d dur ing winding pr oce ss or due to a m a nuf a ctur iprocess fault .

• Nicks an d kinks in the wire can cause the above failureoccur.

Transformers• Open circuit fault in primary and secondary windings d

to e xce ssive the r m a l str e ss c a use d by EOS , shor tingwindings as in the case of coils.

• H i g h l e v e l s o f p a r a s i t i c s s u c h a s l e a k a g e i n d u c t a n cinter-winding capacitance due to faulty design and manfacturing technique.

• Short circuit between pr imary an d secondary due t o po

isolation, low dielectric withsta nding voltage.• H i g h l e ve l s o f co p pe r a n d e d d y c u r r e n t l os s e s , w h i

l e a d s t o h i g h h e a t d i s s i p a t i o n i n t h e t r a n s f o r m e r aaffects adjacent components. Basically caused by podesign.

• Corona discharge can sometimes occur between adjacetur ns or windings. To pr e ve nt this, im pr e gna tion of ttransformer should be proper.

Relays• Arcing induced dama ge of conta cts.• C or r osion of c onta c ts due to ingr e ss of m oistur e , f lu

cleaning a gents du e to improper sealing.• Melting of contacts du e to Electrical Overstr ess (EOS).• Coil damage due to EOS.• Damage to plastic body due t o exposure t o high tempe

tur e e .g., dur ing solde r ing or inte r na lly ge ne r a te d hedue to EOS.

Printed circuit boards• Discoloration due t o exposure to high temperature duri

soldering, heat dissipation of component s on t he board.• Delamination due to exposure to high temperature.• W a r p i n g d u e t o e x p o s u r e t o h i g h t e m p e r a t u r e , f a u

board design (insufficient t hickness of the lam inate, faulayout and mount ing of components on the board).

The commonly observed failure mechanisms, their causa na lysis te c hnique s to de te c t this f a ult , a nd te st sc r e euse d to pr e c ipita te the f a ilur e m e c ha nism s a r e l iste d Table 2.

Common failures in semiconductor devices, passive components




t e c h n i q u e , c e r t a i n t y p e s o f f a i l u r e ,suc h a s ba ll bond de f e c ts, c or r osion,i n t e r m e t a l l i c d i f fu s i o n , o ve r s t r e s seffects, and spiking across layers, canbe identified. To prepare a sample forI R m i c r o s c o p y , t h e b a c k s i d e o f t h e

p a c k a g e i s p o l i s h e d t o r e m o v e t h ee n c a p s u l a t i o n . O n r e a c h i n g t h e d i es u r f a c e, t h e p o l i s h i n g i s s t o p p e d .V i e w s o f t h e d e v i c e ’s l o w e r l a y e r s ,which cannot be seen by decapsulationof the uppe r pa c ka ge , c a n be se e n byt h i s t e c h n i q u e . B e c a u s e t h e u p p e rlayer of the device is not damaged bychemical etching, electrical measur e-m e n t s c a n b e m a d e o n t h e s a m p l e i f r e quir e d. ES D a nd c or r osion da m a gein the inne r la ye r s of de vic e s c a n beidentified using th e IR technique.

Other techniques used to study theinternal structure of devices are scan-n i n g a c o u s t i c m i c r o s c o p e , s c a n n i n g

e l e c t r o n m i c r o s c o p e , a n d X - r a y a n dt h e r m a l i m a g i n g t e c h n i q u e s . T h e s etechniques ar e u sed when optical t ech-niques do not h elp identify the pr oblem.Finally, micro-probing may be u sed to

m a ke a ny m e a sur e m e nts a nd ide ntif ythe failed nodes in t he device.

P hotogr a ph 5 shows a c a se of EOSdama ge using a n IR microscope.

Decapsulation techniquesD e c a p s u l a t i o n i s a n F A t e c h n i q u e

u s e d f o r i n t e r n a l e x a m i n a t i o n o f t h edevice. With rapid strides being madein the area of device technology, newtypes of packaging materials for encap-sulation are being developed and usedin the m a nuf a c tur e of se m ic onduc tord e v ic es . D e p e n d i n g o n t h e p a c k a g ematerial used, different techniques a reused for opening devices.

Some of the commonly u sed pa ckag-ing materials are plastic, ceramic andm e ta l- ca n pa c ka ges. P la stic e nc a psu-lation is etched out by chemical agentssuc h a s hot f um ing nitr ic a c id or sul-p h u r i c a c i d d e l i v e r e d t h r o u g h a j e t

de live r y syste m . The r e a r e a num be rof dif f e r e nt e tc hing a ge nts a va ila ble ,so using the pr ope r one is im por ta nt 4.M e t a l a n d c e r a m i c p a c k a g i n g a l s oha ve spe cific de c a psula tion m e thods.

F o l lo w in g a r e t y p i c a l m e t h o d sdevice decapsulation.

• C e r a m i c p a c k a g es a r e o pe n e dr e m oving t he e nca psula tion m e chcally. These tools depend on the fturing of the brittle ceramic packa

for opening by application of pressu• M e ta l-ca n pa c ka ges su c h a s t

sistors are opened using rotary cutfitted with sharp blades.

• M e t a l - li d d e d p a c k a g e s s u c ht h o s e u s e d i n s o m e L S I d e v ice sopened mechanically by means of ing a c or ne r of the se a l a f te r sa wThe r m a lly ope ning the solde r se aalso possible provided care is takeavoid therma l overstress damage t odie within. In all cases, care shoulta ke n to e nsur e tha t the tool doe sdamage t he interconnections or th eduring the decapsulation process.

• G l a s s p a c k a g e s a r e d e l i ca t e

r e q u i r e c a r e fu l h a n d l i n g . T h e yo p e n e d b y m e c h a n i c a l l y l a p p i n gpackage along the axis until the acdevice region is reached.

The sidebar contains an overvie

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c o m m o n f a i l u r e s i n s e m i c o n d u c t o rdevices an d pa ssive components.

Looking aheadMiniaturization of electronic compo-

n e n t s i s p r o g r e s s i n g a t a r a p i d p a c e

a n d d e v ice g e om e t r i e s h a v e s h r u n k o v e r t h e y e a r s w i t h a c o r r e s p o n d i n gincrease in the circuit complexity. Newmaterials are being developed for pack-aging devices at a lower cost. This isalso to protect against thermal stresses,a nd m oistur e . Highe r c om ple xity a n df in e r d e v ic e g e om e t r i e s w i l l p r e s e n tproblems for failure analysis work andr e quir e ne w type s of instr um e nta tiontechniques t o probe into the die - levelworld. A failure analyst should have athorough knowledge of component andsystem design techniques to effectivelytackle failure analysis tasks. The rapidstrides in the field of integrated circuit

technology and microelectronic packag-ing te c hnique s will thr ow up a lot of c ha lle nge s f or f a ilur e a na lysts in thecoming years.

References

[1] Edgar A. Doyle: How Pa rts Fail,IEEE Spectru m, October 1981.

[2] Ameraseker a E. A., et al: Failuremechanisms in semiconductor devices,

John Wiley & Sons, 1987.[3 ] Av r a m B a r -C oh e n , e t a l :

A d v a n c e s i n T h e r m a l M o d e l i n g o f Ele c tr onic C om pone nts a nd S yste m s,Vol. 3, IEEE Press 1993.

[4] Emiliano Pollino: Microelectronic

Reliability, V ol. II , Artech House, 1989.[5] Giulio Di Giacomo: Reliability of

Electronic Packages an d S emicond uctor devices, McGraw Hill, 1997.

[6 ] L a k s h m in a r a y a n a n , V. :M i n i m i zi n g F a i l u r e s i n E l e ct r o n i cS y s t e m s b y D e s i g n , E D N , A u g u s t 3 ,2000.

About the authorM r . V . L a k s h m i n a r a y a n a n h o

an M. E. in electrical communicate n gi n ee r in g fr om t h e I n d

I nstitut e of S cie nce , B a nga lor e ahas more than 17 years of experiei n t h e d e s i g n a n d d e v e l o p m e n te lectr onic syste m s. He is a m e mof the I EEE a nd is the c oor dina tengineer - failure analysis & reliaity at the Centre for DevelopmentTelematics, Bangalore, India. He cbe contacted at: vln @cdotb.ern et.in

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fa techniques for ic_ lakshim34

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