F4 : Latches, Flip-Flops, Data buses & Resolved functions

Latches & Flip-Flops

SR-Latch

R

S

Q

Q

Q+ Qn+SR =

Q Qn 00 01 11 1000 11 01 00 1001 01 01 00 0011 00 00 00 00

10 10 00 00 10

Gated SR-Latch

R

C

S

Q

Q

D-latch

C

Q

Q

D

D

Clk

q

Master-Slave Flipflop

D

Clk

q

D

Clk

q

Edge-triggered Flipflop

Q

QClk

D

Latches

Mux:

process(a,b,sel)begin

if (sel=1) thenq

Signal Attributes

signal s:bit;

sdelayed(5 ns) =slast_event =

slast_active =

slast_value =

D-latch with asynchronous reset

Latch:

process(D,reset,clk)begin

if (reset=0) thenq

Asynchronous reset

process(clk,reset) -- synthesis might complain that d is not-- listed

beginif (reset=1) then

q

Bus Resolution in VHDL VHDL does not allow multiple concurrent signal assignments to the

same signal Multiple sequential signal assignments are allowed

-- this code will generate an errorENTITY bus IS

PORT (a, b, c : IN bit; z : OUT bit);END bus;

ARCHITECTURE smoke_generator OF bus ISSIGNAL circuit_node : bit;

BEGINcircuit_node

std_logic

type std_logic is resolved std_ulogic;

type std_logic_vector is array(integer range ) of std_logic;

type std_logic_LUT is array(std_logic,std_logic) of std_logic;

std_logic Resolved functionFunction resolved(input:std_logic_vector) return std_logic is

constant resolve_table:std_logic_LUT:=();variable res:std_logic:=Z;

begin

for i in inputrange loop

res:=resolve_table(res,input(i));end loop;

return res;

end resolved;

std_logic Resolved functionFunction resolved(input:std_logic_vector) return std_logic is

constant resolve_table:std_logic_LUT:=(-- U,X, 0, 1, Z,W,L,H, -

( U,U,U,U,U,U,U,U,U), -- U( U,X,X,X,X,X, X,X,-), -- X( U,X, 0,X, 0,0, 0, 0, -), -- 0( U,X,X, 1, 1,1, 1, 1, -), -- 1( U,X, 0, 1, Z,W,L,H,-), -- Z( U,X, 0, 1,W,W,W,W,-), -- W( U,X, 0, 1,L, W,L,W,-), -- L( U,X, 0, 1,H,W,W,H,-), -- H( U, -, -, -, -, -, -, -, -)); -- -

How accurate is the Resolution model?

VDD

VOH

VSS

VL

VL

N connected Units

Voltage levels

VH

VLNoise Margin

TTL VH>2.4 V, VL90% of VDD -VSS, VL Z

~10 kOhms => L, H, W

~10 Ohms => 0, 1, X

Physical representation of std_ulogic

VresRres

0.8V,2.4V - TTL10%, 90% - CMOS (% of VDD-VSS)

1kOhm, 1 MOhm (TTL)>1 GOhm (CMOS)

0 X 1

L W H

Z Z Z

Equivalent Two-pole of output stage

V

R

V=VOHR=ROH

VDD

VOH

VSS

VL

VL

Equivalent Two-pole of output stage

V

R

V=VOLR=ROL

VDD

VOL

VSS

VH

VH

0 - Forcing Zero

V

Two-pole equivalent

Rres = R1||R2Vres = V1*R2/(R1+R2)+V2*R1/(R1+R2)

V1

R1

V2

R2

Vres

Example: X - Forcing Unknown

VL 0.9*VDD then

if Rres> 1 (kOhm) then return H; else return 1; end if;elsif Vres> 0.1*VDD then

if Rres> 1 (kOhm) then return W; else return X; end if;else

if Rres> 1 (kOhm) then return L; else return 0; end if;end if;

Final Result table

VresRres

0.8V,2.4V - TTL10%, 90% - CMOS (% of VDD-VSS)

1kOhm, 1 MOhm (TTL)>1 GOhm (CMOS)

0 X 1

L W H

Z Z Z

Example - Resolution functions

How many Open Drains (H) can be connected to a Forcing Zero (0) before the Forcing Zero goes into the unknown region?

How many Open Source (L) can be connected to a Forcing One (1) before the Forcing One goes into the unknown region?

Example: D-Flipflop with Tri-state enable

En

D

Clk

Q

Example: I2C (CAN)-bus protocol

0

1 2 3 4

Single wire usedboth for arbitrationand communicationin any direction!!!

Appendix

Dataflow Modeling of Tri-state functionality

Dataflow modeling

U0: q0

Concurrent If-statements

q

The Implicit Guard-signal The Guard can also be used as an implicit signal Example

ARCHITECTURE guarded_assignments OF n_1_regs ISBEGINbi: FOR j IN regsrange GENERATE

bj: BLOCK (enable=1 and read=1)BEGINx

X - Forcing Unknown

VL

H - Weak High (Open Drain)

VH