f3 mpc5500 print - nxp semiconductors...56f8300 hybrid series 56f800 hybrid series mid 56f800 hybrid...

1

Slide 1

Introduction

PURPOSE:

- Introduce Freescale’s MPC5500 family of microcontrollers, with specific focus on the MPC5554 and the MPC5553 devices.

OBJECTIVES:- Describe the features of the MPC5000 family.- Identify significant system performance improvements to the MPC5500

family.- Compare and contrast the features of the MPC5554 and MPC5553.- Describe an enhanced Time Processing Unit (eTPU).- Describe the types of support offered with the MPC5500 family.

CONTENT:- 31 pages- 5 questions

LEARNING TIME:- 45 minutes

This course covers the newest generation of Freescale’s PowerPC 32-bit microcontrollers: the MPC5500 family. This course describes some of the features of this exciting 32-bit, MPC5500 family, with specific focus on the MPC5554 and MPC5553 devices. The course also provides some detailed technical information and identifies the types of support that are available.

2

Slide 2

Devices

HighmobileGT™ MPC5200PowerPC® MPC5500 familyPowerPC® MPC500 familyColdFire® MCF5xxx family

UpperMid

ColdFire®

56F8300 hybrid series56F800 hybrid series

Mid 56F800 hybrid seriesHC(S)12 16-bit families

Low HCS08 low-voltage, low-power familyHC08 QT/QY family

Range

The Controller Continuum, Analog and SensorsA full range of products, technology, services and tools for a complete system

Sense(Sensors)

Process(MCU, MPU, DSP)

Control(Analog)

.

ControlSystem

SensorsAnalog

Low-g accelerometersTire pressure monitoring system (TPMS)

eXtreme SwitchMotion controlPower mgmt.E-FieldQUICCsupplyI/O expansion

Software, Tools, &

Services

Here is an overview of Freescale’s Transportation and Standard Products Group’s portfolio, listed by family. As with the MPC500 family, which was initially designed for large automotive OEMs, the MPC5500 family of devices fit into our standard products portfolio.

The MPC5500 family builds upon the large success of the MPC500 family. It is a next generation PowerPC microcontroller which was developed on the PowerPC BookEcompliant architecture for complex, real-time control applications. It uses a platform design of code-compatible cores with pin-to-pin compatibility. Freescale leverages new technologies to add more embedded Flash and more peripheral integration, while simultaneously improving overall quality and reliability through improved verification and the addition of new test features to meet zero defect requirements. Additionally, there is a widely supported integrated tool chain for development.

3

Slide 3

MPC5500 Family Applications

Service Processor

Engine Control

Avionics

AUV

Motion Control / Industrial Control

Utilities / Alt. Energy

Specific Applications include: Robotic Servo Control, Navigation Control, Autonomous Unmanned Vehicles (AUV), Power Management, Fuel Control, Environment Control, Camshaft Positioning, Spark Timing, Medical Patient Monitor, Alternative Energy, Turbine Control, Aircraft Instrumentation, Actuator Control, Various Military Applications, etc.

Target Markets

The MPC500 and MPC5500 families are ideal solutions for a large array of 32-bit embedded control needs requiring intensive, real-time control algorithms.

Although the MPC5500 family was originally designed for automotive powertrain and engine control applications, it has many other real-time applications. These include motion control, avionics, turbine control, robotics, medical applications, among others. The entire family features the eTPU, or enhanced Time Processing Unit for real-time processing, CAN, Ethernet, and other interfaces for communications. It also features 5 volt A to D converters for sensing and monitoring activities and a large array of embedded Flash. When combined with the high performance of the PowerPC core and its superb architecture, these features provide a superb solution for any real-time control application.

4

Slide 4

MPC5554PPC e200z6 core @ 80 or 132MHz2M Flash, 32K Cache, 64K RAM88-channel Timed IO40-channel ADC

MPC5553PPC e200z6 core @ 80 or 132MHz1.5M Flash, 8K Cache, 64K RAM56-channel Timed IO40-channel ADCEthernet controller

MPC5500 Roadmap

2001 2004 2007A

pplic

atio

n Pe

rfor

man

ce

MPC565

MPC561

MPC563MPC555

In Production

Planned

Proposed

In Execution

2002 2005 20062000

Note:Leading edge: Sample DateLagging edge: AEC Qual Date

MPC5554

MPC555x

MPC553x

MPC55xx

MPC5553(1.5M)

(2.0M)

MPC5534

Slide 4Freescale Semiconductor Confidential Proprietary. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004

Position your mouse pointer over MPC5554 and MPC5553 to learn more.

Here is the MPC5500 road map, with the existing MPC500 family shown in blue in the lower left. The MPC5554 and the MPC5553 are the first two MPC5500 products to come to market.TheMPC5534 is the third derivative of this family.

Other innovative technologies and peripherals will be introduced as the family continues to expand into several other derivatives over the next few years, including higher and lower performing cores, increased or decreased amount of integration, and various sizes of embedded flash, depending on application-specific needs.

Position your mouse pointer over MPC5554 and MPC5553 to learn more.

5

Slide 5

Question

Which of the following statements about the MPC5500 family are true? Select all that apply and then click Done.

a. The MPC5554 and the MPC5553 are the first two MPC5500 products to come to market.

b. The MPC5500 family builds upon the large success of the MPC5200 family.

c. The MPC5500 family is a next generation PowerPC microcontroller developed on the PowerPC BookE compliant architecture for complex, real-time control applications.

d. The MPC5500 family is designed for automotive powertrain and engine control applications, and motion control, avionics, turbine control, robotics, medical applications.

Done

Here is a question to test your understanding of the material.

Correct. Statements A, C, and D are true. Statement B is not true. The MPC5500 family was built upon the successes of the MPC500 family.

6

Slide 6

Actual PerformanceMPC563 vs MPC5554

MPC5554 vs MPC563

0.00

0.20

0.40

0.60

0.80

1.00

1.20

MPC563 Code onMPC563 EVB @

56MHz

MPC563 Code onMPC5554 EVB

@56MHz (CacheDisabled)

SPE Code onMPC5554 EVB

@56MHz (CacheDisabled)

SPE code onMPC5554 EVB @

56MHz (Cacheenabled)

SPE code onMPC5554 @128MHz

(Cache Enabled)

Code, Platform, and Enhancement

Tim

e

Application 1

Application 2

Application 3

Application 4

Application 5

Application 6

System Performance Improvements

This chart illustrates the integrated performance enhancements of the MPC5500 family by comparing the MPC5554 to the MPC563. The performance improvements shown are not simply due to the additional speed of the PowerPC Book E core. They are also the result of system improvements.

Notice that there is a significant performance improvement of code running on the MPC5554 with the SPE from the performance of the same code running on the MPC563. These system enhancements combine for actual tested performance improvements many times better than the MPC563. Please note that the MPC563 is currently used as a great solution for current complex real-time control applications in the automotive and industrial markets.

The system performance is improved due to several reasons, however three worth mentioning are: the eDMA, or the enhanced Direct Memory Access, the SPE, or Signal Processing Extension, and the added Cache memory. Click the “System Performance Improvements” button for details.

7

Slide 7

MPC5554 Performance

Boot Assist Module

Interrupt Controller

eDMA

External B

us Interface

ExternalMaster

Interface

3 x 5 Crossbar Switch

I/OBridge SIU

I/OBridge2M

FLASH

64KSRAM

(32K S/B)

NexusIEEE-ISTO 5001-2003

JTAGPowerPC

e200z6

32k CacheMMU

SIMD(DSP &

floating point)

DSPI

DSPI

DSPI

DSPI

eSCI

eSCI

FlexC

AN

FlexC

AN

FlexC

AN

AD

C

ADCiAD

C

3k DataRAM

16k CodeRAM

ETPU32

Channel

ETPU32

Channel

EMIOS24

ChannelAMux

• Crossbar enables simultaneous access from masters to peripherals

• Core to memory• DMA to I/O

• eDMA performs complex data transfers.• Scatter gather• Nested loops• Fast context switches

Platform architecture for optimized configurations of modular components:

• PowerPC 32-bit RISC processor.• 32 General Register• SIMD Signal Processing• Extensive tools support

• eTPU Processes input signals and generates output waveforms derived from programmable time bases

• Independently services interrupts• Offloads CPU processes (almost 70%

for some tasks)

Another system highlight includes a three by five crossbar, which allows three masters and five slaves to transfer data simultaneously.

The three masters include the eDMA itself, the core, and an external master via the external bus interface.

The core complex is connected to the rest of the system via the crossbar. The crossbar provides 64-bit wide data paths.

The eDMA will provide performance benefits in the following two cases: First during data transfers between peripherals and secondly during queuing of large quantities of data. So basically, the eDMA will move data that would otherwise be moved by a CPU interrupt handler. This interrupt handling is no longer needed with the addition of the eDMA.

There ARE separate paths to Flash and SRAM. The Flash has a two-line, 256-bit wide buffer driven by a local pre-fetch engine. This means that the core can now access program code from the on-chip flash concurrently. The eDMA performs complex data transfers which include scatter gather, nested loops and fast context switches.

The eTPU is another performance enhancing module. It processes input signals and generates output waveforms derived from programmable time bases which are independently serviced by interrupts which ultimately offload CPU processes. This will be discussed in more detail later in the course.

8

Slide 8

Advantages of Embedded Flash

Embedded Flash Off Chip Flash

Reduced Emissions for EMI ComplianceReduced Board Space and ComplexityFaster Access Rates

Radiated and Conducted emissions of Embedded Flash vs. Off Chip Flash

Some of the advantages of the embedded Flash include reduced EMI, reduced board space, and faster access

rates.

The MPC5500 family includes large arrays of embedded Flash. The MPC5554 includes 2Mbytes of Flash. The embedded flash features read while write capability and Error Correction Coding referred to as ECC. The embedded flash is high density floating-gate technology and is qualified at -40 to 125 degrees Celsius. There will be MPC5500 versions that are qualified down to -55 degrees Celsius. The Flash read operations are guaranteed down to three volts. An embedded hardware algorithm for program and erase is integrated on the Flash array. The on-chip SRAM also features ECC capability. Unified cache with line-locking is alsoon-chip as well as a Memory Management Unit, or MMU.

9

Slide 9

Question

Which of the following statements about the MPC5500 family are accurate? Select all that apply and then click Done.

a. The enhanced Direct Memory Access (eDMA) b. The Signal Processing Extension (SPE) c. The additional memory cached. The elimination of embedded Flash

Done


Correct.

Statements A, B, and C are true. Statement D is not true. The MPC5500 family includes large arrays of embedded Flash.

10

Slide 10

Embedded NVM Reliability Goals

0.35µFeb 2000

0.25µDec 2001

0.13µ2005

MPC555:100 P/E Cycles10 Years DR

MPC55xx:100,000 P/E Cycles

20 Years DR

Rel

iabi

lity

Technology:Qualification:

MPC56x:1,000 P/E Cycles

15 Years DR

This chart indicates Freescale’s technology advancements with respect to reliability goals of our Non-Volatile Memory or NVM. This shows Freescale’s Leadership, which includes successfully implementing sub-half micron floating gate flash since 1999; Freescale’s Knowledge, which includes over 500 engineering-years invested into development and improvement of automotive-grade embedded flash technology, and Freescale’s Experience, which includes over 33 million MCU’s shipped with sub .5 micron floating gate flash in the field.

The MPC5500 family will include the .13 micron process, which is qualified for up to 100,000 program and erase cycles, or with 20 years of data retention. Data retention for EEPROM emulation can be expected to be valid for one year from the last write. A technology certification vehicle was previously developed to qualify this Flash process before the MPC5500 family was developed. Aggressive stress conditions were used on the technology certification vehicle which has enabled manufacturing and design to verify and improve the reliability before a product was brought to market.

11

Slide 11

ECC in Flash for Automotive

• Freescale is applying Error Correction Coding (ECC) to the flashmemory to drive to a “ZERO” defect product for automotive

• ECC is implemented only to protect against random latent defects

• Technology Certification is based on the natural behavior of flash bit cells utilizing an uncorrected 4Mb Test Vehicle

• Qualification is based on the raw and uncorrected behavior of the flash array with ECC disabled

• ECC is not for “time zero” yield enhancement

Error Correction Coding, or ECC, is applied to drive zero defect product for strict automotive requirements. ECC is implemented to protect against latent defects.

The technology certification is based on the natural behavior of flash bit cells utilizing an uncorrected 4 Megabit Test Vehicle.

The qualification is based on the raw and uncorrected behavior of the flash array with ECC disabled, meaning that ECC is not used for yield enhancement, but solely for quality improvement to satisfy Freescale’s zero defect goal.

ECC is implemented on both embedded Flash and SRAM, while the cache has Parity. ECC cannot be implemented on external flash or SRAM. ECC is implemented with a standard Hamming code scheme, and has single-bit correction and double bit detection. So a single bit error correction will be transparent to the user, whereas a double-bit error will cause an exception and raise an interrupt. ECC is checked with reads and calculated on writes. This capability is great for safety-critical and higher reliability applications, and Freescale recommends the use of the ECC to protect Flash array contents.

12

Slide 12

RWW Partition

1

RWW Partition

0

64 KB

64 KB

128 KB

128 KB

128 KB

128 KB

RWW Partition

n

(128K blocks

added to meet

required flash size)

RWW Partition

2

Flash Blocks

(smallest erasable

units)

128 KB

128 KB

RWW Partition

348KB16KB

48KB16KB

16KB blocks ideal for EEPROM Emulation, 48K blocks for software boot code

MPC5500 Flash : Block and RWW Partitions

The MPC5500 family embedded flash array is organized into partitions and includes read-while-write capability.

An embedded hardware program and erase algorithm gives the user the ability to read one partition while writing to another. This allows a developer to write data to the small arrays while executing code from flash. Although a user can read-while-write with multiple partitions, one cannot read and write the same partition simultaneously.

Each partition has at least one pair of blocks. High-voltage and verify operations for program and erase are performed within a block pair. While programming or erasing a block, other blocks in that partition cannot be read; however, blocks from different, separate partitions can be read. Through an Erase suspend, program suspend, and erase-suspended program, access is provided to a block when another block is being erased in the same partition.

EEPROM emulation is allowed on partition zero. It can be used as a scratch pad, if you will. It allows a smaller block in partition zero to store data. The EEPROM emulation is a variable linked record scheme and allows storage of variable-size EEPROM data elements in the Flash.

13

The eTPU, as discussed before, stands for enhanced Time Processing Unit. These are real-time complex controllers operating independent of the CPU. In a way, an eTPU is a second on-chip processor. The eTPU is an upgrade of the original TPU that was featured on the previous two generations of product families: the MPC500 and 68K Families.

There are several reasons why an eTPU is needed and why it is integrated into Freescale’sdevices.

The number one constraint in microcontrollers today is the limited ability to perform high-speed, time-related tasks.

This constraint is due to CPU interrupt overhead, servicing timers, and other peripherals. Some applications are known to use more than 70% of the CPU time to perform these tasks.

The eTPU gives you the flexibility of a second microprocessor on board to take care of this real-time programming, or lower-level device driven applications.

The eTPU is dedicated to the handling of complex control, I/O, and timing algorithms, while the main CPU is free to handle other higher level tasks.

Since the eTPU was designed for the complex I/O management required in automotive engines, it can handle the most demanding timing applications.

Slide 13

Why do I need an eTPU?

The Challenge: • The number one constraint of microcontrollers is their limited ability to perform

high speed time related tasks.• Limited by CPU interrupt overhead in servicing timers and other peripherals.• Some applications may use more than 70% of CPU time to perform these tasks.• The flexibility of the microcontroller has been severely limited by the fixed

functionality and number of timer pins.

The Solution: • The eTPU is dedicated to handling complex control, I/O, and timing algorithms• MCU is free to handle other tasks, allowing for more system throughput and

increased system performance• Since it was designed for the complex I/O management required in automotive

engines, it can handle even the most demanding timing applications

eTPeTP

www.freescale.com/etpu

The eTPU (enhanced Time Processor Unit) is a programmable I/O controller with it’s own core and memory system, allowing it to perform complex timing and I/O management independently of the CPU.

The eTPU is essentially a microcontroller all by itself!

The eTPU is an upgrade of the original TPU featured on the MPC500 and 68K families.

14

Slide 14

What people are doing with the eTPU

Engine ControlSpark Timing, Fuel Injection

Serial CommunicationsUARTs, I2C, ARINC, Proprietary Protocols

Motor ControlFactory Automation, Robotics, Stepper Motor

Custom Logic ReplacementFPGAs and/or ASICs used for I/O


The eTPU is used for various functions.Many different serial communications can be emulated with the eTPU including UARTs, I2C, military protocols, or other proprietary protocols.

Motor control applications include factory automation, robotics, stepper motors, DC brushless motors, and many others.

Custom logic can take the place of FPGA’s or ASIC’s to reduce system costs.

The eTPU was designed specifically for engine control applications that require intense real-time control to manage camshaft positioning, spark timing, fuel injection and other various tasks.

The eTPU is completely programmable and users have the choice of just downloading and using Freescale’s prewritten library of functions or they can write their own custom applications in C. This makes the eTPU very user-friendly, which in turn enables customers to go from zero to production in record time.

15

Slide 15

User-friendly Features

Freescale provides a free library of eTPU functions including C Source Code, Host C API and detailed Application Notes. Please visit http://www.freescale.com/etpu

Customers may customize library functions and/or develop custom functions using the Byte Craft C Compiler and ASH WARE Simulator

- eTPU Functional LibraryeTPeTP

ACIM V/Hz ControlQuadrature Decoder &

CommutatorSPI

PMSM Vector Control

Hall Sensor Decode Using Angle Mode

UART

Synchronized PWM

ACIM Vector ControlCurrent ControlGeneral Purpose

I/O

Motor Control PWMMotor Control PWM

Queued Output Match

Analog SensingAnalog SensingAngle PulseStepper Motor

Hall Sensor Decode

Hall Sensor DecodeSpark ControlPulse/ Period

Accumulate

Quadrature DecodeQuadrature DecodeFuel Control

Pulse & Frequency

Measurement

DC Bus Break Control

DC Bus Break ControlCam DecodeOutput Compare

Motor Speed Control

Motor Speed ControlAngle ClockInput Capture

Set 1 FunctionsSet 1 FunctionsSet 1 FunctionsPulse Width Modulation

Set 4AC Motors

Set 3DC Motors

Set 2Automotive

Set 1General

eTPU Functions Library

BLDC with QD Speed & Current Loop

BLDC with QD Speed Loop

PMSM Vector Control with Speed LoopBLDC with QD Open Loop

PMSM Torque Vector ControlBLDC with HD Speed & Current Loop

ACIM Vector Control with Speed LoopBLDC with HD Speed Loop

ACIM Torque Vector ControlBLCD with HD Open Loop

ACIM V/Hz Speed Loop with SVM DriveDC Speed & Current Loop

ACIM V/Hz Speed Loop with Sine Wave DriveDC Speed Loop with HD

ACIM V/Hz Open Loop with SVM DriveDC Speed Loop with QD

ACIM V/Hz Open Loop with Sine Wave DriveDC Open Loop

Set 4Set 3

Electric Motors and Controls Supported

The eTPU is user-friendly in that users have the choice of downloading and using Freescale’s prewritten library of functions or writing their own custom applications in C. This enables rapid development of extra serial interfaces or motor applications, because there is no need to write custom code for specific operations like UARTs, SPI’s, DC or AC motor applications.

Freescale provides four general sets of libraries of pre-written functions, which are downloadable for free at www.freescale.com/etpu. Each set includes source code and detailed application notes.

Set 1 includes most serial communication needs.

Set 2 is specific to automotive type applications, complete with an angle clock function.

Set 3 provides code for DC motors applications.

Set 4 includes code for several AC motor needs.

Sets 3 and 4 support specific electric motors and controls, as shown.

16

Slide 16

eTPU UART Performance Example

eTPU Performance with UART function:• If no other function is running on the eTPU• 830k baud with 37.5MHz eTPU• 1.45M baud with 66MHz eTPU• Each UART can run at any baud rate• A separate eTPU channel is required for each transmit and receive signal.

• Example • 37.5MHz eTPU (150MHz MCF523x)

8 UARTs, 7 at 115k baud (tx and rx) and 1 at 19.2k baud (tx and rx) - (16 channels used)8 UARTs (tx and rx) at 103k baud (16 channels used)

• 66MHz eTPU (132MHz MPC5500)16 UARTs, 12 at 115k baud(tx and rx), 3 at 19.2k and 1 at 9600 baud (32 channels used)8 UARTs (tx and rx) at 181k baud (16 channels used)

• Performance scales with frequency, maximum MCF523x CPU clock = 150MHz (37.5MHz eTPU clock)

• The UART function requires 64 bytes of Data memory per UART used, and 504 bytes of Code memory (independent of the number of UARTs used).

Timer

Channels

Scheduler

Micro-

engine

HostInterface

andData

Memory

CodeMemory

Debug


This example illustrates the eTPU’s capability to function as several UARTs.

Each UART function requires two channels of the eTPU: one for transmission and one for reception. The eTPU UART function running on the MPC5500 family, operating no other functions on the eTPU, can run at 1.45 Mega baud. The performance will scale with the clock frequency.

The eTPU on the MPC5500 family runs at 66MHz or half the system clock of the 132MHz version.

The UART function requires 64 bytes of data memory per UART used and 504 bytes of code memory regardless of the number of UARTs implemented. This function is available at www.freescale.com/etpu

17

Slide 17

Question

Which of the following statements about the eTPU are accurate? Select all that apply and then click Done.

a. The eTPU gives you the flexibility of a second microprocessor to handle real-time programming.

b. The eTPU is dedicated to the handling of complex control, I/O and timing algorithms, while the main CPU is free to handle other higher level tasks.

c. The eTPU can be used for various functions, including serial communications, motor control, custom logic replacement, and engine control applications.

d. The eTPU can handle demanding timing applications by leveraging its strengths in handling the complex I/O management required in automotive engines.

Done


Correct. All of these statements are true. Click the forward arrow to continue on to the next page.]

18

Slide 18

MPC5500 Timed IO

Host-Interface

IP Interface

µEngine

Scheduler

32 Double Action Channels

PLM/MUXPins

TCR1TCR2

Angle Clock

Shar

ed T

ime/

Ang

le B

us

Shared Parameter RAM (3K)Shared Code (12K) Memory

Link to other modules

Host-Interface

IP Interface

µEngine

Scheduler

32 Double Action Channels

PLM/MUXPinsPins

TCR1TCR2

Angle Clock

Shar

ed T

ime/

Ang

le B

us

Shared Parameter RAM (3K)Shared Code (12K) Memory

Link to other modules

eTPUeTPU•Flexible implementation of complex timing thru RISC microengine•Powerful angle clock hardware, simplifies angle domain scheduling.•New instructions enable more sophisticated timing functions, anduse of C compiler.•Nexus Class 3 debug•Shared Time/Angle bus for synchronizing eMIOS functions.•eDMA support

IP b

us

Bus interface

UnitUnified

channel_0

Unified channel_1

Red C

Unified channel_2

ClockPrescaler

SysClock

A

B

MTS_0 O/PMTS_0 I/P

MTS_1 O/PMTS_1 I/P

MTS_2 O/PMTS_2 I/P

Unified channel_15

MTS_15 O/PMTS_15 I/P

O/P disable [0:3]

IP b

usIP

bus

Bus interface

Unit

Bus interface

UnitUnified

channel_0Unified

channel_0

Unified channel_1

Unified channel_1

Red CRed C

Unified channel_2

Unified channel_2

ClockPrescaler

ClockPrescaler

SysClock

A

B

MTS_0 O/PMTS_0 I/P

MTS_1 O/PMTS_1 I/P

MTS_2 O/PMTS_2 I/P

Unified channel_15

Unified channel_15

MTS_15 O/PMTS_15 I/P

O/P disable [0:3]

eMIOSeMIOS•2 x 24-bit wide counter buses•Shared Time/Angle bus for synchronizing eTPU functions.•24 unified channels that all support dual input capture, output compare, modulus counter and high speed PWM•Pulse or edge accumulation and counting•Windowed Programmable Time Accumulation•Interrupt request vector per channel •eDMA Support

The eTPU is essentially a second processor capable of handling complex real-time I/O control. It includes angle clock hardware, simplifying angle domain scheduling new instructions enabling more sophisticated timing functions and use of a C compiler.

Nexus Class 3 debug mode support a shared time angle bus for synchronizing eMIOSfunctions, and is fully supported by the eDMA allowing efficient transfers of data, without CPU involvement.

The eMIOS, which stands for enhanced Modular I/O System, has a number of features.It is 24 bits wide and includes two 24-bit wide counter buses. There is a shared time angle bus for synchronizing with eTPU functions.

Its 24 independent channels support functions such as dual input capture, output capture, modulus counter, and high-speed pulse width modulation. It also supports pulse or edge accumulation and counting, and window programmable time accumulation. This allows a user to configure a window of data and measure the time a pulse is high or a pulse is low, rather than simply counting the transitions.

The eMIOS also features interrupt request vector per channel, and eDMA support.

19

Slide 19

MPC5500 Serial Comms

FlexCANFlexCAN eSCIeSCI DSPIDSPI

• FlexCAN module fully compatible with TouCAN(MPC5xx family)

• ISO compliant • Message buffer extended

to 64 per CAN module• Software Bus-off recovery

option• Message buffer size

configurable at application

MPC5500 Rx Queue Tx Queue

DMA Controller

SCITxpush

Rx pull

DMA request

DMA request

Shift Reg

TX

RX

SRAMFlash or

SRAM

• MPC5500 SCI + DMA emulates QSCI

• Programmable 8-bit or 9-bit data format

• Programmable parity• 10 / 13 bit break signal• Separately enabled

transmitter and receiver• Interrupt-driven operation

with eight flags• 2 channel DMA interface• LIN support

MPC5500 Rx Queue Tx Queue Cmd Queue

DMA Controller

Flash or SRAM

DSPI

SRAM

Txfifo

Rx fifo

DMA request

DMA request

Shift Reg

Flash or SRAM

SOUTSIN

• MPC5500 DSPI + DMA emulates QSPI

• Master and Slave mode• 64-width external demultiplexer• eDMA support• SPI, DSI, CSI• Command options per frame

• Clock Rate (up to fSys/4)• 4 to 16 bit size• 6 Chip Selects

Continuous CS• LSB or MSB first

Some of the other serial communications include the FlexCAN, the eSCI, and the DSPI.

FlexCAN is Freescale’s next generation implementation of the standard Controller Area Network protocol that complies with the CAN 2.0b specification.

FlexCAN implements full ISO compliant CAN with added enhancements. Each FlexCANmodule features 64 message buffers, programmable I/O modes, maskable interrupts, programmable loop-back for self-test operation, and software bus off recovery option, and Message buffer size that is configurable at application. The CAN protocol is implemented independent of the transmission medium assuming an external transceiver is available. CAN is an open network architecture, it is a multi-master concept, and it is designed for harsh environments. There is short latency time for high-priority messages and it features a low-power sleep mode with a programmable wake up on bus activity.

The eSCI, or enhanced Serial Communications Interfaces, is feature-rich. It includes full duplex operation, standard non-return-to-zero format, 13-bit baud rate selection, and programmable eight-bit or nine-bit data formats programmable parity, 10/13 bit break signals separately enabled transmitter and receiver, and interrupt-driven operation with eight flags.

Other features include a two channel DMA interface and LIN support. The DSPI, which stands for Deserialization Serialization Peripheral Interface, is a high-speed, full duplex, three wire synchronous interface with many features. Master and slave modes are supported.

There are six peripheral chip selects which are expandable to a 64-width external demultiplexerand it includes de-glitching support of up to 32 chip selects when the external multiplexer is used. The DSPI with the eDMA has an unlimited message buffer queue which means that the user is able fill up the SRAM.

Three DSPI configurations are available including Serial Peripheral Interface, S-P-I, DeserialSerial Interface, D-S-I, or Combined Serial Interface, C-S-I. These modes enable GPIO expansion.

20

Slide 20

MPC5500 ADC

Features Continued:Features Continued:•Active clamps for current injection (biased towards >5V)

•Differential conversion capability on channel pairs (new feature)

• Variable sample rates 2 to 128 clocks

• Output right justified unsigned or left justified signed (NOTE: no left justified unsigned)

• Conversion time stamp

• Flexible trigger/scan modes

• Pause feature

• Results directly into system RAM or ETPU parameter RAM

• Status snap-shot

• 6 queues

• ETPU or EMIOS internal triggering

• Four 8x1 external MUX support

• Seamless integration for additional off-board ADC(s)

System RAM

DM

A

Queue 0Command ResultCommand Result

Command ResultCommand Result











6

System RAM

DM

A















Queue 0Command ResultCommand ResultCommand ResultCommand Result

Command ResultCommand ResultCommand ResultCommand Result





















6

66

6

Nextcommand

Lastresult

On-chip ADCs2:2 or40x1 Mux

2:2 or40x1 Mux

40

+

-ADC1

+

-ADC0

Commanddecode, comms& ADC control

On-chip ADCsOn-chip ADCs2:2 or40x1 Mux

2:2 or40x1 Mux

40

+

-ADC1

+

-

+

-ADC1

+

-ADC0

+

-

+

-ADC0

Commanddecode, comms& ADC control

Pins

ETPU

MIO

S

S/W

Triggers

Pins

ETPU

MIO

S

S/W

Triggers

Command Buffers

Queue 0

Queue 1

Queue 2

Queue 3

Queue 4

Queue 5

Command Buffers

Queue 0

Queue 1

Queue 2

Queue 3

Queue 4

Queue 5

Prio

rity

66

ADCi

Results Buffers

Queue 0

Queue 1

Queue 2

Queue 3

Queue 4

Queue 5

Results Buffers

Queue 0

Queue 1

Queue 2

Queue 3

Queue 4

Queue 5Off-chip deviceOff-chip deviceMux +

-+-

Commanddecode, comms

& controlSerial port

Features:Features:•Two converters

•Up to 40 shared channels via internal mux

•12-bit resolution

•At 400ks/s, 10 bit accuracy

•Maximum 800ks/s, 8 bits accurate

•0 to 5V conversion range (per MPC565)

The MPC5500 family A to D converter capabilities feature two modules totaling 40 channels with 12-bit resolution and 10-bit accuracy at 400 kilo samples. Conversion time will approach 1.25 micro seconds with lower resolutions. Each of the 40 channels are available to either of the two modules. The single ended signal ranges from zero to five volts.

There are 4 differential analog input channels.Sampling times of 2, 8, 64, or 128 ADC clock cycles can be implemented

The data can be obtained in right-justified signed and unsigned result formatsand a time stamp of the information can be taken, if requested

Six independent trigger sources are available which feature both single and continuous-scan mode.

The continuous mode does not require software involvement to re-arm the queue. The trigger sources include two external pins, six eMIOS pins and six eTPU channels.

The ADC features analog channel expansion capabilities that support 4 external 8-to-1 multiplexes which can expand the input channel number from 40 to 68. There is also a built-in migration path to future external ADCs which would use the same command structure and same queues as the internal conversions. A full duplex synchronous interface to an external device is available as well.

21 1

Slide 21

Nexus Support Classes

Class 1

Class 2

Class 3

– All class 3 features– Start data or program traces upon watchpoint occurrence– Program execution from Nexus port (not supported on MPC5500)

•substitutes instructions and data in memory

– Enter a debug mode from reset or user code– Read/ write user registers or memory in debug mode– Single step instructions in user mode and reenter debug mode– Ability to set breakpoints or watchpoints– Stop program execution on instruction/ data breakpoint and enter debug mode (minimum 2 breakpoints)– Device identification

– All class 1 features– Monitor process ownership while process runs in real- time (Ownership trace)– Trace program flow in real time

– All class 2 features– Trace data reads & writes while processor runs in real- time– Read/ write memory locations while processor runs in real-time

MP

C55

00 S

uppo

rts

Class 4

MP

C56

x/53

x S

uppo

rts

Program Trace Msgs

Data Trace Msgs

Memory Substitution

Port Replacement

Static Debugr / w regs. & mem.start/stop processorhw / sw breakpoints

Watchpoint Msg

Read / Write Access

Ownership Trace Msg

Nexus

The MPC5500 family has implemented the use of the Nexus debug interface and support. There are four support classes.

Class 1 features the following: the ability to enter a debug mode from reset or user code, read/write user registers or memory in debug mode, the ability to allow a user to single-step instructions in user mode and reenter debug mode, the ability to set break points or watch points,stop program execution or instruction data point break to enter debug mode, and device identification

Class 2 includes all of the features of class 1, plus monitor process ownership while programs run in real time, and trace program flow in real-time.

Class 3 includes all of the features of class 1 and 2, plus trace data reads and writes while the processor runs in real-time, and read or rewrite of memory locations while a process runs in real-time.

While the MPC500 family supports classes 1, 2, and 3, the MPC5500 family features all that plus a part of Class four operations Class 4 includes all of the features of classes 1, 2, and 3, plus the ability to start data and program traces upon watch point occurrences.

22

Slide 22

MPC

56x

MPC

56x

MPC

5500

MPC

5500

RCPURCPURCPU TPU3TPU3TPU3MIOS14MIOS14MIOS14 QSPIQSPIQSPI QSCIQSCIQSCI TouCANTouCANTouCAN

e200z6e200z6e200z6 ETPUETPUETPUEMIOSEMIOSEMIOS DSPIDSPIDSPI SCISCISCI FlexCANFlexCANFlexCAN

QADC64QADC64QADC64

ADCADCADC

Int ContIntInt ContCont

Int ContIntInt ContCont

•All Features

Supported

•All Features

Supported

•13-bit break for

LIN support

•13-bit break for

LIN support

•DMA Support Added


MPC5xx/55xx Compatibility and Enhancements

•Integer IS Compatible•Integer IS Compatible

•SIMD APU for DSP and Floating

Point

•SIMD APU for DSP and Floating

Point

•MMU Supporting

Memory Re-location

•MMU Supporting

Memory Re-location

•Integrated Cache

•Integrated Cache

•Same register concept

•Same register concept

•Same basic

feature set

•Same basic

feature set

•Single unified channel Utilized

•Single unified channel Utilized

•Timebaseincreased to 24bit

•Timebaseincreased to 24bit

•All Features

Supported

•All Features

Supported



•CS With Strobe Signal

•CS With Strobe Signal

•All Features

Supported

•All Features

Supported

•Enhanced to 64

message buffers

•Enhanced to 64

message buffers

•No Code changes required

(header file only)

•No Code changes required

(header file only)

EnhancementEnhancement

CompatibleCompatible

Key

•Up to 512 sources

•Up to 512 sources

•Unique Vector for

Core

•Unique Vector for

Core

•Oak Mode Compatible•Oak Mode Compatible

•16 Prog’ Priority Levels

•16 Prog’ Priority Levels

•8 SW Settable interrupt sources

•8 SW Settable interrupt sources

•All Features

Supported

•All Features

Supported

•7 levels of priority queues

•7 levels of priority queues

•Unlimited Queuing in

SRAM

•Unlimited Queuing in

SRAM



•1.25uS Conversion

•1.25uS Conversion

• 5V Input• 5V Input

•TPU instructions have ETPU equivalent

•TPU instructions have ETPU equivalent

•Architecture compatibility•Architecture compatibility

•Increased number of channels

•Increased number of channels

•C-Compiler and Nexus

Support

•C-Compiler and Nexus

Support

•Timebaseincreased to

24bit

•Timebaseincreased to

24bit

•Angle Clock •Angle Clock

This diagram demonstrates the features, compatibility, and enhancements that were added to the MPC5500 family when compared to the MPC500 family.

As far as the core is concerned, integer compatibility still exists, but there is also a SIMD unit, which includes DSP and floating point features. There is also an MMU supporting memory re-location, and integrated cache, which has been added. As far as the floating point comparison is concerned, the 5500 features 32 pairs of single precision floating point registers. These are shared with integer units. Execution unit is scalar or vector, but single precision, whereas on the 500 family it was only scalar and double precision.

The MIOS is upgraded to the eMIOS on the MPC5500 family. The MPC5500 still has the same register concept, the same basic feature set, but single unified channel is added and increased the eMIOS to 24 bits.

The QSPI was upgraded to the DSPI, so all the QSPI features are supported, but there is also a chip select with a strobe signal and DMA support on the DSPI.

As far as the QSCI, all previous features are supported, but on the 5500 family, you now have 13-bit break for LIN support, and again, DMA support to improve performance.

As far as the CAN modules are concerned, all features are supported that were supported on the 500 family. There are no code changes required, so you just need a new header file. The CAN module has been enhanced to 64 message buffers.

The analog to digital converter was also improved. The five volt input remains, but unlimited queuing in the SRAM has been added due to the DMA support. There are levels of priority queues. There is 12-bit resolution now, rather than ten, and there are up to 800 kilo samples per second.

The TPU was improved to the enhanced Time Processing Unit, which is also featured on some of Freescale’sother ColdFire parts. The eTPU is extremely easy to use and we encourage development with the pre-built library functions or through customized code which can be developed with the ByteCraft C compiler. All the previous TPU instructions have an eTPU equivalent function. The architecture is compatible, but the number of channels has been increased from 16 to 32 on each eTPU module. The time base has been increased to 24-bit and there is Nexus support for the eTPU. There is also an angle clock functionality, which is valuable for engine control applications.

As far as interrupt controllers, all the MPC500 modes are compatible, but there are up to 512 sources now. There is unique vector for core, 16 programmable priority levels, and eight software-settable interrupt sources.

23

Slide 23

MPC5554 / MPC5553

SIMD PowerPC MMUe200z6

32KU-Cache

2MFlash

64KSRAM

GPI/O JTAG NEXUS

ExternalBus

32 CheTPU

19KSRAM

32 CheTPU

24 cheMIOS

64 chDMA

2x 40chADC

4 DSPI3 CAN

2 eSCI

SIMD PowerPC MMUe200z6

8KU-Cache

1.5MFlash

64KSRAM

GPI/O JTAG NEXUS

ExternalBus

24 cheMIOS

32 chDMA

2x 40chADC

3 DSPI2 CAN

2 eSCI

32 CheTPU

14.5KSRAM

Ethernet

2Mbyte RWW Flash with ECC32k unified-cache (with line locking)

1.5Mbyte RWW Flash with ECC

8k unified-cache (with line locking)

64k SRAM (including 32K with standby) with ECC

Memory

PowerPC e200x6 Core

eTPU

I/O

System

MPC5554 Features: MPC5553 Features:Common Features:

MPC5554 MPC5553

Module

For more information, roll your mouse pointer over any of the

five modules below.

Here is the block diagram for the MPC5554 and the MPC5553, which are the first two products launched in for the MPC5500 Family.

As you can see, both devices feature the e200z6 Power PC Core, which includes the new SIMD module, sometimes referred to as the Signal Processing Extension, or SPE, for DSP and floating point capabilities. A memory management unit is also featured. The core is a 32-bit synthesized, Power PC book e processor. The SIMD, or SPE, can do basic DSP and arithmetic functionality, including logic, compares, and register shifts. Again, the floating point capability was added for DSP algorithms and embedded operations as well as Kalmanfilters. The MPC5554 and MPC5553 devices will be offered in 80 and 132MHz versions. The MPC5554 and MPC5553 will be completely pin compatible in the 416 pin PBGA. This is a 27 millimeter package and Freescale will offer the full range of MPC5500 devices in this package. The 416 pin PBGA will be a standard pin-for-pin compatible platform for the family. As the family proliferates the same compatibility can be assumed which includes not only packaging but also binary code, memory mapping, voltages, and other areas.

There is up to two megs of embedded Flash memory, featuring ECC and Read-While-Write capabilities. There is 64K of SRAM with ECC and up to 32K of unified cache with line-locking.

The MPC5554 features two eTPU modules, which is 64 channels. 32 channels per eTPU. The eTPU has a dedicated of SRAM. The MPC5554 has 19 and the MPC5553 has 14.5 kilobytes.

The MPC5554 has three CAN modules, four DSPI modules, two ESCI units, two A to D modules that include 40 orthogonal channels, 24 channels of eMIOS, and a 64 channel eDMA, whereas the MPC5553 features two CAN modules, three DSPI, and a 32 channel eDMA.

Nexus debug support is featured for advanced debug capabilities. Both devices feature a FMPLL that can be enabled to significantly reduce EMI through modulation.

Roll your mouse pointer over any of the five modules for more details.

24

Slide 24

MPC5554 / MPC5553

2Mbyte RWW Flash with ECC

2 x 32 I/O channels19k designated SRAM (16k code &

3k parameters)

3 x CAN - 64 buffers each

4 x DSPI 16 bits wide up to 6 chip selects each

64 Channel DMA Controller

300 Source Interrupt Controller

416 PBGA package (40 ADC)


MPC5554 Features:

1.5Mbyte RWW Flash with ECC

1 x 32 I/O channels14.5k designated SRAM (16k

code & 3k parameters)

2 x CAN - 64 buffers each

3 x DSPI 16 bits wide up to 6 chip selects each


200 Source Interrupt Controller324 PBGA package (36 ADC)416 PBGA package (40 ADC, Ethernet)


24 channel EMIOS with unified channels

2 x eSCI

40 channel dual ADC - up to 12 bit and up to 1.25µs conversions, 6 queues with triggering and DMA support.

FM-PLLNexus IEEE-ISTO 5001-2003 Class 3+MPC500 compatible External Bus Interface 5/3.3V IO, 5V ADC, 3.3V/1.8V bus, 1.5V core Temperature Range: -40 to 125ºC

MPC5553 Features:Common Features:

64k SRAM (including 32K with standby) with ECC

PowerPC ISA e200z6 Core with SIMD 80 or 132MHz - New SIMD (SPE) module for

DSP and floating point features

System

I/O

eTPU

Memory

PowerPC e200x6 Core

This slide is for reference for the preceding screen.

25

Slide 25

Question

Categorize each of the following ten attributes as belonging to either the MPC5554 or MPC5553. Click each of the attributes shown below and drag it to the correct column. Click “Done” when you are finished.

Done

MPC5554 MPC5553

2 Mbyte RWW Flash with ECC

1.5 Mbyte RWW Flash with ECC

8k unified-cache

32k unified-cache

1 x 32ch eTPU

2 x 32ch eTPU

3 x CAN

2 x CAN




26

Slide 26

MPC5500 Tools Support

Stacks Drivers

Translators

CompilerSimulatorDebugger

RTOS

Eval BoardsRef Designs

GNUGNU

MPC5554DEMO$750

MPC5553DEMO$750

eTPUTools

Initialization Tools

CCompiler

$2495

SimulatorDebugger

$1850Free

As far as tool support, MPC5500 will be widely supported throughout the industry.

Again, it was developed on the success of the MPC500 family, which was supported by many of the vendors shown here. EVB’s will be priced $750 and sold directly from the Freescale websites. The EVB’s will include a “MPC5554/MPC5553 Revealed” book that provides a great introduction to the MPC5554 and MPC5553 architecture and programming.

As far as operating system support, Green Hills, Metrowerks, ARC, and others will provide solutions.

Compilers, simulators, and debuggers are provided through Lauterbach, GreenHills, Metrowerks, Ashling, and many others.

Stacks and drivers, including CAN and Ethernet, are available from companies such as Ixxat, ARC, Green Hills, and Accelerated Technologies.

There are also eTPU tools, as discussed earlier, which include the C compiler, available by Bytecraft, and an eTPU simulator and debugger available from ASHWARE. ASHWARE also offers classes specific to the eTPU. And finally UnisProcessor Expert allows easy graphical configuration during initial setup of your development stage. This is free.

There are also detailed, hands-on training classes available. More information can be found on our Freescale website under the MPC5500 product pages.

27

Slide 27

eTPU Web Page

http://www.freescale.com/etpu

OTHER INFORMATION SOURCESMPC500 Family Discussion Group

Yahoo! MPC500 User Grouphttp://groups.yahoo.com/group/mot-mpc500-apps/

eTPU microcode releases and documentation is available on the eTPU webpage

The eTPU web page is a great resource for pertinent information. This is where one can find the complete set of functions available in the functional library and download each of the 4 function sets for free. Most all of these sets are complete, with a few to be completed by the end of 2005. Another addition tool will be developed in the future. This will allow a user to pick and choose specific functions, rather than having to load the entire function set into memory. This can save memory, especially if any custom coding is required. Other sources of information are the MPC500 family discussion group on Yahoo. We plan on expanding this with the MPC5500 family.

28

Slide 28

BOOKS AVAILABLEMPC5554/MPC5553; eTPU Programming; Nexus Debug

http://www.amtpublishing.com

http://www.freescale.com....

http://www.ashware.com

“Nexus Revealed”

Presents an overview of the Nexus debug standard, including the specific implementation on the MPC56x, the MPC55xx, and the MAC71xx Families.

Written by Randy Dees, Freescale 32-bit Automotive Applications and Co-chair of the Hardware Technical Subcommittee of the Nexus Consortium

"MPC5554 Revealed“

Offers system designers, university professors, and students a complete understanding of the first member of a new microcontroller family based on the Book E PowerPC architecture. This book introduces the reader to the MPC5554 and provides details of the functionality of its on-chip modules and some of its targeted applications in automotive and industrial environments.

“eTPU Programming Made Easy“

Provides readers with a complete understanding of eTPU Programming catering to almost all backgrounds and learning styles. Part I of the book focuses on eTPU programming and provides a problem-based approach to this programming. Part II provides a detailed technical explanation on all aspects of the eTPU. The accompanying CD-ROM contains everything needed to complete a small programming project.

Roll your mouse pointer over each book for a summary.

When purchasing an Evaluation Board, the “MPC5554 Revealed” book will be included. The book offers users a complete understanding of the Book E PowerPC architecture and peripherals. It also effectively introduces the MPC5500 family.

Other notable books include “eTPU Programming Made Easy” and “Nexus Revealed.”

These books are available through AMT Publishing and via a link on the Freescale website. These books, and other books of similar interest, are also available through ASHWARE.

Roll your mouse pointer over each book for a summary.

29

Slide 29

Question

True or false? Users have the choice of downloading Freescale’s free libraries of eTPU functions.

a. Trueb. False

Done


Correct. This statement is true. Users can also write their own custom applications in C.

30

Slide 30Freescale Semiconductor Confidential Proprietary. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004

Summary

• The target markets and roadmap of the MPC5500 family

• Performance characteristics

• The reasons for using an eTPU

• Comparisons of the MPC5554 and MPC5553

• Support tools

This course covered the MPC5500 family by providing details on the first two releases in that family: the MPC5554 and the MPC5553.

This course covered MPC5500, the newest generation of Freescale’s PowerPC 32-bit microcontrollers, by providing details on the first two devices in that family: the MPC5554 and the MPC5553. Specifically, the course covered the target markets and roadmap of the MPC5500family, performance characteristics, the reasons for using an eTPU, comparisons of the MPC5554 and MPC5553, and the support tools that are available.

f3 mpc5500 print - nxp semiconductors...56f8300 hybrid series 56f800 hybrid series mid 56f800 hybrid...

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