Ez-Gate (Gateway)

Gateway of Sensor Networks

Yongjin KimCASP Lab. Hanyang Univ.yjkim@casp.hanyang.ac.kr

Contents

Ez-Gate Features주요 Component의 Spec.Ez-Gate Schematics

Ez-Gate Features

Ez-Gate Block Diagram

PXA255(Intel ARM Processor)

Flash ROM(Boot, NAND)

SDRAM& Buffer

JTAG Wall Node

전원(5 V Adapter & USB)

Serial Interface

Board Debugging

EthernetController

컴퓨터와 통신RS232 & USB

Oscillator(32.768KHz3.6864MHz)

Oscillator20MHz

Internet 연결

Ez-Gate

Ez-Gate Board 구성

1

2

34

5

6

7

8

9

108

87

3

11

10

10

1. PXA 255 ARM Processor

2. Clock for Operation of PXA 255

3. CPLD & CPLD JTAG Port

4. Boot Flash (512KB)

& Back-Side NAND Flash (64MB)

5. SDRAM & Back-Side more one

(SDRAM *2) (4MB*16bit*4bank*2)

6. USB Port

7. COM Port & Driver

8. Ethernet Port & Driver, Clock

9. JTAG Port for Programming

10. Regulator (5v 3v, 3v 1.3v),

Adaptor, Power Switch

11. Serial Interface (Connect Wall Node)

& Driver

주요 Component의 Spec.

PXA 255 Block Diagram

PXA 255 Micro-Architecture Features• ARM Architecture Version 5TE ISA compliant.

— ARM Thumb Instruction Support— ARM DSP Enhanced Instructions

• Low power consumption and high performance• Intel® Media Processing Technology

— Enhanced 16-bit Multiply— 40-bit Accumulator

• 32-KByte Instruction Cache• 32-KByte Data Cache• 2-KByte Mini Data Cache• 2-KByte Mini Instruction Cache• Instruction and Data Memory Management Units• Branch Target Buffer• Debug Capability via JTAG Port

System Integration Features

• Memory Controller• Clock and Power Controllers• Universal Serial Bus Client• DMA Controller• LCD Controller• AC97• I2S• MultiMediaCard

• FIR Communication• Synchronous Serial Protocol Port• I2C• General Purpose I/O pins• UARTs• Real-Time Clock• OS Timers• Pulse Width Modulation• Interrupt Control

Boot Flash(AM29LV400B) Block Diagram

AM29LV400B Features4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0

Volt-only Boot Sector Flash MemorySingle power supply operation

— Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications

— Regulated voltage range: 3.0 to 3.6 volt read and write operations for compatibility with high performance 3.3 volt microprocessors

High performance— Full voltage range: access times as fast as 70 ns— Regulated voltage range: access times as fast as 55 ns

Ultra low power consumption (typical values at 5 MHz)

— 200 nA Automatic Sleep mode current— 200 nA standby mode current— 7 mA read current— 15 mA program/erase current

Unlock Bypass Program Command— Reduces overall programming time when issuing multiple

program command sequences

Embedded Algorithms— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any combination of designated sectors

— Embedded Program algorithm automatically writes and verifies data at specified addresses

Data# Polling and toggle bits— Provides a software method of detecting program or

erase operation completion

Ready/Busy# pin (RY/BY#)— Provides a hardware method of detecting program or

erase cycle completion

Erase Suspend/Erase Resume— Suspends an erase operation to read data from, or

program data to, a sector that is not being erased, then resumes the erase operation

Hardware reset pin (RESET#)— Hardware method to reset the device to reading array

data

NAND Flash(K9F1208U0A) Block Diagram

K9F1208U0A Features64M x 8 Bit NAND Flash Memory

· Voltage Supply : 2.7V~3.6V · Organization

- Memory Cell Array : (64M + 2,048K)bit x 8bit- Data Register : (512 + 16)bit x8bit multipled by four

planes

· Automatic Program and Erase- Page Program : (512 + 16)Byte- Block Erase : (16K + 512)Byte

· 528-Byte Page Read Operation- Random Access : 12ms(Max.)- Serial Page Access : 50ns(Min.)

· Fast Write Cycle Time- Program time : 200ms(Typ.)

- Block Erase Time : 2ms(Typ.)

· Command/Address/Data Multiplexed I/O Port

· Hardware Data Protection- Program/Erase Lockout During Power Transitions

· Reliable CMOS Floating-Gate Technology- Endurance : 100K Program/Erase Cycles

- Data Retention : 10 Years

· Command Register Operation

· Intelligent Copy-Back Operation

SDRAM(K4S561632) Block Diagram

K4S561632 Features

K4S561632E-TC(L)60/75 16M x 16 166MHz (CL=3)• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system clock.

• Burst read single-bit write operation

• DQM (x4,x8) & L(U)DQM (x16) for masking

• Auto & self refresh

• 64ms refresh period (8K Cycle)

CPLD(XC9536XL) Block Diagram

XC9536XL Features• 4 ns pin-to-pin logic delays• System frequency up to 200 MHz• 36 macrocells with 800 usable gates• Optimized for high-performance 3.3V systems

- Low power operation- 5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V

signals- 3.3V or 2.5V output capability- Advanced 0.35 micron feature size CMOS

FastFLASH™ technology

• Advanced system features- In-system programmable- Superior pin-locking and routability with

FastCONNECT II™ switch matrix- Extra wide 54-input Function Blocks- Up to 90 product-terms per macrocell with

individual product-term allocation- Local clock inversion with three global and one

product-term clocks

- Individual output enable per output pin

- Input hysteresis on all user and boundary-scan pin inputs

- Bus-hold circuitry on all user pin inputs

- Full IEEE Standard 1149.1 boundary-scan (JTAG)

• Fast concurrent programming

• Slew rate control on individual outputs

• Enhanced data security features

• Excellent quality and reliability- Endurance exceeding 10,000 program/erase cycles

- 20 year data retention

- ESD protection exceeding 2,000V

Ethernet Controller(CS8900A) Block Diagram

CS8900A FeaturesSingle-Chip IEEE 802.3 Ethernet Controller with Direct ISA-Bus InterfaceMaximum Current Consumption = 55mA (5V Supply)3 V OperationIndustrial Temperature RangeComprehensive Suite of Software Drivers AvailableEfficient PacketPage™ Architecture

Operates in I/O and Memory Space, and as DMA SlaveFull Duplex OperationOn-Chip RAM Buffers Transmit and Receive Frames10BASE-T Port with Analog Filters, Provides:

— Automatic Polarity Detection and Correction

AUI Port for 10BASE2, 10BASE5 and 10BASE-F

Programmable Transmit Features:— Automatic Re-transmission on Collision

— Automatic Padding and CRC Generation

Programmable Receive Features:— Stream Transfer™ for Reduced CPU Overhead

— Auto-Switch Between DMA and On-Chip Memory

— Early Interrupts for Frame Pre-Processing

— Automatic Rejection of Erroneous Packets

EEPROM Support for JumperlessConfiguration

Boot PROM Support for Diskless Systems

Boundary Scan and Loopback Test

LED Drivers for Link Status and LAN Activity

Standby and Suspend Sleep Modes

Ez-Gate Schematics

Ez-Gate 구성도

PXA 255

BootFlash

NANDFlash

SDRAM

CPLD

MAX241

Buffer 1

Buffer 2

Buffer 3

HC125

10 Pin

20 P

in JT

AG

6 Pin JTAG

USB

Adapter

SW

5v-3.3v

3.3v-1.3v

Sipex DA 9

RJ45

CS8900A

ST7011

전체 구성도 (Ez-Gate & Wall Node)

PXA 255

BootFlash

NANDFlash

SDRAM

CPLD

MAX241

Buffer 1

Buffer 2

Buffer 3

HC125

10 Pin

20 P

in JT

AG

6 Pin JTAG

USB

Adapter

SW

5v-3.3v

3.3v-1.3v

Sipex DA 9

RJ45

CS8900A

ST7011