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ExpressLane PEX 8648-AA, AB, and BB48-Lane/12-Port PCI Express Gen 2 SwitchData Book

Version 1.3

June 2012

Website www.plxtech.com

Technical Support www.plxtech.com/support

Phone 800 759-3735

408 774-9060

FAX 408 774-2169

Copyright © 2012 by PLX Technology, Inc. All Rights Reserved – Version 1.3June, 2012

http://www.plxtech.comhttp://www.plxtech.com/support/

Data Book PLX Technology, Inc.

Copyright Information

Copyright © 2009 – 2012 PLX Technology, Inc. All Rights Reserved. The information in this documentis proprietary and confidential to PLX Technology. No part of this document may be reproduced in anyform or by any means or used to make any derivative work (such as translation, transformation, or

Revision History

Version Date Description of Changes

1.0 February, 2009Production release, Silicon Revision BB.Support for pre-Production Silicon Revisions AA and AB is also included.

1.1 September, 2009Production update, Silicon Revision BB. Applied miscellaneous corrections, changes, and enhancements throughout data book.

1.2 October, 2010

Production update, Silicon Revision BB.Added support for Industrial temperature.Updated PEX 8648 part ordering information.Applied miscellaneous corrections, changes, and enhancements throughout data book.

1.3 June, 2012

Production update, Silicon Revision BB.Updated the thermal matrix table.Updated the ordering part number.Applied miscellaneous corrections, changes, and enhancements throughout data book.

adaptation) without written permission from PLX Technology.

PLX Technology provides this documentation without warranty, term or condition of any kind, eitherexpress or implied, including, but not limited to, express and implied warranties of merchantability,fitness for a particular purpose, and non-infringement. While the information contained herein isbelieved to be accurate, such information is preliminary, and no representations or warranties ofaccuracy or completeness are made. In no event will PLX Technology be liable for damages arisingdirectly or indirectly from any use of or reliance upon the information contained in this document.PLX Technology may make improvements or changes in the product(s) and/or the program(s) describedin this documentation at any time.

PLX Technology retains the right to make changes to this product at any time, without notice.Products may have minor variations to this publication, known as errata. PLX Technology assumes noliability whatsoever, including infringement of any patent or copyright, for sale and useof PLX Technology products.

PLX Technology and the PLX logo are registered trademarks and Dual Cast, ExpressLane,performancePAK, Read Pacing, and visionPAK are trademarks of PLX Technology, Inc.

PCI Express is a trademark of the PCI Special Interest Group (PCI-SIG).

EUI-64 is a trademark of The Institute of Electrical and Electronics Engineers, Inc. (IEEE).

Tri-State is a registered trademark of Texas Instruments, Inc.

All product names are trademarks, registered trademarks, or service marks of their respective owners.

Document Number: 8648-AA/AB/BB-SIL-DB-P1-1.3

ExpressLane PEX 8648-AA, AB, and BB 48-Lane/12-Port PCI Express Gen 2 Switch Data Book, Version 1.3ii Copyright © 2012 by PLX Technology, Inc. All Rights Reserved

June, 2012 Preface

Preface

The information in this data book is subject to change without notice. This PLX data book to be updatedperiodically as new information is made available.

Audience

This data book provides functional details of PLX Technology’s ExpressLane PEX 8648-AA, AB, andBB 48-Lane/12-Port PCI Express Gen 2 Switch, for hardware designers and software/firmwareengineers. The information provided pertains to all Silicon Revisions (AA, AB, and BB), unlessspecified otherwise.

Supplemental Documentation

This data book assumes that the reader is familiar with the following documents:

• PLX Technology, Inc. (PLX), www.plxtech.com

The PLX PEX 8648 Toolbox includes this data book and other supporting documentation, such as errata, and design and application notes.

• The Institute of Electrical and Electronics Engineers, Inc. (IEEE), www.ieee.org

– IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture

– IEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture

– IEEE Standard 1149.1-1994, Specifications for Vendor-Specific Extensions

– IEEE Standard 1149.6-2003, IEEE Standard Test Access Port and Boundary-Scan Architecture Extensions

• NXP Semiconductors, ics.nxp.com

– The I2C-Bus Specification, Version 2.1

• PCI Special Interest Group (PCI-SIG), www.pcisig.com

– PCI Local Bus Specification, Revision 3.0

– PCI Bus Power Management Interface Specification, Revision 1.2

– PCI to PCI Bridge Architecture Specification, Revision 1.2

– PCI Express Base Specification, Revision 1.1

– PCI Express Base Specification, Revision 2.0

– PCI Express Base Specification, Revision 2.0 Errata

– PCI Express Card Electromechanical Specification, Revision 2.0

– PCI Express Mini Card Electromechanical Specification, Revision 1.1

– PCI Express Architecture PCI Express Jitter and BER White Paper, Revision 1.0

• Personal Computer Memory Card International Association (PCMCIA), www.pcmcia.org

– ExpressCard Standard Release 1.0

• PXI Systems Alliance (PXI), www.pxisa.org

– PXI-5 PXI Express Hardware Specification, Revision 1.0

ExpressLane PEX 8648-AA, AB, and BB 48-Lane/12-Port PCI Express Gen 2 Switch Data Book, Version 1.3Copyright © 2012 by PLX Technology, Inc. All Rights Reserved iii

http://www.plxtech.comhttp://www.ieee.org/http://ics.nxp.com/http://www.nxp.com/acrobat_download/literature/9398/39340011.pdfhttp://www.pcmcia.org/http://www.pcisig.com/http://www.pcisig.com/specifications/pciexpress/technical_library/PCIe_Rj_Dj_BER_R1_0.pdfhttp://www.pxisa.org/http://www.plxtech.com/products/expresslane/pex8648

Supplemental Documentation PLX Technology, Inc.

Note: In this data book, shortened titles are associated with the previously listed documents. The following table lists these abbreviations.

Abbreviation Document

PCI r3.0 PCI Local Bus Specification, Revision 3.0

PCI Power Mgmt. r1.2 PCI Bus Power Management Interface Specification, Revision 1.2

PCI-to-PCI Bridge r1.2 PCI to PCI Bridge Architecture Specification, Revision 1.2

PCI Express Base r1.1 PCI Express Base Specification, Revision 1.1

PCI Express Base r2.0 PCI Express Base Specification, Revision 2.0

PCI ExpressCard CEM r2.0 PCI Express Card Electromechanical Specification, Revision 2.0

PCI ExpressCard Mini CEM r1.1 PCI Express Mini Card Electromechanical Specification, Revision 1.1

IEEE Standard 1149.1-1990 IEEE Standard Test Access Port and Boundary-Scan Architecture

IEEE Standard 1149.6-2003IEEE Standard Test Access Port and Boundary-Scan Architecture Extensions

I2C Bus v2.1

I2C Bus v2.1a

a. Due to formatting limitations, the specification name may appear without the superscripted “2” in its title.

The I2C-Bus Specification, Version 2.1

ExpressLane PEX 8648-AA, AB, and BB 48-Lane/12-Port PCI Express Gen 2 Switch Data Book, Version 1.3iv Copyright © 2012 by PLX Technology, Inc. All Rights Reserved

June, 2012 Terms and Abbreviations

Terms and Abbreviations

The following table lists common terms and abbreviations used in this data book. Terms andabbreviations defined in the PCI Express Base r2.0 are not included in this table.

Terms and Abbreviations Definitions

8b/10bData-encoding scheme used on data transferred across a Link that is operating at either Gen 1 or Gen 2 Link speed (2.5 or 5.0 GT/s, respectively).

ACK Acknowledge Control Packet. Control packet used by a destination to acknowledge data packet receipt. Signal that acknowledges signal receipt.

AMCAMAddress-mapping CAM that determines a memory Request route. Contains mirror copies of the PCI-to-PCI bridge Memory Base and Memory Limit registers in the PEX 8648.

ARI Alternative Routing-ID Interpretation.

BAR Base Address register.

BER Bit error rate.

BusNoCAMBus Number-mapping CAM that determines the Completion route. Contains mirror copies of the PCI-to-PCI bridge Secondary Bus Number and Subordinate Bus Number registers in the PEX 8648.

CAM Content-Addressable Memory.

CDR Clock Data Recovery.

CRC Cyclic Redundancy Check.

CSR Configuration Space register.

DLL Data Link Layer.

DMA Direct Memory Access.

Downstream Station Station that contains only downstream Ports.

ECC Error-Correcting Code.

ECRC End-to-end Cyclic Redundancy Check.

EIOS Electrical Idle Ordered-Set.

EP Endpoint.

Field Multiple register bits that are combined for a single function.

FC Flow Control.

GPIO General-Purpose Input/Output.

GT/s Giga-Transfers per second.

INCH Ingress Credit Handler.

InitFC Initialization Flow Control.

IOCAMI/O-mapping CAM that determines an I/O Request route. Contains mirror copies of the PCI-to-PCI bridge I/O Base and I/O Limit registers in the PEX 8648.

JTAG Joint Test Action Group.

Lane Bidirectional pair of differential PCI Express I/O signals.

LCRC Link Cyclic Redundancy Check.

Link InterfacePrimary side of the NT Port, connects to external device pins. The secondary side of the NT Port is referred to as the NT Port Virtual Interface, and connects to the internal virtual PCI Express interface.

ExpressLane PEX 8648-AA, AB, and BB 48-Lane/12-Port PCI Express Gen 2 Switch Data Book, Version 1.3Copyright © 2012 by PLX Technology, Inc. All Rights Reserved v

Terms and Abbreviations PLX Technology, Inc.

LocalReference to PCI Express attributes (such as credits) that belong to the PCI Express Station.

LTSSM Link Training and Status State Machine.

LUT Lookup Table.

MRL Manually operated Retention Latch.

NAK Negative Acknowledge.

N_FTS Number of Fast Training Sequences field in Training Sets.

NTNon-Transparent. A bridging technique used in the PCI Express Switch to isolate Memory spaces by presenting the processor as an endpoint rather than another memory system. The PEX 8648 supports one NT Port.

PCI Express Station

Functional unit that provides the PCI Express conforming system interface. Includes the Serializer/De-Serializer (SerDes) hardware interface modules and PCI Express interface, which provides the Physical Layer (PHY), Data Link Layer (DLL), and Transaction Layer (TL) logic.

PEX PCI Express.

PHY Physical Layer.

PLL Phase-Locked Loop.

PM Power Management.

PME Power Management Event.

PortInterface to a group of SerDes and supporting logic that is capable of creating a Link, for communication with another Port.

P-P PCI-to-PCI.

PRBS Pseudo-Random Bit Sequence.

QoS Quality of Service.

RAS Reliability, Availability, and Serviceability.

RoHS Restrictions on the use of certain Hazardous Substances (RoHS) Directive.

RR Round-Robin scheduling.

Rx Receiver.

SerDesSerializer/De-Serializer. A high-speed differential-signaling parallel-to-serial and serial-to-parallel conversion logic attached to Lane pads.

SPI Serial Peripheral Interface.

Sticky bits

Register bits in which the current values are unchanged by a Hot Reset, Link Down event, or Secondary Bus Reset, while the PEX 8648 is powered. Sticky bits are reset to default values by a Fundamental Reset. Applies to ROS, RW1CS, and RWS CSR types, and sometimes HwInit. (Refer to Table 12-5, “Register Types, Grouped by User Accessibility,” for CSR type definitions.)

TC Traffic Class.

TCB Training Control Bit field in Training Sets.


ExpressLane PEX 8648-AA, AB, and BB 48-Lane/12-Port PCI Express Gen 2 Switch Data Book, Version 1.3vi Copyright © 2012 by PLX Technology, Inc. All Rights Reserved

June, 2012 Terms and Abbreviations

TL Transaction Layer.

TLCTransaction Layer Control. The module performing PCI Express Transaction Layer functions.

TLP Transaction Layer Packet. PCI Express packet formation and organization.

Transparent Refers to standard PCI Express upstream-to-downstream routing protocol.

TS1 Type 1 Training Sequence Ordered-Set.

TS2 Type 2 Training Sequence Ordered-Set.

Tx Transceiver.

UI Unit Interval – 400 ps at 2.5 GT/s, 200 ps at 5.0 GT/s.

Upstream Station Contains the component’s upstream Port. An upstream Station can also contain one or more downstream Ports.

UTP User Test Pattern.

VC Virtual Channel.

Vector Address and data.

Virtual Interface Secondary side of the NT Port, connects to the internal virtual PCI Express interface.

WRR Weighted Round-Robin scheduling.


ExpressLane PEX 8648-AA, AB, and BB 48-Lane/12-Port PCI Express Gen 2 Switch Data Book, Version 1.3Copyright © 2012 by PLX Technology, Inc. All Rights Reserved vii

Data Book Notations and Conventions PLX Technology, Inc.

Data Book Notations and Conventions

Notation / Convention Description

Blue text

Indicates that the text is hyperlinked to its description elsewhere in the data book. Left-click the blue text to learn more about the hyperlinked information. This format is often used for register names, register bit and field names, register offsets, chapter and section titles, figures, and tables.

PEX_XXXn[x]PEX_XXXp[x]

When the signal name appears in all CAPS, with the primary Port description listed first, field [x] indicates the number associated with the signal balls/pads assigned to a specific SerDes module/Lane. The lowercase “n” (negative) or “p” (positive) suffix indicates the differential pair of signals, which are always used together.

# = Active-Low signalsUnless specified otherwise, Active-Low signals are identified by a “#” appended to the term (for example, PEX_PERST#).

Program/code samplesMonospace font (program or code samples) is used to identify code samples or programming references. These code samples are case-sensitive, unless specified otherwise.

command_done Interrupt format.

Command/Status Register names.

Parity Error Detected Register parameter [bit or field] or control function.

Upper Base Address[31:16] Specific Function in 32-bit register bounded by bits [31:16].

Number multipliers

k = 1,000 (103) is generally used with frequency response.

K = 1,024 (210) is used for Memory size references.KB = 1,024 bytes.M = meg.

= 1,000,000 when referring to frequency (decimal notation)= 1,048,576 when referring to Memory sizes (binary notation)

255d d = Suffix that identifies decimal values.

1Fhh = Suffix that identifies hex values.Each prefix term is equivalent to a 4-bit binary value (Nibble).Legal prefix terms are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F.

1010bb = suffix which identifies binary notation (for example, 01b, 010b, 1010b, and so forth). Not used with single-digit values of 0 nor 1.

0 through 9 Decimal numbers, or single binary numbers.

byte Eight bits – abbreviated to “B” (for example, 4B = 4 bytes).

LSB Least-Significant Byte.

lsb Least-significant bit.

MSB Most-Significant Byte.

msb Most-significant bit.

DWord Double-Word (32 bits) is the primary register size in these devices.

QWord Quad-Word (64 bits).

Reserved Do not modify reserved bits and words. Unless specified otherwise, these bits read as 0 and must be written as 0.

word 16 bits.

ExpressLane PEX 8648-AA, AB, and BB 48-Lane/12-Port PCI Express Gen 2 Switch Data Book, Version 1.3viii Copyright © 2012 by PLX Technology, Inc. All Rights Reserved

Contents

Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Chapter 2 Features and Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.1 Flexible and Feature-Rich 48-Lane, 12-Port Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1.1 Highly Flexible Port Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.1.2 Non-Blocking Crossbar Switch Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.1.3 Low Packet Latency and High Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1.3.1 Data Payloads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.1.3.2 Cut-Thru Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1.4 Virtual Channel and Traffic Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.1.5 End-to-End Packet Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.1.6 Configuration Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1.7 Interoperability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1.8 Low Power with Granular SerDes Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1.9 Dynamic Lane Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1.10 performancePAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.10.1 Read Pacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1.10.2 Dual Cast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1.10.3 Dynamic Buffer Pool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.11 visionPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1.11.1 Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1.11.2 Error Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1.11.3 SerDes Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1.11.4 SerDes Eye Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1.12 Hot Plug for High Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.1.13 Fully Compliant Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.1.14 General-Purpose Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.1.15 PCI Express Switch Non-Transparent Bridging . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.2.1 Host-Centric Fan-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.2.2 Communications Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.2.3 Backplane Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.2.4 Failover Storage Systems with Dual Cast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3 Software Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.3.1 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.3.2 Interrupt Sources and Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chapter 3 Signal Ball Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.2 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.3 Internal Pull-Up/Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.4 Signal Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.4.1 PCI Express Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193.4.2 Hot Plug Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4.2.1 Parallel Hot Plug Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.4.2.2 Serial Hot Plug Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

ExpressLane PEX 8648-AA, AB, and BB 48-Lane/12-Port PCI Express Gen 2 Switch Data Book, Version 1.3Copyright © 2012 by PLX Technology, Inc. All Rights Reserved ix

Contents PLX Technology, Inc.

3.4.3 Serial EEPROM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.4.4 Strapping Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303.4.5 JTAG Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363.4.6 I2C Slave Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.4.7 Device-Specific Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383.4.8 External Resistor Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423.4.9 No Connect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433.4.10 Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.5 Physical Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Chapter 4 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .474.1 Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.1.1 Station and Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484.1.1.1 Port Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484.1.1.2 Port Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.2 PCI Express Station Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524.3 Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.3.1 Physical Layer Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534.3.2 Physical Layer Status and Command Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 544.3.3 Hardware Link Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.4 Transaction Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554.4.1 Locked Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574.4.2 Relaxed Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574.4.3 TL Transmit/Egress Protocol – End-to-End Cyclic Redundancy Check . . . . . . . . 574.4.4 TL Receive/Ingress Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584.4.5 Flow Control Credit Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584.4.6 Flow Control Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.5 PCI-Compatible Software Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Chapter 5 Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .615.1 Reset Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

5.1.1 Fundamental Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625.1.2 Hot Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625.1.3 Secondary Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625.1.4 Register Bits that Affect Hot Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625.1.5 Reset and Clock Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645.2.1 Default Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655.2.2 Default Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.2.2.1 Device-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655.2.3 Serial EEPROM Load Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665.2.4 I2C Load Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Chapter 6 Serial EEPROM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .676.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686.3 Serial EEPROM Load Following Upstream Port Reset . . . . . . . . . . . . . . . . . . . . . . . . 686.4 Serial EEPROM Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696.5 Serial EEPROM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726.6 PCI Express Configuration, Control, and Status Registers . . . . . . . . . . . . . . . . . . . . . 736.7 Serial EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

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6.8 Serial EEPROM Random Write/Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746.8.1 Writing to Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746.8.2 Reading from Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756.8.3 Programming a Blank Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6.9 Serial EEPROM Loading of NT Port Link Interface Registers . . . . . . . . . . . . . . . . . . . 766.10 NT Port Expansion ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Chapter 7 I2C Slave Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777.1 I2C Support Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777.2 I2C Addressing – Slave Mode Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787.3 I2C Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787.4 I2C Register Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

7.4.1 Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837.5 I2C Register Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

7.5.1 Register Read Address Phase and Command Packet . . . . . . . . . . . . . . . . . . . . . 887.5.2 Register Read Data Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Chapter 8 Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918.2 Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

8.2.1 Shared Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918.2.2 Unidirectional Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928.2.3 Ideal PCI Express Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948.2.4 Bidirectional PCI Express Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968.2.5 Read Completion Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

8.3 DLLP Policies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088.3.1 ACK DLLP Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088.3.2 UpdateFC DLLP Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108.3.3 Unidirectional DLLP Policies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

8.4 Ingress Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1138.4.1 Initial Credit Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148.4.2 Dynamic Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1158.4.3 Ingress Credit Handler Threshold Registers (Offsets A00h through A50h) . . . . 1188.4.4 Adjusting Initial Credit Values (Ingress Resources) . . . . . . . . . . . . . . . . . . . . . . 1198.4.5 Credit Allocation When Common Pool Is Consumed . . . . . . . . . . . . . . . . . . . . . 1208.4.6 INCH Port Pool Registers (Offset 940h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1228.4.7 Wait for ACK – Avoiding Congestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

8.5 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238.5.1 Host-Centric Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248.5.2 Peer-to-Peer Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258.5.3 Other Latency Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

8.6 Queuing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268.6.1 Destination Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1278.6.2 Source Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288.6.3 Port Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1298.6.4 Port Bandwidth Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

8.7 Read Pacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308.7.1 Read Pacing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1318.7.2 Read Spacing (Spreading) Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1338.7.3 Read Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1348.7.4 Read Pacing Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1348.7.5 Enabling Read Pacing and Read Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

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8.8 Using the Dual Cast Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368.8.2 Dual Cast System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1378.8.3 Dual Cast Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

8.8.3.1 Dual Cast Low BAR[0-7], Dual Cast High BAR[0-7] . . . . . . . . . . . . . . . . . . . 1388.8.3.2 Dual Cast Low BAR[0-7] Translation, Dual Cast

High BAR[0-7] Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1398.8.3.3 Dual Cast Low BAR[0-7] Setup, Dual Cast High BAR[0-7] Setup . . . . . . . . 1408.8.3.4 Dual Cast Source Destination Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

8.8.4 Dual Cast Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1448.8.4.1 Register Programming Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

8.8.5 Dual Cast to a Non-Transparent Destination Port . . . . . . . . . . . . . . . . . . . . . . . . 1448.8.6 Error Reporting of Failed Dual Cast Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Chapter 9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1459.1 Interrupt Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

9.1.1 Interrupt Sources or Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1469.1.2 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

9.2 INTx Emulation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1509.2.1 INTx-Type Interrupt Message Re-Mapping and Collapsing . . . . . . . . . . . . . . . . 151

9.3 MSI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1529.3.1 MSI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1529.3.2 MSI Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

9.4 PEX_INTA# Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1549.5 General-Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Chapter 10 Hot Plug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15710.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15710.2 Hot Plug Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15810.3 Hot Plug Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15910.4 Hot Plug Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

10.4.1 Hot Plug Port External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16010.4.2 Hot Plug Output States for Disabled Hot Plug Slots . . . . . . . . . . . . . . . . . . . . . 160

10.5 Hot Plug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16110.6 Hot Plug Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16110.7 Hot Plug Controller Slot Power-Up/Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . 162

10.7.1 Slot Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16210.7.1.1 Configuring Slot Power-Up Sequence Features with Serial EEPROM . . . 16310.7.1.2 Slot Power-Up Sequencing When Power Controller Present Bit Is Set . . . 16410.7.1.3 HP_PERST_x# (Reset) and HP_PWRLED_x# Output Power-Up

Sequencing When Power Controller Present Bit Is Cleared . . . . . . . . . . . . 16710.7.1.4 Disabling Power-Up Hot Plug Output Sequencing . . . . . . . . . . . . . . . . . . . 168

10.7.2 Slot Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16810.8 Serial Hot Plug Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

10.8.1 Hot Plug Operations by way of I2C I/O Expander . . . . . . . . . . . . . . . . . . . . . . . 17010.8.2 I2C I/O Expander Parts Selection and Pin Definition . . . . . . . . . . . . . . . . . . . . . 17010.8.3 Serial Hot Plug Port Enumeration and Assignment . . . . . . . . . . . . . . . . . . . . . . 172

10.9 Hot Plug Board Insertion and Removal Process . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

ExpressLane PEX 8648-AA, AB, and BB 48-Lane/12-Port PCI Express Gen 2 Switch Data Book, Version 1.3xii Copyright © 2012 by PLX Technology, Inc. All Rights Reserved

June, 2012 Contents

Chapter 11 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17911.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17911.2 Power Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18011.3 Power Management Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

11.3.1 Device Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18111.3.1.1 D0 Device Power Management State . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18111.3.1.2 D3hot Device Power Management State . . . . . . . . . . . . . . . . . . . . . . . . . . 181

11.3.2 Link Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18211.3.3 PCI Express Power Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

11.4 Power Management Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19311.5 Power Management Event Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

Chapter 12 Transparent Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19512.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19512.2 Type 1 Port Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19612.3 Port Register Configuration and Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19912.4 Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

12.4.1 PCI r3.0-Compatible Configuration Mechanism . . . . . . . . . . . . . . . . . . . . . . . . 20112.4.2 PCI Express Enhanced Configuration Access Mechanism . . . . . . . . . . . . . . . . 20212.4.3 Device-Specific Memory-Mapped Configuration Mechanism . . . . . . . . . . . . . . 203

12.5 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20512.6 PCI-Compatible Type 1 Configuration

Header Registers (Offsets 00h – 3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20612.7 PCI Power Management Capability Registers

(Offsets 40h – 44h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22312.8 MSI Capability Registers

(Offsets 48h – 64h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22612.9 PCI Express Capability Registers

(Offsets 68h – A0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23312.10 Subsystem ID and Subsystem Vendor ID

Capability Registers (Offsets A4h – FCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25812.11 Device Serial Number Extended Capability Registers

(Offsets 100h – 134h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25912.12 Power Budget Extended Capability Registers

(Offsets 138h – 144h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26112.13 Virtual Channel Extended Capability Registers

(Offsets 148h – 1BCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26412.13.1 Port Arbitration Table Registers

(Offsets 1A8h – 1BCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27012.14 Device-Specific Registers

(Offsets 1C0h – 51Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27512.14.1 Device-Specific Registers – Error Checking and Debug

(Offsets 1C0h – 1FCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27612.14.2 Device-Specific Registers – Physical Layer

(Offsets 200h – 25Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30912.14.3 Device-Specific Registers – Serial EEPROM

(Offsets 260h – 26Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35512.14.4 Device-Specific Registers – Physical Layer

(Offsets 270h – 28Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36212.14.5 Device-Specific Registers – I2C Slave Interface

(Offsets 290h – 2C4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36912.14.6 Device-Specific Registers – Bus Number CAM

(Offsets 2C8h – 304h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

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12.14.7 Device-Specific Registers – I/O CAM(Offsets 308h – 344h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

12.14.8 Device-Specific Registers – Address-Mapping CAM(Offsets 348h – 444h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

12.14.9 Device-Specific Registers – Vendor-Specific Dual CastExtended Capability (Offsets 448h – 51Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . 409

12.15 ACS Extended Capability Registers(Offsets 520h – 528h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

12.16 Device-Specific Registers(Offsets 54Ch – F8Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

12.16.1 Device-Specific Registers – Port Configuration(Offsets 574h – 628h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438

12.16.2 Device-Specific Registers – General-Purpose Input/Output(Offsets 62Ch – 65Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

12.16.3 Device-Specific Registers – Ingress Control and Port Enable(Offsets 660h – 67Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464

12.16.4 Device-Specific Registers – IOCAM Base and LimitUpper 16 Bits (Offsets 680h – 6BCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

12.16.5 Device-Specific Registers – Base Address Shadow(Offsets 6C0h – 73Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

12.16.6 Device-Specific Registers – Virtual Channel ResourceControl Shadow (Offsets 740h – 83Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

12.16.7 Device-Specific Registers – Ingress Credit Handler Port Pool(Offsets 940h – 94Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

12.16.8 Device-Specific Registers – Vendor-Specific ExtendedCapability 2 (Offsets 950h – 95Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513

12.16.9 Device-Specific Registers – ACS Extended Capability(Offsets 980h – 9FCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

12.16.10 Device-Specific Registers – Ingress Credit Handler Threshold(Offsets A00h – B7Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

12.16.11 Device-Specific Registers – SerDes Support(Offsets B80h – BFCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570

12.16.12 Device-Specific Registers – Port Configuration Header(Offsets E00h – E3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

12.16.13 Device-Specific Registers – Source Queue Weightand Soft Error (Offsets F00h – F30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624

12.16.14 Device-Specific Registers – Read Pacing(Offsets F34h – F3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

12.16.15 Device-Specific Registers – Error Reporting(Offsets F40h – F4Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

12.16.16 Device-Specific Registers – ARI Capability(Offsets F50h – F8Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

12.17 Advanced Error Reporting ExtendedCapability Registers (Offsets FB4h – FDCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645

Chapter 13 Non-Transparent Bridging – NT Mode Only . . . . . . . . . . . . . . . . . . . . . . . . . . . .65313.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653

13.1.1 Device Type Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65413.1.2 NT Port Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65413.1.3 Intelligent Adapter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65513.1.4 NT Port Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656

13.1.4.1 Fundamental Reset (PEX_PERST#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65613.1.4.2 Intelligent Adapter Mode NT Port Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 656

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13.1.5 NT Port Memory-Mapped Base Address Registers . . . . . . . . . . . . . . . . . . . . . 65613.1.6 Doorbell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65813.1.7 Scratchpad Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65913.1.8 NT Base Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

13.1.8.1 NT BARx Setup Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65913.1.9 Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661

13.1.9.1 Direct Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66213.2 Requester ID Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664

13.2.1 Transaction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66513.2.2 Transaction Originating in Local Host Domain . . . . . . . . . . . . . . . . . . . . . . . . . 66613.2.3 Transaction Originating in System Host Domain . . . . . . . . . . . . . . . . . . . . . . . 668

13.3 NT Port Power Management Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67013.3.1 Active State Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67013.3.2 PCI-PM and PME Turn Off Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67013.3.3 Message Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670

13.4 Expansion ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67013.5 NT Port Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671

13.5.1 NT Port Virtual Interface Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67113.5.2 NT Port Link Interface Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672

13.6 NT Port Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67313.7 Cursor Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67413.8 Port Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674

Chapter 14 NT Port Virtual Interface Registers – NT Mode Only. . . . . . . . . . . . . . . . . . . . . 67514.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67514.2 NT Port Virtual Interface Type 0 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67614.3 Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678

14.3.1 PCI Express Base r2.0 Configuration Mechanism . . . . . . . . . . . . . . . . . . . . . . 67814.3.1.1 PCI r3.0-Compatible Configuration Mechanism . . . . . . . . . . . . . . . . . . . . . 67814.3.1.2 PCI Express Enhanced Configuration Access Mechanism . . . . . . . . . . . . 679

14.3.2 Device-Specific Memory-Mapped Configuration Mechanism . . . . . . . . . . . . . . 68014.3.3 Device-Specific Cursor Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681

14.4 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68114.5 NT Port Virtual Interface PCI-Compatible Type 0

Configuration Header Registers (Offsets 00h – 3Ch) . . . . . . . . . . . . . . . . . . . . . . 68214.6 NT Port Virtual Interface PCI Power Management

Capability Registers (Offsets 40h – 44h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69214.7 NT Port Virtual Interface MSI Capability Registers

(Offsets 48h – 64h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69514.8 NT Port Virtual Interface PCI Express Capability

Registers (Offsets 68h – A0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69914.9 NT Port Virtual Interface Subsystem ID and

Subsystem Vendor ID Capability Registers(Offsets A4h – C4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709

14.10 NT Port Virtual Interface Vendor-SpecificCapability 3 Registers (Offsets C8h – FCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710

14.11 NT Port Virtual Interface Device Serial NumberExtended Capability Registers (Offsets 100h – 134h) . . . . . . . . . . . . . . . . . . . . . . 717

14.12 NT Port Virtual Interface Virtual Channel ExtendedCapability Registers (Offsets 148h – 1A4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718

14.13 NT Port Virtual Interface Port ArbitrationTable Registers (Offsets 1A8h – 1BCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722

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14.14 NT Port Virtual Interface Device-Specific Registers(Offsets 1C0h – C88h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727

14.14.1 NT Port Virtual Interface Device-Specific Registers –Error Checking and Debug (Offsets 1C0h – 1FCh) . . . . . . . . . . . . . . . . . . . . . 730

14.14.2 NT Port Virtual Interface Device-Specific Registers –Ingress Control and Port Enable (Offsets 660h – 67Ch) . . . . . . . . . . . . . . . . . 733

14.14.3 NT Port Virtual Interface Device-Specific Registers –Vendor-Specific Extended Capability 2 (Offsets 950h – 95Ch) . . . . . . . . . . . . 735

14.14.4 NT Port Virtual Interface Device-Specific Registers –Vendor-Specific Extended Capability 4 (Offsets C34h – C88h) . . . . . . . . . . . 736

14.15 NT Port Virtual Interface NT Bridging-SpecificRegisters (Offsets C8Ch – F30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745

14.15.1 NT Port Virtual Interface NT Bridging-Specific Registers –Base Address and Base Address Setup (Offsets D68h – D90h) . . . . . . . . . . 746

14.15.2 NT Port Virtual Interface NT Bridging-Specific Registers –Requester ID Translation Lookup Table Entry (Addresses D94h – DB0h) . . . 757

14.16 NT Port Virtual Interface Device-Specific Registers(Offsets F34h – F8Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759

14.16.1 NT Port Virtual Interface Device-Specific Registers –ARI Capability (Offsets F50h – F8Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760

14.17 NT Port Virtual Interface Advanced Error ReportingExtended Capability Registers (Offsets FB4h – FDCh) . . . . . . . . . . . . . . . . . . . . . 767

14.18 NT Port Virtual Interface Device-Specific Registers –Link Error (Offsets FE0h – FFCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773

Chapter 15 NT Port Link Interface Registers – NT Mode Only . . . . . . . . . . . . . . . . . . . . . . .77515.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77515.2 NT Port Link Interface Type 0 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77615.3 Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778

15.3.1 PCI Express Base r2.0 Configuration Mechanism . . . . . . . . . . . . . . . . . . . . . . 77815.3.1.1 PCI r3.0-Compatible Configuration Mechanism . . . . . . . . . . . . . . . . . . . . . 77815.3.1.2 PCI Express Enhanced Configuration Access Mechanism . . . . . . . . . . . . 778

15.3.2 Device-Specific Memory-Mapped Configuration Mechanism . . . . . . . . . . . . . . 78015.3.3 Device-Specific Cursor Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781

15.4 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78115.5 NT Port Link Interface PCI-Compatible Type 0

Configuration Header Registers (Offsets 00h – 3Ch) . . . . . . . . . . . . . . . . . . . . . . 78215.6 NT Port Link Interface PCI Power Management

Capability Registers (Offsets 40h – 44h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79215.7 NT Port Link Interface MSI Capability Registers

(Offsets 48h – 64h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79515.8 NT Port Link Interface PCI Express Capability

Registers (Offsets 68h – A0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79915.9 NT Port Link Interface Subsystem ID and

Subsystem Vendor ID Capability Registers(Offsets A4h – C4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809

15.10 NT Port Link Interface Vendor-Specific Capability 3Registers (Offsets C8h – FCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

15.11 NT Port Link Interface Device Serial Number ExtendedCapability Registers (Offsets 100h – 134h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816

15.12 NT Port Link Interface Power Budget ExtendedCapability Registers (Offsets 138h – 144h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816

15.13 NT Port Link Interface Virtual Channel ExtendedCapability Registers (Offsets 148h – 1A4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817

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June, 2012 Contents

15.14 NT Port Link Interface Device-Specific Registers(Offsets 1C0h – C88h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820

15.14.1 NT Port Link Interface Device-Specific Registers –Error Checking and Debug (Offsets 1C0h – 1FCh) . . . . . . . . . . . . . . . . . . . . 821

15.14.2 NT Port Link Interface Device-Specific Registers –Ingress Control and Port Enable (Offsets 660h – 67Ch) . . . . . . . . . . . . . . . . . 824

15.14.3 NT Port Link Interface Device-Specific Registers –Vendor-Specific Extended Capability 2 (Offsets 950h – 95Ch) . . . . . . . . . . . 825

15.14.4 NT Port Link Interface Device-Specific Registers –Vendor-Specific Extended Capability 4 (Offsets C34h – C88h) . . . . . . . . . . . 826

15.15 NT Port Link Interface NT Bridging-Specific Registers(Offsets C8Ch – EFCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828

15.15.1 NT Port Link Interface NT Bridging-Specific Registers –Requester ID Translation Lookup Table Entry(Addresses DB4h – DF0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828

15.16 NT Port Link Interface Device-Specific Registers –Source Queue Weight (Offsets F00h – F30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830

15.17 NT Port Link Interface Advanced Error ReportingExtended Capability Registers (Offsets FB4h – FDCh) . . . . . . . . . . . . . . . . . . . . . 831

Chapter 16 Test and Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83316.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83316.2 Physical Layer Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834

16.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83416.2.2 Analog Loopback Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83516.2.3 Digital Loopback Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83716.2.4 Analog Loopback Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83816.2.5 Digital Loopback Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838

16.3 Using the SerDes Quad x Diagnostic Data Registers . . . . . . . . . . . . . . . . . . . . . . . 83916.4 Pseudo-Random and Bit-Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84016.5 PHY Testability Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84216.6 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844

16.6.1 IEEE 1149.1 and IEEE 1149.6 Test Access Port . . . . . . . . . . . . . . . . . . . . . . . 84416.6.2 JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84516.6.3 JTAG Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84616.6.4 JTAG Reset Input – JTAG_TRST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846

16.7 Port Good Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847

Chapter 17 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84917.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84917.2 Power-Up/Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84917.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84917.4 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84917.5 Power Consumption Estimates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85017.6 I/O Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85117.7 Transmit Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861

17.7.1 Default Transmit Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87217.8 Receive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873

17.8.1 Receive Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87317.8.2 Receiver Electrical Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874

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Chapter 18 Thermal and Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87518.1 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875

18.1.1 Sample Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87618.2 General Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87818.3 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879

Appendix A General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .881A.1 Product Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881A.2 United States and International Representatives and Distributors . . . . . . . . . . . . . . 882A.3 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882

ExpressLane PEX 8648-AA, AB, and BB 48-Lane/12-Port PCI Express Gen 2 Switch Data Book, Version 1.3xviii Copyright © 2012 by PLX Technology, Inc. All Rights Reserved

Registers

Transparent Port Registers

PCI-Compatible Type 1 ConfigurationHeader Registers (Offsets 00h – 3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

12-1. 00h PCI Configuration ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20612-2. 04h PCI Command/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20712-3. 08h PCI Class Code and Revision ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21012-4. 0Ch Miscellaneous Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21112-5. 10h Base Address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21212-6. 14h Base Address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21312-7. 18h Bus Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21312-8. 1Ch Secondary Status, I/O Limit, and I/O Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21412-9. 20h Memory Base and Limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21612-10. 24h Prefetchable Memory Base and Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21712-11. 28h Prefetchable Memory Upper Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21812-12. 2Ch Prefetchable Memory Upper Limit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21812-13. 30h I/O Upper Base and Limit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21912-14. 34h Capability Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21912-15. 38h Expansion ROM Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21912-16. 3Ch Bridge Control and PCI Interrupt Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

PCI Power Management Capability Registers(Offsets 40h – 44h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

12-17. 40h PCI Power Management Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22312-18. 44h PCI Power Management Status and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

MSI Capability Registers(Offsets 48h – 64h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

12-19. 48h MSI Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22712-20. 4Ch MSI Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22812-21. 50h MSI Upper Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22812-22. 54h MSI Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22812-23. 58h MSI Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22912-24. 5Ch MSI Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231

PCI Express Capability Registers(Offsets 68h – A0h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

12-25. 68h PCI Express Capability List and Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23412-26. 6Ch Device Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23512-27. 70h Device Status and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23712-28. 74h Link Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23912-29. 78h Link Status and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24312-30. 7Ch Slot Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24612-31. 80h Slot Status and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25012-32. 8Ch Device Capability 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25612-33. 90h Device Status and Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25612-34. 98h Link Status and Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

Subsystem ID and Subsystem Vendor IDCapability Registers (Offsets A4h – FCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

12-35. A4h Subsystem Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25812-36. A8h Subsystem ID and Subsystem Vendor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258

ExpressLane PEX 8648-AA, AB, and BB 48-Lane/12-Port PCI Express Gen 2 Switch Data Book, Version 1.3Copyright © 2012 by PLX Technology, Inc. All Rights Reserved xix

Registers PLX Technology, Inc.

Device Serial Number Extended Capability Registers(Offsets 100h – 134h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

12-37. 100h Device Serial Number Extended Capability Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25912-38. 104h Serial Number (Lower DW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26012-39. 108h Serial Number (Upper DW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Power Budget Extended Capability Registers(Offsets 138h – 144h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

12-40. 138h Power Budget Extended Capability Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26112-41. 13Ch Data Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26212-42. 140h Power Budget Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26212-43. 144h Power Budget Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Virtual Channel Extended Capability Registers(Offsets 148h – 1BCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

12-44. 148h Virtual Channel Extended Capability Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26412-45. 14Ch Port VC Capability 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26512-46. 150h Port VC Capability 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26512-47. 154h Port VC Status and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26612-48. 158h VC0 Resource Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26712-49. 15Ch VC0 Resource Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26812-50. 160h VC0 Resource Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

Port Arbitration Table Registers(Offsets 1A8h – 1BCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

12-51. 1A8h Port Arbitration Table Phases 0 to 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27112-52. 1ACh Port Arbitration Table Phases 8 to 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27212-53. 1B0h Port Arbitration Table Phases 16 to 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27312-54. 1B4h Port Arbitration Table Phases 24 to 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

Device-Specific Registers(Offsets 1C0h – 51Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

Device-Specific Registers – Error Checking and Debug(Offsets 1C0h – 1FCh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

12-55. 1C0h Device-Specific Error Status for Egress ECC Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27712-56. 1C4h Device-Specific Error Mask for Egress ECC Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28112-57. 1C8h ECC Error Check Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28512-58. 1CCh Error Handler 32-Bit Error Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28712-59. 1D0h Error Handler 32-Bit Error Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28912-60. 1D8h Clock Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29112-61. 1DCh Debug Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29412-62. 1E0h Power Management Hot Plug User Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30112-63. 1E8h Bad TLP Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30412-64. 1ECh Bad DLLP Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30412-65. 1F4h Station 0/1 Lane Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30512-66. 1F8h ACK Transmission Latency Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Device-Specific Registers – Physical Layer(Offsets 200h – 25Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

12-67. 200h Physical Layer Receiver Detect Status and Electrical Idle for Compliance Mask. . . . . . 31112-68. 204h Electrical Idle Detect/Receiver Detect Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31712-69. 210h Physical Layer User Test Pattern, Bytes 0 through 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 32112-70. 214h Physical Layer User Test Pattern, Bytes 4 through 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 32112-71. 218h Physical Layer User Test Pattern, Bytes 8 through 11 . . . . . . . . . . . . . . . . . . . . . . . . . . 32212-72. 21Ch Physical Layer User Test Pattern, Bytes 12 through 15 . . . . . . . . . . . . . . . . . . . . . . . . . 32212-73. 220h Physical Layer Command and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32312-74. 228h Physical Layer Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

ExpressLane PEX 8648-AA, AB, and BB 48-Lane/12-Port PCI Express Gen 2 Switch Data Book, Version 1.3xx Copyright © 2012 by PLX Technology, Inc. All Rights Reserved

June, 2012 Registers

12-75. 230h Physical Layer Port Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33112-76. 234h SKIP Ordered-Set Interval and Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33512-77. 238h SerDes Quad 0 Diagnostic Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34112-78. 23Ch SerDes Quad 1 Diagnostic Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34212-79. 240h SerDes Quad 2 Diagnostic Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34312-80. 244h SerDes Quad 3 Diagnostic Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34412-81. 248h Port Receiver Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34612-82. 24Ch Target Link Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34712-83. 254h Physical Layer Additional Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34912-84. 258h PRBS Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351

Device-Specific Registers – Serial EEPROM(Offsets 260h – 26Ch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

12-85. 260h Serial EEPROM Status and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35612-86. 264h Serial EEPROM Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35912-87. 268h Serial EEPROM Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36012-88. 26Ch Serial EEPROM 3rd Address Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361

Device-Specific Registers – Physical Layer(Offsets 270h – 28Ch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

12-89. 270h Station 2 Software Lane Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36212-90. 274h Station 0/1 Lane Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36412-91. 278h Station 2 Lane Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367

Device-Specific Registers – I2C Slave Interface(Offsets 290h – 2C4h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

12-92. 294h I2C Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369

Device-Specific Registers – Bus Number CAM(Offsets 2C8h – 304h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370

12-93. 2C8h BusNoCAM0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37112-94. 2CCh BusNoCAM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37112-95. 2D0h BusNoCAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37112-96. 2D4h BusNoCAM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37212-97. 2D8h BusNoCAM4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37212-98. 2DCh BusNoCAM5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37212-99. 2E0h BusNoCAM6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37312-100. 2E4h BusNoCAM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37312-101. 2E8h BusNoCAM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37412-102. 2ECh BusNoCAM9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37412-103. 2F0h BusNoCAM10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37512-104. 2F4h BusNoCAM11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375

Device-Specific Registers – I/O CAM(Offsets 308h – 344h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

12-105. 308h IOCAM0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37712-106. 30Ah IOCAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37712-107. 30Ch IOCAM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37812-108. 30Eh IOCAM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37812-109. 310h IOCAM4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37912-110. 312h IOCAM5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37912-111. 314h IOCAM6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38012-112. 316h IOCAM7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38012-113. 318h IOCAM8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38112-114. 31Ah IOCAM9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38112-115. 31Ch IOCAM10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38212-116. 31Eh IOCAM11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382

ExpressLane PEX 8648-AA, AB, and BB 48-Lane/12-Port PCI Express Gen 2 Switch Data Book, Version 1.3Copyright © 2012 by PLX Technology, Inc. All Rights Reserved xxi

Registers PLX Technology, Inc.

Device-Specific Registers – Address-Mapping CAM(Offsets 348h – 444h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383

12-117. 348h AMCAM0 Memory Base and Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38512-118. 34Ch AMCAM0 Prefetchable Memory Base and Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38512-119. 350h AMCAM0 Prefetchable Memory Base Upper 32 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . 38612-120. 354h AMCAM0 Prefetchable Memory Limit Upper 32 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . 38612-121. 358h AMCAM1 Memory Base and Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38712-122. 35Ch AMCAM1 Prefetchable Memory Base and Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38712-123. 360h AMCAM1 Prefetchable Memory Base Upper 32 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . 38812-124. 364h AMCAM1 Prefetchable Memory Limit Upper 32 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . 38812-125. 368h AMCAM2 Memory Base and Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38912-126. 36Ch AMCAM2 Prefetchable Memory Base and Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38912-127. 370h AMCAM2 Prefetchable Memory Base Upper 32 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . 39012-128. 374h AMCAM2 Prefetchable Memory Limit Upper 32 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . 39012-129. 378h AMCAM3 Memory Base and Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39112-130. 37Ch AMCAM3 Prefetchable Memory Base and Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39112-131. 380h AMCAM3 Prefetchable Memory Base Upper 32 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . 39212-132. 384h AMCAM3 Prefetchable Memory Upper Limit Address . . . . . . . . . . . . . . . . . . . . . . . . . 39212-133. 388h AMCAM4 Memory Base and Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39312-134. 38Ch AMCAM4 Prefetchable Memory Base and Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39312-135. 390h AMCAM4 Prefetchable Memory Base Upper 32 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . 39412-136. 394h AMCAM4 Prefetchable Memory Limit Upper 32 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . 39412-137. 398h AMCAM5 Memory Base and Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39512-138. 39Ch AMCAM5 Prefetchable Memory Base and Limit . .

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