export/supplier content/vicor-1102... · 2012-08-16 · picor corpo 8 descrip the pi33xx range dc...
TRANSCRIPT
Picor Corpo
8
DescripThe PI33XX
range DC
controller,
all within a
integration
Switching
increases p
class powe
external in
complete D
Dev
PI3311‐
PI3312‐
PI3301‐
PI3302‐
PI3303‐
PI3305‐
Table 1 ‐ PI3
higher 18A c
and Vout >1
The Zero
enables hi
switching
switching f
external
density, an
line and lo
high switc
input volta
its 20ns m
conversion
I2C is a trade
ration • picorpo
8V to 36
ption X is a family o
C‐DC ZVS‐Bu
power switch
a high density
n of a high
(ZVS) topolog
point of load p
er efficiency. T
nductor and m
DC‐DC switchin
vice Ou
Set
‐X0‐LGIZ 1.0V
‐X0‐LGIZ 2.5V
‐X0‐LGIZ 3.3V
‐X0‐LGIZ 5.0V
‐X0‐LGIZ 12V
‐X0‐LGIZ 15V
33XX Portfolio. A
current, output
15.
Voltage Switc
igh frequency
losses and ma
frequency ope
filtering com
nd enables ve
oad transients
hing frequency
age without sa
inimum on‐tim
ns up to 36Vin.
mark of NXP Semico
ower.com
6Vin Coo
of high efficien
uck regulator
hes, and suppo
System‐in‐Pac
performance
gy, within the
performance p
The PI33XX re
minimal capaci
ng mode buck
utput Voltage
t Range
V 1.00 to 1.4
V 2.0 to 3.1
V 2.3 to 4.1
V 3.3 to 6.5
V 6.5 to 13.0
V 10.0 to 16.0
Additional versio
voltages (Vout)
ching (ZVS) ar
operation wh
aximizing effici
ration reduces
mponents, im
ery fast dynam
s. The PI33XX
y all the way u
acrificing effici
me, supports la
nductors
PI33XX‐X0‐LGIZ
ol‐Power
ncy, wide inpu
rs integratin
ort component
ckage (SiP). Th
e Zero‐Voltag
PI33XX series
roviding best i
equires only a
itors to form
regulator.
Iout Max
10A
10A
10A
10A
8A
8A
ons available for
of 1.5 to 1.9V,
rchitecture als
hile minimizin
iency. The hig
s the size of th
proves powe
mic response t
series sustain
up to the rate
iency and, wit
arge step dow
Z Family Datashe
r® ZVS B
ut
ng
ts
e
ge
s,
n
n
a
r
o
g
h
e
er
o
ns
d
h
n
Feat H Z W V H U P P In O O F ‐4 O
App H CA
H
Pack 1 5
eet Rev
Buck Reg
tures High efficiency
ZVS‐Buck Topo
Wide input volt
Very‐Fast trans
High accuracy p
User adjustable
Power‐up into
Parallel capable
nput Over/Und
Output Overvo
Over Temperat
Fast and slow c
40°C to 125°C
Optional I2C fun
Vout margi
Fault repor Enable and Phase delaregulators)
plicationsHigh efficiency
Computing, ComAutomotive Eq
High voltage ba
kage Inform10mm x 14mm
5.4kW/in3
1.1 August 6, 20
gulator F
up to 98%
logy
tage range of 8
sient response
pre‐trimmed o
e soft‐start & t
pre‐biased loa
e with single w
der Voltage Lo
ltage Protectio
ture Protection
current limits
operating rang
nctionality & p
ining
rting
d SYNCI pin pol
y (for interleav)
systems
mmunicationsuipment
attery operatio
mation x 2.6mm LGA
P
012 Page
Family
8V to 36V
utput voltage
racking
d (select versio
wire current sha
ckout (OVLO/U
on (OVP)
n (OTP)
ge (TJ)
programmabilit
arity
ving multiple
, Industrial,
on
SiP
PI33XX‐X0‐ Cool‐Pow
1 of 40
ons)
aring
UVLO)
ty:
‐LGIZwer®
Picor Corporation • picorpower.com PI33XX‐X0‐LGIZ Family Datasheet Rev 1.1 August 6, 2012 Page 2 of 40
Contents Order Information ............................................... 3
PI33XX Efficiency ................................................. 3
Pin Description .................................................... 4
Package Pin‐Out .................................................. 4
Absolute Maximum Ratings at 25°C ................... 5
PI3311‐X0 (1.0 VOUT) Electrical Characteristics . 6
Electrical Specifications ................................... 6
PI3311‐X0 Typical Characteristics ................... 9
PI3312‐X0 (2.5 Vout) Electrical Characteristics . 11
Electrical Specifications ................................. 11
PI3312‐X0 Typical Characteristics ................. 13
PI3301‐X0 (3.3 Vout) Electrical Characteristics . 15
Electrical Specifications ................................. 15
PI3301‐X0 Typical Characteristic ................... 17
PI3302‐X0 (5.0Vout) Electrical Characteristics .. 19
Electrical Specifications ................................. 19
PI3302‐X0 Typical Characteristics ................. 21
PI3303‐X0 (12Vout) Electrical Characteristics ... 23
Electrical Specifications ................................. 23
PI3303‐X0 Typical Characteristics ................. 25
PI3305‐X0 (15 Vout) Electrical Characteristics .. 27
Electrical Specifications ................................. 27
PI3305‐X0 Typical Characteristics ................. 29
Functional Description ...................................... 31
ENABLE (EN) .................................................. 31
Switching Frequency Synchronization .......... 31
Output Voltage Trimming ............................. 31
Soft‐Start ....................................................... 31
Remote Sensing ............................................ 32
Output Current Limit Protection ................... 32
Input Under‐Voltage Lockout ....................... 32
Input Over Voltage Lockout .......................... 32
Output Over Voltage Protection ................... 32
Over Temperature Protection ....................... 32
Pulse Skip Mode (PSM) ................................. 32
Variable Frequency Operation ...................... 33
Parallel Operation ......................................... 33
I2C Bus (PI33XX‐20 and PI33XX‐21 only) ....... 33
Application Description ..................................... 34
Output Voltage Programming ....................... 34
Soft‐Start Adjust and Tracking ...................... 35
Inductor Pairing ............................................. 35
Input and Output Filter Considerations ........ 36
Layout Guidelines .............................................. 37
Recommended PCB Footprint and Stencil ........ 38
Package Drawings ............................................. 39
Warranty ........................................................... 40
Picor Corpo
Order In
Cool-P
PI3311‐0
PI3312‐0
PI3301‐0
PI3302‐0
PI3303‐0
PI3305‐0
Higher C
PI3311‐0
PI3312‐0
PI3301‐0
I2C Func
PI3311‐2
PI3312‐2
PI3301‐2
PI3302‐2
PI3303‐2
PI3305‐2
PI3311‐2
PI3312‐2
PI3301‐2
*Please con
PI33XX
ration • picorpo
nformatio
Power
0‐LGIZ
0‐LGIZ
0‐LGIZ
0‐LGIZ
0‐LGIZ
0‐LGIZ
Current Versio
1‐LGIZ
1‐LGIZ
1‐LGIZ
tionality & P
0‐LGIZ
0‐LGIZ
0‐LGIZ
0‐LGIZ
0‐LGIZ
0‐LGIZ
1‐LGIZ
1‐LGIZ
1‐LGIZ
ntact Picor for av
Efficiency
ower.com
n
Output R
Set
1.0V 1
2.5V 2.
3.3V 2
5.0V 3
12V 6
15V 10
ons*
1.0V 1
2.5V 2
3.3V 2
rogrammabil
1.0V 1
2.5V 2
3.3V 2
5.0V 3
12V 6
15V 10
1.0V 1
2.5V 2
3.3V 2
vailability
PI33XX‐X0‐LGIZ
Range
Range
.00 to 1.4V
.0V to 3.1V
2.3 to 4.1V
3.3 to 6.5V
.5 to 13.0V
0.0 to 16.0V
1.0 to 1.4V
2.0 to 3.1V
2.3 to 4.1V
lity*
1.0 to 1.4V
2.0 to 3.1V
2.3 to 4.1V
.30 to 6.5V
.5 to 13.0V
0.0 to 16.0V
1.0 to 1.4V
2.0 to 3.1V
2.3 to 4.1V
Z Family Datashe
Iout Max
10A 10m
10A 10m
10A 10m
10A 10m
8A 10m
8A 10m
18A 10m
18A 10m
18A 10m
10A 10m
10A 10m
10A 10m
10A 10m
8A 10m
8A 10m
18A 10m
18A 10m
18A 10m
eet Rev
Package
mm x 14mm 12
mm x 14mm 12
mm x 14mm 12
mm x 14mm 12
mm x 14mm 12
mm x 14mm 12
mm x 14mm 12
mm x 14mm 12
mm x 14mm 12
mm x 14mm 12
mm x 14mm 12
mm x 14mm 12
mm x 14mm 12
mm x 14mm 12
mm x 14mm 12
mm x 14mm 12
mm x 14mm 12
mm x 14mm 12
1.1 August 6, 20
e T
23‐pin LGA
23‐pin LGA
23‐pin LGA
23‐pin LGA
23‐pin LGA
23‐pin LGA
23‐pin LGA
23‐pin LGA
23‐pin LGA
23‐pin LGA
23‐pin LGA
23‐pin LGA
23‐pin LGA
23‐pin LGA
23‐pin LGA
23‐pin LGA
23‐pin LGA
23‐pin LGA
012 Page
Transport Me
TRAY
TRAY
TRAY
TRAY
TRAY
TRAY
TRAY
TRAY
TRAY
TRAY
TRAY
TRAY
TRAY
TRAY
TRAY
TRAY
TRAY
TRAY
3 of 40
edia
Picor Corpo
Pin DesName
SGND
PGND
VIN
VOUT
VS1
PGD
EAO
EN
REM
ADJ
TRK
NC
SYNCO
SYNCI
SDA
SCL
ADR1
ADR0
Package
ration • picorpo
scription Number
Block 1
Block 2
Block 3
Block 5
Block 4
A1
A2
A3
A5
B1
C1
K3, A4
K4
K5
D1
E1
H1
G1
e Pin‐Out
123‐Lead LGA (Top
TJmax = 125 °C,
ower.com
Description
Signal ground:communicatio
Power ground
Input voltage:
Output voltage
Switching nod
Parallel Good:
Error amp out
Enable Input: Asserted low, r
Remote Sense
Adjust input: Athe output volt
Soft‐start and to decrease th
No Connect: L
Synchronizatioother converte
Synchronizatioimpedance dig
Data Line: No
Clock Line: No
Tri‐state Addre
Tri‐state Addre
10mm x 14mm)view
θJA = 22 °C/W
PI33XX‐X0‐LGIZ
: Internal logic gn returns. SGND
: VIN and VOUT
and sense for U
e: and sense for
e: and ZVS sens
Used for paralle
put: External co
Regulator enablregulator output
e: High side conn
An external resistage up or down
track input: Ane rate of rise du
Leave pins floati
on output: Outpers.
on input: Synchrgital input node a
connect for PI3
connect for PI3
ess : No connect
ess : No connect
)
Z Family Datashe
round for EA, TRD and PGND are
power returns
UVLO, OVLO and
r power switches
e for power swit
el timing manag
onnection for add
e control. Assertt disabled. Polar
nection. Connec
stor may be conn.
n external capaciring soft‐start.
ng.
puts a low signal
ronize to the falland should alwa
3XX‐10 and ‐11.
3XX‐10 and ‐11.
t for PI33XX‐10 a
t for PI33XX‐10 a
eet Rev
RK, SYNCI, SYNCOstar connected w
feed forward ra
s and feed‐forw
tches
gement intended
ditional compen
ted high or left frity is programm
ct to output regu
nected between
itor may be conn
for ½ of the min
ling edge of exteays be connected
. For use with PI
. For use with PI
and ‐11. For use
and ‐11. For use
Block 1: B2‐H2
Block 2: A8‐
F4‐ Block 3: G1
Block 4: A1E1
Block 5: A6
1.1 August 6, 20
O, ADJ and I2C (owithin the regul
amp
ard ramp
d for lead regula
nsation and curr
floating – regulamable via I2C inte
ulation point.
n ADJ pin and SG
nected between
nimum period fo
ernal clock frequd to ground whe
33XX‐20 and ‐21
33XX‐20 and ‐21
e with PI33XX‐20
e with PI33XX‐20
‐4, C2‐4, D2‐32‐3, J1‐3, K1‐2
‐10, B8‐10, C8‐‐10, G4‐10, H4
2‐14, H12‐14,
12‐14, B12‐14, 2‐14,
6‐7, B6‐7, C6‐7,
012 Page
options) lator package.
ator.
ent sharing.
ator enabled; erface.
GND or VOUT to
n TRK pin and SG
or synchronizatio
uency. SYNCI is en not in use.
1 only.
1 only.
0 and ‐21 only.
0 and ‐21 only.
3, E2‐3, F1‐3,
‐10, D8‐10, E4‐4‐10, J4‐10, K6‐
J12‐14, K12‐14
C12‐14, D12‐1
, D6‐7
4 of 40
trim
GND
on of
a high
G2‐3,
‐10, ‐10
4
14,
Picor Corpo
Absolut
Note: All
VIN
VS1
VOUT
SGND
PGD, SYN
Storage T
Operating
Soldering
ESD Ratin
V
ration • picorpo
te Maximu
voltage nodes
NCO, SYNCI, EN
Temperature
g Junction Tem
g Temperature
ng
(I2C pi
VIN
PGND
SYNCO
PGD
VC
EN
SYNCI
Power Control
ower.com
um Ratings
s are reference
, EAO, ADJ, TR
mperature
for 20 second
ins SCL, SDA, AD
Q1
CC
Mem
0Ω
PI33XX‐X0‐LGIZ
s at 25°C
ed to PGND
RK, ADR1, ADR2
s
Figure 1: Sim
R0, and ADR1 on
1Q2
Imory
ZVS Contro
Z Family Datashe
2, SCL, SDA
mplified Block D
nly active for PI3
Interface
l
eet Rev
See r
Diagram
33XX‐20 and PI3
+
-
R4
R2
R1
1V
1.1 August 6, 20
‐0.7V to 36V
‐0.7 to 36V, ‐
relevant produ
‐0.3V to 5
‐65°C
‐40°C
33XX‐21 versions
TRK
EAO
ADJ
VS1
VOUT
REM
R3
012 Page
V / 18A DC
‐4V for 5ns
uct section
100mA
5.5V / 5mA
C to 150°C
C to 140°C
260°C
2kV HBM
s)
Vout
5 of 40
Picor Corpo
PI3311‐
Electrical
Unless oth
Paramete
Efficiency
Output
Output Vo
Output Vo
Output Vo
Line Regu
Load Regu
Output Vo
Continuou
Current Li
Input Cur
Input Curr
Inrush Inp
Input Curr
(Fault Con
Protection
UVLO Thre
UVLO Hys
OVLO Thr
OVLO Hys
UVLO/OV
UVLO/OV
OVP
Over‐Tem
Over‐Tem
Hysteresis
Timing
Switching
ration • picorpo
‐X0 (1.0 VO
Specification
erwise specifie
er
oltage
oltage Total Re
oltage Range
lation
ulation
oltage Ripple
us Output Curr
mit
rent
rent
put Current At
rent At Output
ndition)
n
eshold
steresis
eshold
steresis
LO Fault Delay
LO Response T
mperature Fault
mperature Rest
s
Frequency
ower.com
OUT) Elect
ns
ed: ‐40C < TJ <
egulation
rent Range
Soft Start
t Short
y Time
Time
t Threshold
tart
PI33XX‐X0‐LGIZ
rical Chara
< 125C, Vin =2
Symbol
VOUT_DC
VOUT_DC
VOUT_DC
∆VOUT(∆VIN)
∆VOUT(∆IOUT)
VOUT_AC
IOUT_DC
IOUT_CL
IIN_DC
IIN_SS
IIN_Short
VUVLO
VUVLO_HYS
VOVLO
VOVLO_HYS
tf_DLY
tf
VOVP
VOTP
VOTP_HYS
fS
Z Family Datashe
acteristics
24V, L1=120nH
Min
0.987
)
0
10.2
7.08
37
130
eet Rev
H
Typ Max
87.7
1.0
1.0 1.013
1.0 1.4
0.1 0.15
0.1 0.15
20
10
13
476
200
300
7.45 7.82
0.37
38.4 40
0.77
128
500
20
135 140
30
380
1.1 August 6, 20
Units Co
% Vi Io
V 0
V ‐4
V
% @
12
% @
0.
mVp‐p Io
20
A Se
A
mA ViIo
mA ViCi
mA
V
V
V
V
Cycles
N
s
c
ns +
% A
°C
°C
kHz Vi(1)
012 Page
onditions
in = 24V, TC = 2out = 10 A
0 °C <TJ <70°C
40 °C <TJ <125°
@ 25°C,
2V<Vin<36V
@ 25°C,
.5A<Iout<10A
ut=5A, Cout=8x
0MHz BW
ee Iout vs. TA Cu
in = 24V, TC = 2out=10A
in=24V, Iout=0in=4x4.7µF ML
Number of the
switching frequ
cycles
+1% overdrive
Above VOUT
in ≥ 18V, Iout ≤)
6 of 40
25°C,
C
100μF,
urves
25°C,
0ALCC
e
uency
≤ 8A
Picor Corpo
Fault Rest
ration • picorpo
tart Delay
ower.com PI33XX‐X0‐LGIZ
tFR_DLY
Z Family Datashe
eet Rev
30
1.1 August 6, 20
ms
012 Page 7 of 40
Picor Corpo
PI3311‐(continuUnless oth
Paramete
Input Pow
Input Volt
Input Volt
Input Quie
Soft Start
TRK Active
TRK Offse
Charge Cu
Discharge
Soft‐Start
Enable
High Thre
Low Thres
Threshold
Enable Pu
Enable Pu
Source Cu
Sink Curre
Sync In (S
Synchroni
SYNCI Thr
SYNCI Pro
Sync Out
SYNCO Hig
SYNCO Lo
SYNCO Ris
SYNCO Fa
Note 1: Re
ration • picorpo
‐X0 Electricued) erwise specifie
er
wer
tage
tage Slew Rate
escent Current
And Tracking
e Range (Nomi
t Voltage / Dis
urrent (Soft – S
Current (Fault
Time
shold
shold
d Hysteresis
ll‐Up Voltage
ll‐Down Voltag
urrent
ent
YNCI)
ization Frequen
reshold
ogrammable Ph
(SYNCO)
gh
w
se Time
ll Time
efer to Switchin
ower.com
cal Specific
ed: ‐40C < TJ <
t
Function
inal)
able Threshold
Start)
t)
ge
ncy Range
hase Shift
ng Frequency v
PI33XX‐X0‐LGIZ
cations
< 125C, Vin =2
Symbol
VIN_DC
VIN_SR
IQ_VIN
VTRK
d VTRK_OV
ITRK
ITRK_DIS
tSS
VEN_HI
VEN_LO
VEN_HYS
VEN_PU
VEN_PD
IEN_SO
IEN_SK
∆fSYNCI
VSYNCI
∆φSYNCI
VSYNCO_HI
VSYNCO_LO
tSYNCO_RT
tSYNCO_FT
vs. Iout graph
Z Family Datashe
24V,
Min Typ
8
2
0
20
‐70 ‐
6
2
0.9
0.7 0
100 2
‐
50
2
0
4.5
0
eet Rev
p Max
24 36
1
2
2.5
1
40 60
‐50 ‐30
6.8
2.2 2.6
1 1.1
0.8 0.9
200 300
2
0
‐50
50
110
2.5
‐270
5.2
0.5
10 20
10 20
1.1 August 6, 20
Units Co
V
V/μs
mA Di
En
V
mV
µA
mA
ms CT
V
V
mV
V
V
uA
uA
% Wsefr
V
°
V So
V S
ns 2
ns 2
012 Page
onditions
isabled
nabled
TRK = 0
With respect to et switching equency
ource 1mA.
Sink 1mA.
20pF load
20pF load
8 of 40
the
Picor Corpo
PI3311‐
Efficiency
Ambient
0 LFM, Si Switching
L1 = 120n
50
55
60
65
70
75
80
85
90
95
100
0
Efficiency [%]
0
2
4
6
8
10
12
75
Load
Current [A]
050
100150200250300350400450500550
1
Switching Frequency [kH
z]
ration • picorpo
‐X0 Typica
y at 25°C
Temperature
P Only
g frequency vs
nH
1 2 3
85 9Ambient
8V24V36V
1 2 3 4
12Vin
24Vin
36Vin
ower.com
l Characte
vs. Load Curre
s load current
4 5 6 7
Iout [A]
95 105t Temperature [⁰C
VV
5 6 7LOAD [A]
PI33XX‐X0‐LGIZ
ristics
33110
ent Curve
331103
331105
7 8 9 10
12Vin
24Vin
36Vin
115 125C]
8 9 10
Z Family Datashe
01
3
5
To
Tra
LoaCo
Ou
Vo2.0Co
Power Loss [W]
eet Rev
otal Power Los
ansient Respo
ad Step: 2A to 7out = 8X 100 µF C
utput ripple: V
out = 50mV/Div0us/Div out = 8X 100 µF
0
0.5
1
1.5
2
0 1 2
Poweross
[W]
1.1 August 6, 20
s (including ex
onse: 24V to 1.
7A at 5A/us Ceramic
Vin =24V, Vout
v F Ceramic
3 4 5
Iout [
012 Page
xternal compo
0V
= 1.0V at 10A
6 7 8 9
[A]
12Vin
24Vin
9 of 40
nents)
331102
331104
A
331106
9 10
Picor Corpo
PI3311(contin Output ri
Vout = 502.0us/DivCout = 8X
ration • picorpo
1‐X0 Typicanued)
ipple: Vin =24V
0mV/Div v X 100 µF Ceram
ower.com
al Characte
V, Vout = 1.0V
mic
PI33XX‐X0‐LGIZ
eristics
at 5A
331
Z Family Datashe
1107
Sh
VoIin
td
eet Rev
hort circuit test
out = 500mV/Dn = 500mA/Div delay_fault = 1m
1.1 August 6, 20
t
Div =Ch2 = Ch4 ms
012 Page 1
10 of 40
331108
Picor Corpo
PI3312‐
Electrical
Unless oth
Paramete
Efficiency
Output
Output Vo
Output Vo
Output Vo
Line Regu
Load Regu
Output Vo
Continuou
Current Li
Input Cur
Input Curr
Soft‐Start
Input Curr
Condition
Protection
UVLO Thre
UVLO Hys
OVLO Thr
OVLO Hys
UVLO/OV
UVLO/OV
OVP Thres
Over‐Tem
Over‐Tem
Timing
Switching
Fault Rest
ration • picorpo
‐X0 (2.5 Vo
Specification
erwise specifie
er
oltage
oltage Total Re
oltage Range
lation
ulation
oltage Ripple
us Output Curr
mit
rent
rent
Current
rent At Output
)
n
eshold
steresis
eshold
steresis
LO Fault Delay
LO Response T
shold
mperature Faul
mperature Rest
Frequency
tart Delay
ower.com
out) Electri
ns
ed: ‐40C < TJ <
egulation
rent Range
t Short (Fault
y Time
Time
lt Threshold
tart Hysteresis
PI33XX‐X0‐LGIZ
ical Charac
< 125C, Vin = 2
Symbol
VOUT_DC
VOUT_DC
VOUT_DC
∆VOUT(∆VIN)
∆VOUT(∆IOUT)
VOUT_AC
IOUT_DC
IOUT_CL
IIN_DC
IIN_SS
IIN_Short
VUVLO
VUVLO_HYS
VOVLO
VOVLO_HYS
tf_DLY
tf
VOVP
VOTP
s VOTP_HYS
fS
tFR_DLY
Z Family Datashe
cteristics
24V, L1=200 nH
Min T
9
2
2.465 2
2.0 2
0
0
0
1
2
7.08 7
0
37 3
0
1
5
130 1
5
eet Rev
H
Typ Max
91.3
2.50
2.50 2.535
2.5 3.1
0.1 0.15
0.1 0.15
28
10
12
1.14
200
300
7.45 7.82
0.37
38.4 40
0.77
128
500
20
135 140
30
500
30
1.1 August 6, 20
Units Co
% Vi Io
V 0
V ‐4
V
% @
% @
0.
mVp‐p
Io
Co
20
A
A
A ViIo
mA ViCi
mA
V
V
V
V
Cycles
N
s
c
ns +
% A
°C
°C
kHz Vi
ms
012 Page 1
onditions
in = 24V, TC = 2out = 10 A
0 °C <TJ <70°C
40 °C <TJ <125°
@ 25°C 12V<Vin
@ 25°C,
.5A<Iout<10A
out=5A,
out=4x100μF,
0MHz BW
in = 24V, TC = 2out=10A
in=24V, Iout=0in=4x4.7µF ML
Number of the
switching frequ
cycles
+1% overdrive
Above VOUT
n ≥ 18V, Iout ≤ 8A
11 of 40
25°C,
C
n<36V
25°C,
0ALCC
e
uency
(1)
Picor Corpo
PI3312‐
(continuUnless oth
Paramete
Input Pow
Input Volt
Input Volt
Input Quie
Soft Start
TRK Active
TRK Offse
Charge Cu
Discharge
Soft‐Start
Enable
Enable Hig
Enable Lo
Enable Th
Enable Pu
Enable Pu
Source Cu
Sink Curre
Sync In (S
Synchroni
SYNCI Thr
SYNCI Pro
Sync Out
SYNCO Hig
SYNCO Lo
SYNCO Ris
SYNCO Fa
ration • picorpo
‐X0 Electric
ued) erwise specifie
er
wer
tage
tage Slew Rate
escent Current
And Tracking
e Range (Nomi
t Voltage / Dis
urrent (Soft –St
Current (Fault
Time
gh Threshold
w Threshold
reshold Hyster
ll‐Up Voltage
ll‐Down Voltag
urrent
ent
YNCI)
ization Frequen
reshold
ogrammable Ph
(SYNCO)
gh
w
se Time
ll Time
ower.com
cal Specific
ed: ‐40C < TJ <
t
Function
inal)
able Threshold
tart)
t)
resis
ge
ncy Range
hase Shift
PI33XX‐X0‐LGIZ
cations
< 125C, Vin =2
Symbol
VIN_DC
VIN_SR
IQ_VIN
VTRK
d VTRK_OV
ITRK
ITRK_DIS
tSS
VEN_HI
VEN_LO
VEN_HYS
VEN_PU
VEN_PD
IEN_SO
IEN_SK
∆fSYNCI
VSYNCI
∆φSYNCI
VSYNCO_HI
VSYNCO_LO
tSYNCO_RT
tSYNCO_FT
Z Family Datashe
24V,
Min Typ
8
2
0
20
‐70 ‐
6
2
0.9
0.7 0
100 2
‐
50
2
0
4.5
0
eet Rev
p Max
24 36
1
2
2.5
1
40 60
‐50 ‐30
6.8
2.2 2.6
1 1.1
0.8 0.9
200 300
2
0
‐50
50
110
2.5
270
5.2
0.5
10 20
10 20
1.1 August 6, 20
Units Co
V
V/μs
mA Di
En
V
mV
µA
mA
ms CT
V
V
mV
V
V
uA
uA
% Wsefr
V
°
V So
V S
ns 2
ns 2
012 Page 1
onditions
isabled
nabled
TRK = 0, 0A< Iou
With respect to et switching equency
ource 1mA.
Sink 1mA.
20pF load
20pF load
12 of 40
ut ≤ 8A
the
Picor Corpo
PI3312‐
Efficiency a
L1=200nH
Ambient T
0 LFM, SiP
Switching f
L1 = 200nH
50%
55%
60%
65%
70%
75%
80%
85%
90%
95%
0
Efficiency
[%]
0
2
4
6
8
10
12
75
Output Current [A]
0
100
200
300
400
500
600
1
Freq. [KHz]
ration • picorpo
‐X0 Typica
at 25°C
emperature vs
Only
frequency vs.
0 1 2 3
85 95
Ambient
8V
24V
36V
2 3 4
12V
24V
36V
ower.com
l Characte
s. Load Curren
load current
4 5 6 7
LOAD [A]
105 11
Temperature [°C]
5 6 7Load [A]
PI33XX‐X0‐LGIZ
ristics
331201
nt Curve
331203
331205
8 9 10
12V24V36V
15 125
]
8 9 10
Z Family Datashe
Tota
Trans
VouIout200Cou
Out
Vou2.0uCou
Power Loss [W]
eet Rev
al Power Loss
sient Response
ut = 100mV/Divt = 2A/Div. = C0us/Div. ut = 4 x 100µF C
tput ripple: Vi
ut = 20mV/Div.us/Div. ut = 4 x 100µF C
0.00
1.00
2.00
3.00
4.00
0 1 2
[]
1.1 August 6, 20
(including ext
e: 24V to 2.5V
v. = Ch 1 h 4
Ceramic
in = 24V and V
Ceramic
2 3 4 5
LOAD [
12V24V36V
012 Page 1
ernal compon
V and 5A to Loa
Vout = 2.5V at 1
6 7 8 9
[A]
13 of 40
ents)
331202
ad Step
331204
10A
331206
10
Picor Corpo
PI3312‐(continu
Output rip
Vout = 20m2.0us/Div. Cout = 4 x
ration • picorpo
‐X0 Typicalued)
ple: Vin = 24V
mV/Div.
100µF Ceramic
ower.com
l Characte
V and Vout = 2
c
PI33XX‐X0‐LGIZ
ristics
.5V at 5A
331207
Z Family Datashe
Sho
Vout Iin = 5tdela
eet Rev
ort circuit test
= 1V/Div. = Ch500mA/Div. = ay_fault = 1ms
1.1 August 6, 20
h4 Ch1
012 Page 1
14 of 40
331208
Picor Corpo
PI3301‐
Electrical
Unless oth
Paramete
Efficiency
Output
Output Vo
Output Vo
Output Vo
Line Regu
Load Regu
Output Vo
Continuou
Current Li
Input Cur
Input Curr
Soft‐Start
Input Curr
Condition
Protection
UVLO Thre
UVLO Hys
OVLO Thr
OVLO Hys
UVLO/OV
UVLO/OV
OVP
Over‐Tem
Over‐Tem
Timing
Switching
Fault Rest
ration • picorpo
‐X0 (3.3 Vo
Specification
erwise specifie
er
oltage
oltage Total Re
oltage Range
lation
ulation
oltage Ripple
us Output Curr
mit
rent
rent
Input Current
rent At Output
)
n
eshold
steresis
eshold
steresis
LO Fault Delay
LO Response T
mperature Faul
mperature Rest
Frequency
tart Delay
ower.com
out) Electri
ns
ed: ‐40C < TJ <
egulation
rent Range
t Short (Fault
y Time
Time
lt Threshold
tart Hysteresis
PI33XX‐X0‐LGIZ
ical Charac
< 125C, Vin =2
Symbol
VOUT_DC
VOUT_DC
VOUT_DC
∆VOUT(∆VIN)
∆VOUT(∆IOUT)
VOUT_AC
IOUT_DC
IOUT_CL
IIN_DC
IIN_SS
IIN_Short
VUVLO
VUVLO_HYS
VOVLO
VOVLO_HYS
tf_DLY
tf
VOVP
VOTP
s VOTP_HYS
fS
tFR_DLY
Z Family Datashe
cteristics
24V, L1=200 nH
Min T
9
3
3.25 3
2.3 3
0
0
3
0
1
2
7.08 7
0
37 3
0
1
5
130 1
6
eet Rev
H
Typ Max
92.2
3.30
3.30 3.36
3.3 4.1
0.10 0.15
0.10 0.15
37.5
10
12
1.49
200
300
7.45 7.82
0.37
38.4 40.0
0.77
128
500
20
135 140
30
650
30
1.1 August 6, 20
Units Co
% Vi Io
V 0
V ‐4
V
% @
% @
0.
mVp‐p
Io
Co
20
A
A
A ViIo
mA ViCi
mA
V
V
V
V
Cycles
N
s
c
ns +
% A
°C
°C
kHz Vi(1)
ms
012 Page 1
onditions
in = 24V, TC = 2out = 10 A
0 °C <TJ <70°C
40 °C <TJ <125°
@ 25°C 12V<Vin
@ 25°C,
.5A<Iout<10A
out=5A,
out=4x100μF,
0MHz BW
in = 24V, TC = 2out=10A
in=24V, Iout=0in=4x4.7µF ML
Number of the
switching frequ
cycles
+1% overdrive
Above VOUT
in ≥ 12V, Iout ≤)
15 of 40
25°C,
C
n<36V
25°C,
0ALCC
e
uency
≤ 10A
Picor Corpo
PI3301‐
(continuUnless oth
Paramete
Input Pow
Input Volt
Input Volt
Input Quie
Soft Start
TRK Active
TRK Offse
Charge Cu
Discharge
Soft‐Start
Enable
Enable Hig
Enable Lo
Enable Th
Enable Pu
Enable Pu
Source Cu
Sink Curre
Sync In (S
Synchroni
SYNCI Thr
SYNCI Pro
Sync Out
SYNCO Hig
SYNCO Lo
SYNCO Ris
SYNCO Fa
ration • picorpo
‐X0 Electric
ued) erwise specifie
er
wer
tage
tage Slew Rate
escent Current
And Tracking
e Range (Nomi
t Voltage / Dis
urrent (Soft –St
Current (Fault
Time
gh Threshold
w Threshold
reshold Hyster
ll‐Up Voltage
ll‐Down Voltag
urrent
ent
YNCI)
ization Frequen
reshold
ogrammable Ph
(SYNCO)
gh
w
se Time
ll Time
ower.com
cal Specific
ed: ‐40C < TJ <
t
Function
inal)
able Threshold
tart)
t)
resis
ge
ncy Range
hase Shift
PI33XX‐X0‐LGIZ
cations
< 125C, Vin =2
Symbol
VIN_DC
VIN_SR
IQ_VIN
VTRK
d VTRK_OV
ITRK
ITRK_DIS
tSS
VEN_HI
VEN_LO
VEN_HYS
VEN_PU
VEN_PD
IEN_SO
IEN_SK
∆fSYNCI
VSYNCI
∆φSYNCI
VSYNCO_HI
VSYNCO_LO
tSYNCO_RT
tSYNCO_FT
Z Family Datashe
24V,
Min Typ
8
2
0
20
‐70 ‐
6
2
0.9
0.7 0
100 2
‐
50
2
0
4.5
0
eet Rev
p Max
24 36
1
2
2.5
1
40 60
‐50 ‐30
6.8
2.2 2.6
1 1.1
0.8 0.9
200 300
2
0
‐50
50
110
2.5
270
5.2
0.5
10 20
10 20
1.1 August 6, 20
Units Co
V
V/μs
mA Di
En
V
mV
µA
mA
ms N
Io
V
V
mV
V
V
uA
uA
% Wsefr
V
°
V So
V S
ns 2
ns 2
012 Page 1
onditions
isabled
nabled
o external CTRK
out ≤ 8A
With respect to et switching equency
ource 1mA.
Sink 1mA.
20pF load
20pF load
16 of 40
K, 0A<
the
Picor Corpo
PI3301‐
Efficiency a
L1=200nH Ambient T
0 LFM, SiP
Switching
L1 = 200nH
50%
55%
60%
65%
70%
75%
80%
85%
90%
95%
100%
0
Efficiency [%]
0
2
4
6
8
10
12
75
Output Current [A]
0
100
200
300
400
500
600
700
1
Frequency (KHz)
ration • picorpo
‐X0 Typica
at 25°C
Temperature v
P Package Only
frequency vs.
0 1 2 3
85 95Ambient
8V
24V
36V
2 3 4
12V
24V
36V
ower.com
l Characte
vs. Load Curren
load current
4 5 6 7LOAD [A]
1243
105 1t Temperature [°C
5 6 7Load (A)
PI33XX‐X0‐LGIZ
ristic
330101
nt Curve
330103
330105
8 9 10
2V4V6V
115 125C]
8 9 10
Z Family Datashe
5
Tota
Tra
LoaCou Out
Vou2.0Cou
Power Loss (W)
eet Rev
al Power Loss (in
ansient Respon
ad Step: 2A to 7ut = 4 x 100µF
tput ripple: Vi
ut = 50mV/Div us/Div ut = 4 x 100µF
0.00
1.00
2.00
3.00
4.00
0 1 2
Power Loss (W)
1.1 August 6, 20
ncluding extern
nse: 24V to 3.3
7A Ceramic
n = 24V, Vout
Ceramic
2 3 4 5LOAD
12V24V36V
012 Page 1
al components)
3V
= 3.3V at 10A
6 7 8 9(A)
17 of 40
)
330102
330104
330106
9 10
Picor Corpo
PI3301‐(contin
Output rip
Vout = 50m2.0us/Div Cout = 4 x
ration • picorpo
‐X0 Typicaued)
pple Vin = 24V,
mV/Div
100µF Cerami
ower.com
l Characte
, Vout = 3.3V a
c
PI33XX‐X0‐LGIZ
eristic
at 5A
330107
Z Family Datashe
Sho
tdela
eet Rev
ort circuit test
ay_fault = 1ms
1.1 August 6, 20
012 Page 1
18 of 40
330108
Picor Corpo
PI3302‐Electrical
Unless oth
Paramete
Efficiency
Efficiency
Output
Output Vo
Output Vo
Output Vo
Line Regu
Load Regu
Output Vo
Continuou
Current Li
Input Cur
Input Curr
Inrush Inp
Input Curr
Condition
Protection
UVLO Thre
UVLO Hys
OVLO Thr
OVLO Hys
UVLO/OV
UVLO/OV
OVP
Over‐Tem
Over‐Tem
Timing
Switching
Fault Rest
ration • picorpo
‐X0 (5.0VoSpecification
erwise specifie
er
y
oltage
oltage Total Re
oltage Range
lation
ulation
oltage Ripple
us Output Curr
mit
rent
rent
put Current At
rent At Output
)
n
eshold
steresis
eshold
steresis
LO Fault Delay
LO Response T
mperature Fault
mperature Resta
Frequency
tart Delay
ower.com
ut) Electricns
ed: ‐40C < TJ <
egulation
rent Range
Startup
t Short (Fault
y Time
Time
t Threshold
art Hysteresis
PI33XX‐X0‐LGIZ
cal Charac
< 125C, Vin =2
Symbol
VOUT_DC
∆VOUT(∆VIN
∆VOUT(∆IOUT
VOUT_AC
IOUT_DC
IOUT_CL
IIN_DC
IIN_SS
IIN_Short
VUVLO
VUVLO_HYS
VOVLO
VOVLO_HYS
tf_DLY
tf
VOVP
VOTP
VOTP_HYS
fS
tFR_DLY
Z Family Datashe
cteristics
24V, L1=200nH
Min T
9
5
4.93
3.3
N)
T)
0
10.2 1
2
7.08 7
0
37 3
0
1
5
130 1
eet Rev
H
Typ Max
93.9
5.00
5.00 5.07
5.0 6.5
0.1 0.15
0.1 0.15
30
10
11.2 12.6
2.23
100
300
7.45 7.82
0.37
38.4 40
0.77
128
500
20
135 140
30
1.0
30
1.1 August 6, 20
Units Co
% ViIo
V 0
V ‐4
V
% @
% @
0.
mVp‐p
Io
Co
BW
A
A
A ViIo
mA ViCi
mA
V
V
V
V
Cycles
N
s
c
ns +
% A
°C
°C
MHz Vi(1)
ms
012 Page 1
onditions
in = 24V, TC = 2out=10A
0 °C <TJ <70°C
40 °C <TJ <125°
@ 25°C 12V<Vin
@ 25°C,
.5A<Iout<10A
out=5A,
out=4x47μF20
W
in = 24V, TC = 2out=10A
in=24V, Iout=0in=4x4.7µF ML
Number of the
switching frequ
cycles
+1% overdrive
Above VOUT
in ≥ 18V, Iout ≤)
19 of 40
25°C,
C
n<36V
MHz
25°C,
0ALCC
e
uency
≤ 10A
Picor Corpo
PI3302‐
(continuUnless oth
Paramete
Input Pow
Input Volt
Input Volt
Input Quie
Soft Start
TRK Active
TRK Offse
Charge Cu
Discharge
Soft‐Start
Enable
Enable Hig
Enable Lo
Enable Th
Enable Pu
Enable Pu
Source Cu
Sink Curre
Sync In (S
Synchroni
SYNCI Thr
SYNCI Pro
Sync Out
SYNCO Hig
SYNCO Lo
SYNCO Ris
SYNCO Fa
ration • picorpo
‐X0 Electric
ued) erwise specifie
er
wer
tage
tage Slew Rate
escent Current
And Tracking
e Range (Nomi
t Voltage / Dis
urrent (Soft –St
Current (Fault
Time
gh Threshold
w Threshold
reshold Hyster
ll‐Up Voltage
ll‐Down Voltag
urrent
ent
YNCI)
ization Frequen
reshold
ogrammable Ph
(SYNCO)
gh
w
se Time
ll Time
ower.com
cal Specific
ed: ‐40C < TJ <
t
Function
inal)
able Threshold
tart)
t)
resis
ge
ncy Range
hase Shift
PI33XX‐X0‐LGIZ
cations
< 125C, Vin =2
Symbol
VIN_DC
VIN_SR
IQ_VIN
VTRK
d VTRK_OV
ITRK
ITRK_DIS
tSS
VEN_HI
VEN_LO
VEN_HYS
VEN_PU
VEN_PD
IEN_SO
IEN_SK
∆fSYNCI
VSYNCI
∆φSYNCI
VSYNCO_HI
VSYNCO_LO
tSYNCO_RT
tSYNCO_FT
Z Family Datashe
24V,
Min T
8
2
0
20
‐70 ‐
6
2
0.9
0.7 0
100 2
‐
50
2
0
4.5
0
eet Rev
Typ Max
24 36
1
2
2.5
1
40 60
‐50 ‐30
6.8
2.2 2.6
1 1.1
0.8 0.9
200 300
2
0
‐50
50
110
2.5
270
5.2
0.5
10 20
10 20
1.1 August 6, 20
Units
V
V/μs
mA Di
En
V
mV
µA
mA
ms N
Io
V
V
mV
V
V
uA
uA
% Wsefr
V
°
V So
V S
ns 2
ns 2
012 Page 2
Conditions
isabled
nabled
o external CTRK
out ≤ 8A
With respect to et switching equency
ource 1mA.
Sink 1mA.
20pF load
20pF load
20 of 40
s
K, 0A<
the
Picor Corpo
PI3302‐
Efficiency a
L1=200nH
Ambient T
0 LFM, SiP
Switching
L1=200nH
50
55
60
65
70
75
80
85
90
95
100
0
Efficiency [%]
0
2
4
6
8
10
12
50
Output Current [A]
0
0.2
0.4
0.6
0.8
1
1.2
1
Frequency [MHz]
ration • picorpo
‐X0 Typica
at 25°C
Temperature v
Only
frequency vs.
1 2 3 4
60 70 80Ambient
10V24V36V
2 3 4
12V24V36V
ower.com
l Characte
vs. Load Curren
load current
5 6 7 8
Iout [A]
12Vin24Vin36Vin
90 100 1Temperature [°C]
5 6 7Load [A]
PI33XX‐X0‐LGIZ
ristics
330201
nt Curve
330203
330205
8 9 10
nnn
110 120]
8 9 10
Z Family Datashe
Tota
Tran
LoadCou5A/u
Out
Vou1.0uCou
Power Loss [W]
eet Rev
al Power Loss (in
nsient Response
d Step: 2A to 7At = 4 X 47uF Cerus
tput ripple: Vin
ut = 50mV/Div us/Div t = 4 X 47uF Cer
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0 1 2
[]
1.1 August 6, 20
ncluding externa
e: 24V to 5V
A ramic
n = 24V, Vout
ramic
3 4 5Iout [A
PL (12V)PL (24V)PL (36V)
012 Page 2
al components)
330
= 5.0V at 10A
6 7 8 9A]
21 of 40
330202
0204
330206
10
Picor Corpo
PI3302‐(contin
Output rip
Vout = 50m1.0us/Div Cout = 4 X 4
ration • picorpo
‐X0 Typicaued)
pple Vin = 24V,
mV/Div
47uF Ceramic
ower.com
l Characte
, Vout = 5.0V a
PI33XX‐X0‐LGIZ
eristic
at 5A
330207
Z Family Datashe
Sho
tdela
eet Rev
ort circuit test
ay_fault = 1ms
1.1 August 6, 20
012 Page 2
22 of 40
330208
Picor Corpo
PI3303‐
Electrical
Unless oth
Paramete
Efficiency
Output
Output Vo
Output Vo
Output Vo
Line Regu
Load Regu
Output Vo
Continuou
Current Li
Input Cur
Input Curr
Inrush Inp
Input Curr
Condition
Protection
UVLO Thre
UVLO Hys
OVLO Thr
OVLO Hys
UVLO/OV
UVLO/OV
OVP
Over‐Tem
Over‐Tem
Timing
Switching
Fault Rest
ration • picorpo
‐X0 (12Vou
Specification
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VOUT_DC
VOUT_DC
VOUT_DC
∆VOUT(∆VIN)
∆VOUT(∆IOUT)
VOUT_AC
IOUT_DC
IOUT_CL
IIN_DC
IIN_SS
IIN_Short
VUVLO
VUVLO_HYS
VOVLO
VOVLO_HYS
tf_DLY
tf
VOVP
VOTP
VOTP_HYS
fS
tFR_DLY
Z Family Datashe
teristics
24V, L1=230nH
Min T
9
1
11.82 1
6.5
0
0
0
8.1
4
2
13.57 14
0
37 3
0
1
5
130 1
eet Rev
H
Typ Max
96.5
12.0
12.0 12.18
12 13.0
0.1 0.15
0.1 0.15
60
8
10
4.15
200
300
4.29 15.0
0.37
38.4 40
0.77
128
500
20
135 140
30
1.4
30
1.1 August 6, 20
Units Co
% ViIo
V 0
V ‐4
V
% @
% @
0.
mVp‐p
Io
Co
BW
A
A
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mA ViCi
mA
V
V
V
V
Cycles
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s
c
ns +
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°C
°C
MHz Vi(1)
ms
012 Page 2
onditions
in = 24V, TC = 2out=8A
0 °C <TJ <70°C
40 °C <TJ <125°
@ 25°C 16V<Vin
@ 25°C,
.5A<Iout<8A
out=4A,
out=4x22μF, 2
W
in = 24V, TC = 2out=8A
in=24V, Iout=0in=4x4.7µF ML
Number of the
switching frequ
cycles
+1% overdrive
Above VOUT
in ≥ 18V, Iout ≤)
23 of 40
25°C,
C
n<36V
0MHz
25°C,
0ALCC
e
uency
≤ 8A
Picor Corpo
PI3303‐
(continuUnless oth
Paramete
Input Pow
Input Volt
Input Volt
Input Quie
Soft Start
TRK Active
TRK Offse
Charge Cu
Discharge
Soft‐Start
Enable
Enable Hig
Enable Lo
Enable Th
Enable Pu
Enable Pu
Source Cu
Sink Curre
Sync In (S
Synchroni
SYNCI Thr
SYNCI Pro
Sync Out
SYNCO Hig
SYNCO Lo
SYNCO Ris
SYNCO Fa
ration • picorpo
‐X0 Electric
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PI33XX‐X0‐LGIZ
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< 125C, Vin =2
Symbol
VIN_DC
VIN_SR
IQ_VIN
VTRK
d VTRK_OV
ITRK
ITRK_DIS
tSS
VEN_HI
VEN_LO
VEN_HYS
VEN_PU
VEN_PD
IEN_SO
IEN_SK
∆fSYNCI
VSYNCI
∆φSYNCI
VSYNCO_HI
VSYNCO_LO
tSYNCO_RT
tSYNCO_FT
Z Family Datashe
24V,
Min Typ
15.5
2
0
20
‐70 ‐
6
2
0.9
0.7 0
100 2
‐
50
2
0
4.5
0
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24 36
1
2
2.5
1
40 60
‐50 ‐30
6.8
2.2 2.6
1 1.1
0.8 0.9
200 300
2
0
‐50
50
110
2.5
270
5.2
0.5
10 20
10 20
1.1 August 6, 20
Units Co
V
V/μs
mA Di
En
V
mV
µA
mA
ms N
Io
V
V
mV
V
V
uA
uA
% Wsefr
V
°
V So
V S
ns 2
ns 2
012 Page 2
onditions
isabled
nabled
o external CTRK
out ≤ 8A
With respect to et switching equency
ource 1mA.
Sink 1mA.
20pF load
20pF load
24 of 40
, 0A<
the
Picor Corpo
PI3303‐
Efficiency a
L1=230nH Ambient T
O LFM SiP
Switching fr
50
55
60
65
70
75
80
85
90
95
100
0
Efficien
cy [%]
0
1
2
3
4
5
6
7
8
9
10
50
Load
Current [A]
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1
Frequency [MHz]
ration • picorpo
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60 70 80
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16V24V36V
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4 5 6ut [A]
18Vin, 12Vo24Vin, 12Vo36Vin, 12Vo
90 100 11
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4 5 6
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PI33XX‐X0‐LGIZ
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330301
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330303
330305
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10 120
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Vou1.0uCou
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A Output Rippl
ut = 50mV/Div us/Div ut = 4 X 22uF C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0 1
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1.1 August 6, 20
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6A, 5A/us Ceramic
le: Vin = 24V, V
Ceramic
2 3 4Iout [A
012 Page 2
al components)
Vout = 12V at 8
5 6 7A]
24Vin 12Vout
36Vin, 12Vout
25 of 40
330302
330304
8A
330306
8
Picor Corpo
PI3303‐(continu
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PI33XX‐X0‐LGIZ
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330307
Z Family Datashe
Sho
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ay_fault = 1ms
1.1 August 6, 20
012 Page 2
26 of 40
330308
Picor Corpo
PI3305‐Electrical
Unless oth
Paramete
Efficiency
Output
Output Vo
Output Vo
Output Vo
Line Regu
Load Regu
Output Vo
Continuou
Current Li
Input Cur
Input Curr
Inrush Inp
Input Curr
Condition
Protection
UVLO Thre
UVLO Hys
OVLO Thr
OVLO Hys
UVLO/OV
UVLO/OV
OVP
Over‐Tem
Over‐Tem
Timing
Switching
Fault Rest
ration • picorpo
‐X0 (15 VoSpecification
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er
oltage
oltage Total Re
oltage Range
lation
ulation
oltage Ripple
us Output Curr
mit
rent
rent
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Startup
t Short (Fault
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Time
t Threshold
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PI33XX‐X0‐LGIZ
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< 125C, Vin =2
Symbol
VOUT_DC
∆VOUT(∆VIN)
∆VOUT(∆IOUT)
VOUT_AC
IOUT_DC
IOUT_CL
IIN_DC
IIN_SS
IIN_Short
VUVLO
VUVLO_HYS
VOVLO
VOVLO_HYS
tf_DLY
tf
VOVP
VOTP
VOTP_HYS
fS
tFR_DLY
Z Family Datashe
cteristics
24V, L1=230nH
Min T
9
1
14.78 1
10.0
0
0
0
8.1
4
2
16.38 1
0
37 3
0
1
5
130 1
eet Rev
H
Typ Max
97.2
15.0
15.0 15.23
15 16
0.1 0.15
0.1 0.15
60
8
10
4.12
200
300
17.2 18.1
0.37
38.4 40
0.77
128
500
20
135 140
30
1.5
30
1.1 August 6, 20
Units Co
% Vi Io
V 10
V ‐4
V
% @
18
% @
8A
mVp‐p
Io
Co
20
A
A
A ViIo
mA ViCi
mA
V
V
V
V
Cycles
N
s
c
ns +
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°C
°C
MHz Vi(1)
ms
012 Page 2
onditions
in = 24V, TC = 2out = 10 A
0 °C <TJ <70°C
40 °C <TJ <125°
@ 25°C
8.5V<Vin<36V
@ 25°C, 0.5A<Io
A
out=4A,
out=4x22μF,
0MHz BW
in = 24V, TC = 2out=8A
in=24V, Iout=0in=4x4.7µF ML
Number of the
switching frequ
cycles
+1% overdrive
Above Vout
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27 of 40
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C
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0ALCC
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Input Volt
Input Volt
Input Quie
Soft Start
TRK Active
TRK Offse
Charge Cu
Discharge
Soft‐Start
Enable
Enable Hig
Enable Lo
Enable Th
Enable Pu
Enable Pu
Source Cu
Sink Curre
Sync In (S
Synchroni
SYNCI Thr
SYNCI Pro
Sync Out
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SYNCO Lo
SYNCO Ris
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VIN_DC
VIN_SR
IQ_VIN
VTRK
d VTRK_OV
ITRK
ITRK_DIS
tSS
VEN_HI
VEN_LO
VEN_HYS
VEN_PU
VEN_PD
IEN_SO
IEN_SK
∆fSYNCI
VSYNCI
∆φSYNCI
VSYNCO_HI
VSYNCO_LO
tSYNCO_RT
tSYNCO_FT
Z Family Datashe
24V,
Min T
18.6
2
0
20
‐70 ‐
6
2
0.9
0.7 0
100 2
‐
50
2
0
4.5
0
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Typ Max
24 36
1
2
2.5
1
40 60
‐50 ‐30
6.8
2.2 2.6
1 1.1
0.8 0.9
200 300
2
0
‐50
50
110
2.5
270
5.2
0.5
10 20
10 20
1.1 August 6, 20
Units
V
V/μs
mA Di
En
V
mV
µA
mA
ms N
Io
V
V
mV
V
V
uA
uA
% Wsefr
V
°
V So
V S
ns 2
ns 2
012 Page 2
Conditions
isabled
nabled
o external CTRK
out ≤ 8A
With respect to et switching equency
ource 1mA.
Sink 1mA.
20pF load
20pF load
28 of 40
s
, 0A<
the
Picor Corpo
PI3305‐
Efficiency a
L1=230nH
Ambient T
O LFM, SiP
Switching f
50
60
70
80
90
100
0
Efficiency [%]
0
1
2
3
4
5
6
7
8
9
10
50
Output Current [A]
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1
Frequency (MHz)
ration • picorpo
‐X0 Typica
t 25°C
Temperature v
P Only
frequency vs. l
1 2 3
18.6V
24V
36V
60 70 80Ambie
18.6V
24V
36V
2 3
18.6V
24V
36V
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4 5LOAD [A]
0 90 100ent Temperature [
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PI33XX‐X0‐LGIZ
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330503
330505
6 7 8
110 120[°C]
6 7 8
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3
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Vou1usCou
Power Loss [W]
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d Step: 2A to 6Aus ut = 4x22µF Cera
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ut = 100mV/Divs/Div ut = 4x22µF Ce
0.0
1.0
2.0
3.0
4.0
5.0
0 1
1.1 August 6, 20
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A
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v
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24V
36V
012 Page 2
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= 15V at 8A
5 6 7
29 of 40
330502
330504
330506
8
Picor Corpo
PI3305‐(continu
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PI33XX‐X0‐LGIZ
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330507
Z Family Datashe
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1.1 August 6, 20
012 Page 3
30 of 40
330508
Picor Corpo
FunctioThe PI33XX
regulators
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For basic o
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ENABLE (E
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PI3311‐X0‐LGIZ
PI3312‐X0‐LGIZ
PI3301‐X0‐LGIZ
PI3302‐X0‐LGIZ
PI3303‐X0‐LGIZ
PI3305‐X0‐LGIZ
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1.1 August 6, 20
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2.5V
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5.0V
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15V
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“Soft Start Adju
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012 Page 3
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If VIN
thresh
PI33X
switch
cycles
Other
and s
opera
the O
The O
be re
versio
Outp
The P
Voltag
voltag
excee
will co
issue
once
thresh
fault i
cleare
I2C da
Over
The i
preve
therm
Protec
regula
enter
soft‐st
Over‐T
OTP fa
and c
via I2C
Pulse
PI33X
light l
EAO f
condit
single
eet Rev
t Over Voltag
exceeds the in
hold (VOVLO), w
XX will compl
hing. If VIN
s, the PI33XX
rwise, the syst
sets an OVLO
ation when the
VLO threshold
OVLO fault is s
ead and clea
ons only) via I2C
put Over Volta
PI33XX family
ge Protection
ge sensitive
eds 20% of its
omplete the c
an OVP fault.
the output
hold and afte
is stored in a F
ed (PI33XX‐20
ata bus.
Temperature
nternal packa
ent system co
mal maximum
ction Thresho
ator will comp
a low power
tart when the
Temperature
ault is stored i
leared (PI33XX
C data bus.
e Skip Mode (
XX features a P
loads. The reg
falls below a
tions and com
e pulses or sev
1.1 August 6, 20
ge Lockout
nput Over Volt
while the contr
ete the curre
recovers wi
X will resume
tem will enter
fault. The s
e input voltage
d and after the
stored in a Fau
ared (PI33XX‐
C data bus.
age Protectio
y is equipped
(OVP) to preve
devices. If t
set regulated
current cycle,
The system w
voltage falls
er Fault Restar
Fault Register a
and PI33XX‐2
e Protection
age temperatu
omponents fr
m. If the
old (OTP) is e
plete the curr
r mode, set a
e internal temp
Restart Hyste
in a Fault Regis
X‐20 and PI33X
(PSM)
PSM to achiev
gulators are se
PSM thresho
mponent value
veral consecut
012 Page 3
tage Lockout (
roller is runnin
ent cycle and
thin 128 swi
normal oper
r a low power
system will re
e falls below 9
Fault Restart
ult Register an
‐20 and PI33
on
with output
ent damage to
he output v
value, the reg
stop switchin
will resume ope
s below the
rt Delay. The
and can be rea
21 versions on
ure is monitor
rom reaching
Over Tempe
xceeded (VOTP
ent switching
fault flag, an
perature falls
eresis (VOTP_HYS
ster and can b
XX‐21 versions
ve high efficie
tup to skip pu
old. Dependi
s, this may re
tive pulses fol
32 of 40
OVLO)
ng, the
d stop
itching
ration.
r state
esume
98% of
Delay.
nd can
3XX‐21
t Over
o input
voltage
gulator
ng and
eration
OVP
e OVP
ad and
ly) via
red to
their
erature
P), the
cycle,
nd will
below
S). The
e read
s only)
ncy at
ulses if
ng on
sult in
llowed
Picor Corpo
by skippe
reduces ga
efficiency.
rises above
Variable F
Each PI33X
frequency,
(see Table
and load
application
accommod
stretching
preserved
range ther
Parallel O
Paralleling
increase t
power rail
By connec
module to
equally. W
connected
during sof
released t
Also, any f
other regu
ration • picorpo
ed pulses. S
ate drive pow
The regulator
e the Skip Mod
Frequency Op
XX is preprogr
, with respect
5), to operate
variations.
ns, the base
date these ext
the frequen
throughout t
refore maintain
Operation
multiple PI33
the output cu
and reduce ou
Figure 3 ‐ PI33X
cting the EAO
ogether the u
When the TR
together, the
ft‐start and a
o allow the u
fault event in a
ulators. The tw
ower.com
Skipping cycle
wer and impro
r will leave PSM
de threshold.
peration
rammed to a
to the power
e at peak efficie
At low line
frequency w
treme operatin
ncy, the ZVS
the total inpu
ning optimum
3XX modules c
urrent capabil
utput voltage r
XX parallel opera
pins and SGN
units will sha
RK pins of e
e units will tra
ll unit EN pin
units to start
any regulator
wo regulators
PI33XX‐X0‐LGIZ
es significantl
oves light loa
M once the EAO
base operatin
stage inducto
ency across lin
and high loa
will stretch t
ng ranges. B
S operation
ut line voltag
efficiency.
can be used t
ity of a singl
ripple.
ation
ND pins of eac
re the curren
each unit ar
ack each othe
ns have to b
(See Figure 3
will disable th
will be out o
Z Family Datashe
ly
d
O
ng
or
e
d
o
By
is
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h
nt
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er
e
).
e
of
phase
to Sw
To pr
the e
Good
regula
be p
regula
config
SYNCI
open‐
regula
system
config
the fly
enter
Multi‐
(PI33X
basic
about
regula
PI33XX
I2C BuPI33X
interfa
polari
freque
one ti
Also, t
Vout
develo
and n
PI33X
telem
Fault
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e with each ot
itching Freque
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ntire operatio
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ator’s SYNCI p
laced betwee
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guration, at sy
I low forcing t
‐loop startup
ators reach reg
m is now
guration which
y, when any of
variable frequ
‐phasing three
XX‐20 and PI33
single‐phase
t how to pro
ator, please
XX‐2X Multi‐Pha
us(PI33XX‐2XX‐20 and PI
ace that enabl
ity (from high
ency synchro
ime programm
the PI33XX‐20
margining v
opment (settin
not retained b
XX‐21 also hav
metry:
registry list:
Over temp
Fast/Slow c
Output volt
Input overv
Input unde
1.1 August 6, 20
ther reducing
ency Synchroni
onization betw
onal frequency
must be conn
in and a 2.5kΩ
en SYNCO ret
pin, as shown
ystem soft‐star
the lead regula
p synchroniza
gulation, SYNC
synchronized
h allows the s
f the individua
uency mode in
e or more re
3XX‐21 only) w
design. For
ogram phase
refer to Pico
ase Design Pro
20 and PI33XX
33XX‐21 prov
les the user to
h to low asser
nization phas
mable options t
0 and PI33XX‐2
via I2C that
ngs stored in v
y the device).
ve the option
erature protec
current limit
tage high
voltage
ervoltage
012 Page 3
output ripple
ization).
ween regulator
y range, the P
nected to the
Ω Resistor, R1,
turn and the
in Figure 3.
rt, the PGD pin
ator to initiali
ation. Once
CI is released an
in a closed
ystem to adju
l regulators be
the loop.
egulators is po
with no change
r more inform
delays withi
or application
ocedure.
X‐21 only)
vide an I2C
program the E
rtion) and swi
e/delay. Thes
to the device.
21 allow for dy
is useful d
volatile memor
The PI33XX‐2
for extended
ction
33 of 40
(refer
s over
Parallel
e lead
, must
e lead
In this
n pulls
ze the
e the
nd the
d‐loop
ust, on
egin to
ossible
to the
mation
n the
note
digital
EN pin
itching
se are
ynamic
during
ry only
20 and
d fault
Picor Corpo
For more
interface
PI33XX‐2X
Applica
Output Vo
The PI33X
common o
and 15V.
to offset a
maximum
connected
device’s o
nominal s
PI3311‐X0
of 1V).
PI
PI
PI
PI
PI
PI
Table
The remot
to the VO
voltage off
voltage div
Fig
ration • picorpo
information a
please refer
I2C Interface G
tion Descr
oltage Progra
X family of B
output voltages
A post‐packag
ny resistor div
output accur
from the ADJ
utput can be
set voltage (w
which can on
Device
I3311‐X0‐LGIZ
I3312‐X0‐LGIZ
I3301‐X0‐LGIZ
I3302‐X0‐LGIZ
I3303‐X0‐LGIZ
I3305‐X0‐LGIZ
e 3 ‐ PI33XX fam
te pin (REM) s
UT pin, if not
fset. Figure 4 s
vider network.
ure 4 ‐ Internal r
ower.com
about how to
to Picor app
Guide.
ription
amming
uck Regulator
s: 1.0V, 2.5V, 3
ge trim step is
ider network e
acy. With a
J pin to SGND
varied above
with the exce
nly be above t
Output Vo
Set R
1.0V 1.0
2.5V 2.
3.3V 2.
5.0V 3.
12V 6.5
15V 10.
mily output voltag
should always
used, to prev
shows the inte
resistor divider n
PI33XX‐X0‐LGIZ
utilize the I2C
plication note
rs provides six
3.3V, 5.0V, 12V
s implemented
errors ensuring
single resistor
or REM, each
or below the
eption of the
he set voltage
oltage
Range
00 to 1.4
0 to 3.1
3 to 4.1
3 to 6.5
5 to 13.0
0 to 16.0
ge ranges
be connected
vent an output
ernal feedback
network
Z Family Datashe
C
e
x
V
d
g
r
h
e
e
e
d
t
k
R1, R
R_low
the d
outp
regul
PI3
PI3
PI3
PI3
PI3
PI3
By c
range
adjus
or R
equa
value
If, fo
shou
For t
and u
the P
divid
R1=4
these
as fo
The
availa
eet Rev
R2, R3 and R4
w and R_high
designer can a
ut. The in
lator is listed b
Device
3311‐X0‐LGIZ
3312‐X0‐LGIZ
3301‐X0‐LGIZ
3302‐X0‐LGIZ
3303‐X0‐LGIZ
3305‐X0‐LGIZ
Table 4 ‐ PI
choosing an o
es stated in
sted up or dow
R_low value,
ations can be u
es:
112
or example, a
uld choose the
this example,
use Equation (
PI3302’s outp
er network
4.53Ωk, R2=1.1
e values in to
llows:
1.57 64value calcula
able for purch
1.1 August 6, 20
are all interna
h are external
add to modify
nternal resisto
below in Table
R1 R2
1k Open
1.5k 1.0k
2.61k 1.13
4.53k 1.13
11.0k 1.0k
14.0k 1.0k
I33XX Internal d
output voltage
Table 3, VO
wn by selectin
respectively
used to calculat
11 1211 116.0V output
e proper regu
we will selec
(1) to calculate
ut. From Ta
values for
13kΩ, and R3
Equation (1),
1.0 14.53 11.1ated is ideal
hase; therefor
012 Page 3
l 1.0 % resisto
resistors for
y VOUT to a d
or value for
4.
R3 R
n 0 1
k 2.0k 1
k 3.0k 1
k 3.0k 1
k 3.0k 1
k 3.0k 1
divider values
e value withi
OUT can simp
g the proper R
y. The foll
te R_high and
3 3.
is needed, the
ulator from Ta
ct the PI3302
e R_high to inc
able 4, the re
the PI3302
= 3.0kΩ. Ins
R_high is calc
113 3.0 .and may n
e, select a sta
34 of 40
ors and
which
desired
each
R4
100
100
100
100
100
100
in the
ply be
R_high
lowing
R_low
1
2
e user
able 3.
(5.0V)
crease
esistor‐
are:
serting
ulated
ot be
andard
Picor Corpo
1% value c
1%, resisto
by using th
Soft‐Start
The TRK
regulator’s
regulators
internal 10
a minimum
PI33XX reg
capacitor t
increased
used to ca
soft‐start t C
Where, tTR
internal ch
for limits).
There is
tracking
proportion
startup, s
together.
connected
at the sam
For Direct
highest ou
the maste
through a
the slave’s
ration • picorpo
close to the v
or is a standar
he voltage divid
t Adjust and T
pin offers a
s soft‐start tim
. The soft‐sta
00nF and a fixe
m startup tim
gulators. By a
to the TRK pin
further. The
alculate the pr
times: tRK is the soft‐s
harge current (
typically eith
implemented
nal tracking be
simply conne
This type
regulators to
e time (see Fig
Figure 5 ‐ PI33X
Tracking, cho
utput voltage
r to the TRK
divider (Figur
s feedback divid
VOU
VOU
Maste
VOUT
(a)
(b)
ower.com
alue calculate
rd value. Chec
der equation.
Tracking
a means to
me or to track w
art slope is co
ed charge curr
me of 2ms (t
dding an addit
n, the soft‐star
following equ
oper capacitor
I 100xstart time and
see Electrical C
her proportio
within a
etween severa
ect all devic
of tracking
startup and re
gure 5 (a)).
XX tracking meth
oose the regu
as the maste
pin of the ot
re 6) with the
der (see Table
UT 1
UT 2
er VOUT
T 2
PI33XX‐X0‐LGIZ
d. A 1.56kΩ,
ck your results
increase the
with additiona
ntrolled by an
rent to provide
ypical) for al
tional externa
rt time can be
uation can be
r for a desired
x10 , ITRK is a 50uA
Characteristics
nal or direct
design. For
l regulators at
es TRK pins
will force al
each regulation
hods
lator with the
r and connect
her regulators
same ratio as
4 for values).
t
Z Family Datashe
,
s
e
l
n
e
l
l
e
e
d
A
s
t
r
t
s
l
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t
s
s
Figu
All co
with
demo
shou
toget
Indu
The
induc
perfo
value
devic
eet Rev
ure 6 ‐ Voltage d
onnected regu
this metho
onstrated in Fi
uld have the
ther to work p
uctor Pairing
PI33XX utiliz
ctor has been
ormance. Tabl
e and part n
ce and are man
Device
PI3311‐X0‐LGIZ
PI3312‐X0‐LGIZ
PI3301‐X0‐LGIZ
PI3302‐X0‐LGIZ
PI3303‐X0‐LGIZ
PI3305‐X0‐LGIZ
Table 5
PI
S
1.1 August 6, 20
divider connectio
ulators’ soft‐st
od. Direct t
igure 5 (b). Al
ir Enable (EN
properly.
zes an exter
optimized for
le 5 details th
number utilize
nufactured by
Inductor
[nH]
120
200
200
200
230
230
‐ PI33XX Inducto
Master VO
R
R
SGND
TRK
I33XX
Slave
012 Page 3
ons for direct tra
tart slopes wil
tracking timi
ll tracking regu
N) pins conn
rnal inductor.
maximum effi
he specific ind
ed for each P
Coiltronics.
Inductor
Part Number
TBD‐120‐R
FPT705‐200‐R
FPT705‐200‐R
FPT705‐200‐R
FPT705‐230‐R
FPT705‐230‐R
or pairing
OUT
1
2
35 of 40
acking
l track
ng is
ulators
nected
. This
ciency
ductor
PI33XX
R
R
R
R
R
Picor Corpo
Input and
The PI33XX
as well a
capacitors
frequency
PI33XX wi
current fro
when the
During the
replenishe
impedance
converter,
average c
replenishin
been chose
Device
VIN
(V
PI3311
24
PI3312
24
PI3301
24
PI3302
24
PI3303
24
PI3305
24
ration • picorpo
d Output Filte
X requires inp
as low impe
to ensure p
decoupling f
ll draw nearly
om the low im
main high s
e time the high
d from the b
e is high at the
the bulk capa
current into
ng the cerami
en to be 100µF
N
V)
ILOAD (A)
CINPUBulk
Elec
4 10 100µ
50V
5
4 10 100µ
50V
5
4 10 100µ
50V5
4 10 100µ
50V
5
4 8 100µ
50V
4
4 8 100µ
50V
4
MURATA PAR
GRM188R71C
GRM319R71H
GRM31CR60J
ower.com
er Considerat
put bulk storag
dance ceram
proper start
for the powe
y all of the h
mpedance cera
ide MOSFET
side MOSFET
bulk capacitor
e switching fre
acitor must su
the convert
c capacitors. T
F so that the P
UT
k
c.
CINPUT Ceramic
X5R
µF
V
4X4.7µF
50V
µF
V 4X4.7µF
µF
V 4X4.7µF
µF
V 4X4.7µF
µF
V 4X4.7µF
µF
V 4X4.7µF
Table
RT NUMBER
C105KA12D 1
H104KA01D 0
107ME39L 1
Ta
PI33XX‐X0‐LGIZ
tions
ge capacitance
ic X5R input
up and high
er stage. The
high frequency
mic capacitors
is conducting
is off, they are
r. If the input
equency of the
pply all of the
ter, including
This value has
I33XX can
COUTPUT Ceramic
X5R
CINPRipp
Curre
(IRM
8X100µF
2X1 µF
1X0.1 µF
0.5
4X100µF
2X1 µF
1X0.1 µF
1
4X100µF
2X1 µF
1X0.1 µF
1.0
4X100µF
2X1 µF
1X0.1 µF
1.2
4X22µF
2X1 µF
1X0.1 µF
1.3
4X22µF
2X1 µF
1X0.1 µF
1.3
6 ‐ Recommend
DESCRIPTION
1uF 16V 0603 X7
0.1uF 50V 1206 X
100uF 6.3V 1206
ble 7 ‐ Capacitor
Z Family Datashe
e
t
h
e
y
s
.
e
t
e
e
g
s
start
outp
soft
impe
capa
ripple
not b
capa
recom
used
trans
capa
Table
ceram
PUT
ple
ent
MS)
COUTPUT Ripple
Current
(IRMS)
(
5 0.8
1.75
05 1.625
2 1.5
3 1.36
8 1.2
ded input and ou
N MURATA
R GRM31C
X7R GRM31C
6 X5R GRM31C
r manufacturer p
eet Rev
up into a fu
ut capacitive
start capac
edance is 50 O
citor should b
e current in th
be a concern if
citors are
mmended inp
for the vario
sient respons
citor, and inp
e 7 includes th
mic capacitors
Input
Ripple
(mVpp)
Outpu
Rippl
(mVpp
120 20
100 15
150 50
100 24
200 40
125 33
220 50
140 30
275 100
150 60
280 150
160 75
utput capacitanc
A PART NUMBE
CR71H475KA12K
CR61A476ME15
CR61E226KE15L
part numbers
1.1 August 6, 20
ull resistive lo
load with th
citor when
Ohms at 1MH
be approximate
his capacitor i
f the input rec
used. Table
put and outpu
ous models a
se, RMS rip
put and outp
he recommend
.
ut
e
p)
Transient
Deviation
(mVpk)
‐/+40
‐/+80
‐/+100
‐/+170
‐/+300
‐/+400
ce
ER DESCRIP
K 4.7uF 50V 1
L 47uF 10V 1
22uF 25V 1
012 Page 3
oad and supp
e default min
the input s
Hz. The ESR fo
ely 20mΩ. The
s small, so it s
commended ce
e 6 shows
ut capacitors
as well as exp
pple currents
put ripple vol
ded input and o
Recovery
Time
(µs)
L
S
(Sle
40 (5
25 (10
20 (10
30 (5
30 (10
30 (10
PTION
1206 X7R
206 X5R
206 X5R
36 of 40
ly the
nimum
source
or this
e RMS
should
eramic
the
to be
pected
s per
ltages.
output
Load
Step
(A)
ew/µs)
5
A/µs)
5
0A/µs)
5
0A/µs)
5
A/µs)
4
0A/µs)
4
0A/µs)
Picor Corpo
Layout
To optimiz
performan
considerat
resistance
along with
parasitic re
A typical b
The poten
resistance
below.
The path b
particular
flowing thr
Figure 10,
length bet
shorter pa
parasitics c
Fig
ration • picorpo
Guidelines
ze maximum
nce from a
tions are n
and minimizin
proper compo
esistance and i
buck converter
tial areas of h
are the circui
Figure 9 ‐ Typi
between the C
importance s
rough both of t
schematically
tween input a
ath lessens th
can have on th
gure 10 ‐ Curren
ower.com
s
efficiency and
PI33XX de
ecessary. Re
ng high curren
onent placeme
nductance.
r circuit is show
igh parasitic in
t return paths
ical Buck Conver
OUT and CIN c
since the AC
them when Q1
y, shows the
and output ca
e effects that
e PI33XX perfo
nt flow: Q1 close
PI33XX‐X0‐LGIZ
d a low noise
esign, layout
educing trace
nt loop returns
ent will reduce
wn in Figure 9
nductance and
s, shown as LR
rter
capacitors is of
currents are
1 is turned on.
reduced trace
apacitors. The
t copper trace
ormance.
ed
Z Family Datashe
e
t
e
s
e
.
d
R
f
e
e
e
e
Whe
curre
to re
and
induc
CIN i
induc
when
betw
minim
The r
Figur
COUT
curre
used
eet Rev
n Q1 is on an
ent is used to
echarge the C
Q2 is on, the
ctor and the C
s also being re
ctance is imp
n Q1 turns o
ween the CIN
mize switching
Figure 11
recommended
re 11, illustrate
T (and VIN an
ent. This optim
on the PI33XX
Figure 12 ‐
placem
1.1 August 6, 20
nd Q2 is off, th
satisfy the sta
OUT capacitor
e load current
COUT capacito
echarged by th
ortant to min
ff. Also, the
loop and CO
g and GND nois
1 ‐ Current flow:
d component p
es the tight pa
nd VOUT) for
mized layout
X evaluation bo
‐ Recommended
ment and metal
012 Page 3
he majority of
atic output loa
rs. When Q1
t is supplied b
r. During this p
e VIN. Low CIN
nimize peak v
e difference in
OUT loop is vi
se.
: Q2 closed
placement, sho
ath between CI
the high AC
is the same t
oard.
d component
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