exploiting architecture for verification dave whipp
DESCRIPTION
A HW Development Flow Big Paper Spec Design Verification RTL Testbench Checkers Tests Scoreboard Assertions C Model Synthesis Directed Randoms BFMs, TLMs Clocks, Resets Assertions ISS Model Coverage Debug (BAD)TRANSCRIPT
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Exploiting ArchitectureFor Verification
Dave Whipp
![Page 2: Exploiting Architecture For Verification Dave Whipp](https://reader035.vdocuments.us/reader035/viewer/2022062401/5a4d1b557f8b9ab0599a91cb/html5/thumbnails/2.jpg)
Architecture For Verification Simplify the Design
– Reduce corner cases– Decoupled State Machines– Focus Complexity on Performance
• Tradeoff Performance Vs Schedule
Provide Verification-Friendly Work Products– Models– Test benches– Tests
![Page 3: Exploiting Architecture For Verification Dave Whipp](https://reader035.vdocuments.us/reader035/viewer/2022062401/5a4d1b557f8b9ab0599a91cb/html5/thumbnails/3.jpg)
A HW Development FlowBig Paper Spec
Design
Verification
RTL
Testbench Checkers Tests
Scoreboard
Assertions
C Model
Synthesis
Directed
RandomsBFMs,
TLMs
Clocks, ResetsAssertions
ISS Model
CoverageDebug
(BAD)
![Page 4: Exploiting Architecture For Verification Dave Whipp](https://reader035.vdocuments.us/reader035/viewer/2022062401/5a4d1b557f8b9ab0599a91cb/html5/thumbnails/4.jpg)
A HW Development FlowBig Paper Spec
Design
Verification
RTL
Testbench Checkers Tests
Scoreboard
Assertions
C Model
Synthesis
Directed
RandomsBFMs,
TLMs
Clocks, ResetsAssertions
ISS Model
CoverageDebug
(BAD)
![Page 5: Exploiting Architecture For Verification Dave Whipp](https://reader035.vdocuments.us/reader035/viewer/2022062401/5a4d1b557f8b9ab0599a91cb/html5/thumbnails/5.jpg)
A HW Development Flow (Better)
RTL Scoreboards
Synthesis
Randoms
Clocks, Resets
Design
Verification
Testbench
Small Paper Spec
ISS Model ESL
C Model
Interfaces
Assertions
Directed Tests BFMs
TLMs
Validation
Assertions
Triage
Debug
Coverage
Coverage
![Page 6: Exploiting Architecture For Verification Dave Whipp](https://reader035.vdocuments.us/reader035/viewer/2022062401/5a4d1b557f8b9ab0599a91cb/html5/thumbnails/6.jpg)
What Type of Model?
A EB C D F G
D
GA
BE
CF
How do we model that these are equivalent?
ISS:
TLM:
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Exploitation of Executable Models Product Development
– Enable SW development– Validate the Architecture
Verification Bootstrapping– Validate Tests– Functional Checkers– Validate Assertions– Architectural Coverage
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Design Verification Testbenches
TransactionProducer
ScenarioGenerator
CoverageModel
DUT
TransactionConsumer
ScenarioChecker
BFM BFM
UTFmodel
![Page 9: Exploiting Architecture For Verification Dave Whipp](https://reader035.vdocuments.us/reader035/viewer/2022062401/5a4d1b557f8b9ab0599a91cb/html5/thumbnails/9.jpg)
Architectural Validation Testbenches
TransactionProducer
ScenarioGenerator
CoverageModel
UTFmodel
TransactionConsumer
ScenarioChecker
![Page 10: Exploiting Architecture For Verification Dave Whipp](https://reader035.vdocuments.us/reader035/viewer/2022062401/5a4d1b557f8b9ab0599a91cb/html5/thumbnails/10.jpg)
How To Reuse Architectural Tests
Architectural
Mic
ro A
rchi
tect
ural
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Architectural Bringup Tests
Architectural
Mic
ro A
rchi
tect
ural
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Micro-architectural Directed Tests
Architectural
Mic
ro A
rchi
tect
ural
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Micro-architectural Directed Tests
Shallow Features
Dee
p In
tera
ctio
ns
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Constrained Random Tests
Shallow Features
Dee
p In
tera
ctio
ns
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Random Directed Tests
Shallow Features
Dee
p In
tera
ctio
ns
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Testing using GraphsShape
Line
Triangle
Solid
Stipple
Short Fat
Long Skinny Filled
Outline
Aspect Body
Dashed
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Micro-Architectural Tests
Address Cacheable
Page
Evict dirty
Evict about-to-be-needed
Reuse
New
No
Yes
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Conclusion Architects must create Executable
Representations– Validated by Architects– Reused by Verifiers
Not Just Models– Testbenches and VIP– Self-Checking Tests (Directed Random)
Traditional Models serve Multiple Roles– Checkers– Assertions– Coverage